JPH0927732A - Programmable capacitor array - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure the ratio precision of capacitors and improve set resolution, and to suppress an increase in the total capacity value of capacitors. SOLUTION: The programmable capacitor array 30 consists of switches SW20, SW21, SW22, and SW23 connected in parallel between terminals 31 and 32 and four capacitors Cs, C21, C22, and C23 connected to those switches SW20-SW23 in series. The capacitors C21-C23 are constituted by using unite capacitors Cu and weighted in binary notation like the capacitor C21=Cu, C22=2Cu, and C23=4Cu. The capacitor Cs has a smaller capacitance than a unit capacitor Cu. The capacitors Cs and C21-C23 are switched selectively by the switches SW20-SW23.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable capacitor array used in a switched capacitor circuit such as a switched capacitor filter.

[0002]

2. Description of the Related Art Generally, a switched capacitor circuit such as a switched capacitor filter utilizes the characteristic that its circuit characteristic can be determined by the capacitance ratio of the capacitor.
There is a programmable switched capacitor circuit using a programmable capacitor array in which a plurality of capacitors are connected in parallel and an arbitrary capacitor is selected to change the capacitance value.

FIG. 6 is a diagram showing the configuration of a conventional programmable capacitor array having a 3-bit configuration having a binary-weighted capacitance value. As shown in FIG. 6, the programmable capacitor array 10 includes terminals 11,
Switches SW1, SW2, S connected in parallel between 12
It is composed of W3 and three capacitors C1, C2, C3 connected in series with these switches SW1 to SW3. Each of the above three capacitors has C1 = 2 ⁰ C
u = Cu, C2 = 2 ¹ Cu = 2 Cu, and C3 = 2 ²
Binary weighting is performed such as Cu = 4Cu.
The switches SW1 to SW3 are for selectively switching the capacitors C1 to C3.

Here, the capacitor Cu is a unit capacitor having a constant shape and capacitance value as shown in FIGS. 7 (a) and 7 (b). In order to ensure the ratio accuracy of capacitors, in switched capacitor circuits,
Each unit capacitor is configured using such a unit capacitor. This unit capacitor is realized by a device such as a two-layer polysilicon structure or a MOS structure in the LSI process.

FIG. 7A is a plan view of the unit capacitor Cu, and FIG. 7B is a side view. In the figure, the unit capacitor is composed of an upper electrode 13 and a lower electrode 14, and a dielectric 15 such as a silicon oxide film is inserted between both electrodes. Further, in the figure, W and L respectively represent the width and length of the upper electrode 13, and t _0x represents the thickness of the silicon oxide film 15.

FIG. 8 is a diagram showing a circuit configuration example in which the programmable capacitor array 10 of FIG. 6 is applied to a gain control circuit. The terminal 11 of the programmable capacitor array 10 is connected to the input signal terminal 16 and the reference voltage input terminal 17 via the input signal sampling switches SW11 and SW12. The stabilization switch SW13 is provided between the terminal 12 and the output terminal 18.
, The feedback capacitor Cf, and the operational amplifier 19 having the illustrated polarity.
Is connected. The non-inverting input terminal of the operational amplifier 19 is connected to the reference voltage input terminal 17.

FIG. 9 is a diagram showing an image of an arrangement example of capacitors in the circuit configuration of FIG. In the circuit having such a configuration, the gain is determined by the ratio of the total capacitance value C _all of the selected capacitors in the programmable capacitor array to the capacitance value of the feedback capacitor Cf, C _all / C _f . Assuming that in the feedback capacitor Cf with one of the unit capacitors Cu, gain setting range, gain _{= C all / C f = C} 1 / C f ~ (C 1 + C 2 + C 3) / C f = 1~7 And the setting resolution at that time is 1. In addition, C ₁ +
C ₂ + C ₃ is the capacitance value of the capacitors C1, C2, and C3, respectively.

Here, if a setting resolution of 0.5 is required, in the conventional technique, as shown in FIG.
A method is conceivable in which the feedback capacitor is Cf = 2Cu and the programmable capacitor array 20 is C4 = 2 ³ Cu = 8Cu to have a 4-bit configuration. FIG.
It is the figure which showed the image of the example of arrangement | positioning of the capacitor in this case.

[0009]

However, in the method using the circuit having the configuration shown in FIG. 10, the total capacitance value of the capacitors forming the circuit is 8 Cu (see FIGS. 8 and 9) to 17
The increase in cost due to the increase to Cu (see FIG. 10 and FIG. 11) and the doubling or more is a problem.

In order to avoid such a problem, FIG.
In the above circuit configuration, a method of halving the area and the capacitance value of the unit capacitor Cu to prevent an increase in the total capacitance value of the capacitors forming the circuit can be considered. However, if the unit capacitor is halved, there is a problem that the ratio accuracy of the capacitor deteriorates.
Then, if the ratio accuracy of the capacitor deteriorates, the gain control circuit has a problem that the gain accuracy cannot be obtained.

The present invention has been made in view of the above problems, and it is a programmer that secures the ratio accuracy of the capacitors, improves the setting resolution, and minimizes the increase in the total capacitance value of the capacitors forming the circuit. It is an object to provide a capacitor array.

[0012]

That is, the present invention uses a unit capacitor and comprises at least two first capacitance means having a binary weighted capacitance value and at least two first capacitance means. In a programmable capacitor array comprising at least two first selecting means connected in series to each other, a second capacitance means connected in parallel with the first capacitance means and having a smaller capacitance unit than the unit capacitor. And a second selection means connected in series with the second capacitance means for selecting the second capacitance means.

A programmer capacitor array according to the present invention uses a unit capacitor, and includes at least two first capacitance means having a binarized weighted capacitance value and a second capacitance having a smaller capacitance unit than the unit capacitor. The means are connected in parallel. Further, a first selection means and a second selection means are connected in series to each of the at least two first capacitance means and the second capacitance means. The first and second capacitance means are selected by these first and second selection means. As a result, the setting resolution of the capacitor can be improved.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit configuration diagram of a programmable capacitor array of a 4-bit configuration having a binary weighted capacitance value according to the present invention.

Referring to FIG. 1, the programmable capacitor array 30 of the present invention includes switches SW20, SW21, SW22, and SW23 between terminals 31 and 32, and four capacitors Cs connected in series with these switches SW20 to SW23. , C21, C22, C23 are connected in parallel. The capacitors C21 to C23
Is formed by using a unit capacitor Cu, and capacitors C21 = 2 ⁰ Cu = Cu and C22 = 2 ¹ Cu =
2Cu, and C23 = 2Cu ² Cu = 4Cu. Also, the capacitor Cs
Are provided for improving the setting resolution having a capacitance value smaller than that of the unit capacitor Cu. Switch S above
W20 to SW23 are the capacitors Cs and C21 to C21.
It is for selectively switching 23.

FIG. 2 is a diagram showing a circuit configuration example in which the programmable capacitor array 30 of FIG. 1 is applied to a gain control circuit. The terminal 31 of the programmable capacitor array 30 is connected to the input signal terminal 16 and the reference voltage input terminal 17 via the input signal sampling switches SW11 and SW12. A stabilizing switch SW13 for stabilizing the DC characteristics of the circuit, a feedback capacitor Cf, and an operational amplifier 19 are connected between the terminal 32 and the output terminal 18. The non-inverting input terminal of the operational amplifier 19 is the reference voltage input terminal 1
7 is connected.

FIG. 3 is a diagram showing an image of an arrangement example of capacitors in the gain control circuit of FIG. Here, in the gain control circuit of FIG.
In consideration of obtaining the setting resolution of 0.5, when the feedback capacitor Cf = Cu, it is realized by setting the capacitance value of the capacitor Cs to 1/2 of the unit capacitor.

At this time, for example, capacitors C21 and Cs
When bets are selected by the switch SW21 and SW20 are turned on, the gain of that time, gain _{= C all / C f = (} C21 + Cs) / Cf = (Cu + 1 / 2Cu) / Cu = 1.5 , and the 0 A setting resolution of .5 is realized.

The gain setting range is as follows: gain = C _all / C _f = Cs / Cf to (Cs + C21 + C22 + C23) / Cf = (1 / 2Cu) / Cu to (1/2 + 7) Cu / Cu = 0.5 to 7 .5.

Next, the ratio accuracy of the capacitors of the programmable capacitor array according to the present invention will be described. In general, the relationship between the capacitance value C of a capacitor and the shape dimension is given by the following equation.

C = (ε ₀ ε _s WL) / t _0x (1) where ε ₀ is the dielectric constant of vacuum, ε _s is the relative dielectric constant of the silicon oxide film, and t _0x is the thickness of the silicon oxide film. , W and L are the width and length of the upper electrode. If the fluctuations of the parameters in the above equation (1) are independent of each other, the standard deviation for the capacitance value error is as follows.

[0022]

[Equation 1]

Here, only the shape (size) of the capacitor is considered, and the terms of the relative permittivity and the oxide film thickness of the above formula (2) are ignored. Further, the capacitor has a square electrode plate.

At this time, the capacitance value of the unit capacitor is Cu
When the standard deviation sigma _{Cu / 2} with respect to the capacitance error when the standard deviation sigma _Cu, and the capacitance value of the unit capacitors was 1 / 2Cu the case of the, respectively, the following (3) formula and (4) Like

[0025]

[Equation 2]

Here, in order to realize a gain of 1.5,
Compare the standard deviations of the capacitors to be selected in the programmable capacitor array with respect to the error of the capacitance value. With a conventional programmable capacitor array, gain 1.
In order to realize 5, C1 = Cu and C2 = in FIG.
2 Cu should be selected. In this case, it is considered to be equivalent to randomly sampling a sample of size 3 from the population of the population standard deviation σ _Cu , so the standard deviation σ ₁ for the capacitance value error of the selected capacitor is σ ₁ = σ (3Cu) = 3σ _Cu (5)

Next, consider the case where the unit capacitors are set to 1/2 Cu in order to prevent an increase in the total capacitance value of the capacitors forming the circuit in FIG. Considering in the same way as σ ₁ , the standard deviation σ ₂ for the capacitance value error of the selected capacitor in this case is

[0028]

(Equation 3) Becomes

Finally, in the circuit configuration of FIG. 2 in which the present invention is used, in order to realize a gain of 1.5, C1 (= Cu) from the programmable capacitor array and 1 of the unit capacitor which is a feature of the present invention. A capacitor Cs (= 1 / 2Cu) having a capacitance value of / 2 may be selected. In this case, assuming that the standard deviations of the capacitance values of the two selected capacitors C1 and Cs are independent of each other, the standard deviation σ ₃ of the capacitance values of the selected capacitors is

[0030]

(Equation 4) Becomes

From the above equations (5), (6) and (7), it can be seen that the present invention has the smallest standard deviation with respect to the error of the capacitance value, and therefore the variation is small. Similarly, when the standard deviation is obtained for the capacitance value error of the selected capacitors of the programmable capacitor array for all the gain setting values, it becomes as shown in the graph of FIG.

FIG. 4 is a graph showing the relationship between the gain setting value and the standard deviation. The horizontal axis represents the gain setting value and the vertical axis represents the standard deviation with respect to the capacitance value error of the selected capacitor. From Fig. 4, even for all gain setting values,
It can be seen that the present invention has the smallest standard deviation. Therefore, it is clear that the present invention is the most excellent in terms of the specific accuracy of the capacitor.

Further, in FIG. 4, the standard deviations for the gain setting values of 1, 2, 3, ... Align with the standard deviation (in FIG. 8) before the addition of the capacitor Cs. this is,
If a capacitor smaller than the unit capacitor is not selected regardless of the shape of the capacitor, it means that the ratio accuracy before the addition is secured. Therefore, the present invention has a configuration in which the ratio accuracy is not deteriorated at all and the total capacitance of the capacitors forming the circuit is slightly increased by 1/2 Cu.

In the above-described embodiment, the case where the capacitor Cs is a square capacitor is described, but the capacitor Cs is not limited to this. For example, the same effect can be obtained by a method in which only one of the width and the length of the upper electrode is halved. In FIG. 5, the width W of the upper electrode
An example of the programmable capacitor array 40 in which is set to 1/2 is shown.

Also, an example has been described in which the capacitance value of the capacitor Cs is 1/2 of the unit capacitor Cu.
It suffices that the capacitance value of the capacitor Cs be smaller than that of the unit capacitor Cu, and the electrode shape thereof is not particularly limited.

[0036]

As described above, according to the present invention, the ratio accuracy of the capacitor is secured and the setting resolution is improved,
Moreover, it is possible to provide a programmer capacitor array in which the increase in the total capacitance value of the capacitors forming the circuit is minimized.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a programmable capacitor array having a 4-bit structure having a binary weighted capacitance value according to the present invention.

FIG. 2 is a diagram showing a circuit configuration example in which the programmable capacitor array 30 of FIG. 1 is applied to a gain control circuit.

FIG. 3 is a diagram showing an image of an arrangement example of capacitors in the gain control circuit of FIG.

FIG. 4 is a graph for explaining the effect of the programmable capacitor array of the present invention and showing the relationship between the gain setting value and the standard deviation.

5 is a diagram showing an image of another arrangement example of capacitors in the gain control circuit of FIG.

FIG. 6 is a diagram showing a configuration of a conventional programmable capacitor array having a 3-bit configuration having a binarized weighted capacitance value.

7A and 7B show unit capacitors, FIG. 7A is a plan view of a unit capacitor Cu, and FIG. 7B is a side view.

8 is a diagram showing a circuit configuration example in which the programmable capacitor array 10 of FIG. 6 is applied to a gain control circuit.

9 is a diagram showing an image of an arrangement example of capacitors in the circuit configuration of FIG.

FIG. 10 shows a gain setting resolution of 0.5 in FIG.
Conventional programmable capacitor array 2
It is the figure which showed the circuit structural example in which 0 was applied to the gain control circuit.

11 is a diagram showing an image of an arrangement example of capacitors in the gain control circuit of FIG.

[Explanation of symbols]

10, 20, 30, 40 ... Programmable capacitor array, 11, 12, 31, 32 ... Terminal, 13 ... Upper electrode, 14 ... Lower electrode, 15 ... Dielectric (silicon oxide film), 16 ... Input signal terminal, 17 ... Reference voltage input terminal,
18 ... Output terminal, 19 ... Operational amplifier, C1, C2, C
3, C4, C21, C22, C23, Cs ... Capacitor, Cs ... Feedback capacitor, Cu ... Unit capacitor, S
W1 to 3, SW20 to SW23 ... Switch, SW11,
SW12 ... Input signal sample switch, SW13 ... Stabilization switch.

Claims (2)

[Claims] 1. A unit capacitor is used, wherein at least two first capacitance means having binarized weighted capacitance values and at least two serially connected to each of the at least two first capacitance means. In a programmable capacitor array including a first selecting means, a second capacitance means connected in parallel with the first capacitance means and having a smaller capacitance unit than the unit capacitor, and a second capacitance means. And a second selecting means connected in series for selecting the second capacitance means. 2. The second capacitance means has a capacitance value which is half that of the unit capacitor.
A programmable capacitor array according to.