JPH09275328A - Variable capacitance circuit and analog filter circuit using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an analog filter whose cut-off frequency is less fluctuated even when the resistance of a resistive element formed on a semiconductor subscriber is largely dispersed. SOLUTION: A variable capacitance circuit 30 consisting of parallel connection of a variable capacitance circuit section making up of components 20, 3' whose gain is inversely proportioned to the resistance R of a resistive element 2 of the filter and of a fixed capacitance circuit section making up of components 21, 3" whose gain of an amplifier is fixed with respect to input signal terminals T1, VB is used for a capacitive element of the filter and its equivalent capacitance is set proportional to a multiple of the gain of the amplifier 20. Even when the resistance of the resistive element 2 formed on a semiconductor substrate is largely fluctuated, the gain of the amplifier 20 is changed inversely proportional to the resistance and the equivalent capacitance of the variable capacitance circuit cancels the fluctuation of the resistive element 2 of the CR filter circuit thereby keeping the cut-off frequency to be a desired value automatically and stably.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing circuit, an analog filter circuit, and a variable capacitance circuit suitable for use in the analog filter circuit, and particularly to an analog filter circuit suitable for forming a semiconductor integrated circuit, and an ATM-LAN. The present invention relates to a technique effectively applied to a waveform equalization circuit of an interface card.

[0002]

2. Description of the Related Art Conventionally, as an example of an analog filter circuit formed into a semiconductor integrated circuit, a capacitor and a resistor are used in FIG.
A CR filter circuit as shown in (1) is known. FIG.
In the filter circuit, the resistance element 2 having the resistance value R is connected between the analog signal input terminal 1 and the output terminal 4, and the capacitance element 3 having the capacitance value C is connected between the output terminal 4 and the fixed potential VB. It was done. This filter has a low-pass characteristic whose cutoff frequency is represented by fc = 1 / 2πCR.

However, the above-mentioned analog filter technology has the following problems. That is, since the values of the resistance element and the capacitance element formed on a normal semiconductor substrate have manufacturing variations, the cutoff frequency fc of the filter circuit largely deviates from the desired value.

[0004]

In order to solve this problem, the present inventor has examined the following techniques, and all of these techniques have an economical chip cost realized by incorporating an analog filter circuit. It has been clarified that there are still problems to be solved in terms of performance, power consumption of the analog filter circuit, versatility of application range in terms of frequency band, stability of characteristics, and the like.

As a first study technique, the resistance element of the CR filter circuit is replaced with a transconductance circuit realized by using an amplifier, that is, a voltage / current conversion circuit, and the conversion ratio is controlled to cut off the filter. OTA-C (Operatio) which suppresses the frequency variation
nal Trans-conductance Amplifier-Capacitor) circuit. In this method, for example, IEEE Journal of Solid-St
As described in ate Circuits, vol.23, No.3, June 1988, pages 750 to 758, a dedicated PLL (Phase Phase) is provided in the same semiconductor integrated circuit as the filter for controlling transconductance. -Locked Loop)
Since a separate circuit is required and the PLL circuit generally occupies a relatively large circuit scale, cost reduction and power consumption reduction are realized unless a filter with a large order or a large number of filters are integrated. Has become an obstacle factor.

The second study technique uses a variable capacitance circuit which is approximated to a gain multiple of a differential amplifier (hereinafter simply referred to as an amplifier) as a capacitance element of a CR filter circuit, and adjusts the gain to cut the filter. The off frequency is adjusted. For example, as shown in FIG. 2, the differential amplifier 2 whose non-inverting input terminal (+) is connected to the fixed potential VB
0 and a capacitive element 3 ′ connected between its output terminal and the inverting input terminal T1. Here, when the differential gain of the amplifier 20 is G, the capacitance value of the capacitive element 3 ′ is C (impedance is Z), and the voltage of the terminal T1 is V1,
The AC output voltage of the amplifier 20 becomes -GV1, and the terminal T1
Since the current i flowing from the capacitor 3'to the capacitive element 3'is obtained by dividing the voltage difference between the input and output of the amplifier 20 by the impedance Z, i = (V1 + GV1) / Z = (1 + G) V1 / Z ... (Equation 1) Represented by.

Where Z = 1 / sC (s is a complex angular frequency)
Therefore, the equivalent impedance Ze (= V1 / i) of the circuit seen from the terminal T1 obtained by modifying the above equation 1 is Ze = 1 / (1 + G) C ... (Equation 2). As a result, the equivalent capacitance value of the variable capacitance circuit of FIG. 2 becomes (1 + G) times the capacitance value C of the capacitance element 3 ′, and the input / output transfer function Vout / Vin of the filter circuit,
And the cutoff frequency fc can be expressed as follows: Vout / Vin = 1 / {1 + s (1 + G) CR} ... (Equation 3) fc = 1 / 2π (1 + G) CR ... (Equation 4)

Here, if the gain G of the amplifier 20 can be set to a value sufficiently larger than 1 as proposed in Japanese Examined Patent Publication No. 1-14726, the above (formula 4) can be expressed as fc≈1 / 2πGCR ... ( 4 ') can be approximated, and when the resistance value becomes large or small, the gain of the amplifier can be made small or large conversely to theoretically reduce the fluctuation of the cutoff frequency of the filter. However, if the gain of the amplifier is increased, the output of the amplifier is distorted or saturated, and in general, the gain band product of a single transistor with the same manufacturing technology is limited even if the operating current is changed. It becomes difficult to realize a high frequency cutoff with narrow power consumption and low power consumption. On the other hand, when the gain of the amplifier is small, the cutoff frequency of the filter circuit largely deviates from the desired value, which makes practical use difficult.

On the other hand, if the circuit configuration proposed by the present inventors in Japanese Patent Application No. 5-230093 is used prior to the application of the present invention, an equivalent capacitance of G times can be obtained for all amplifier gains. However, unfortunately, in the above proposal, since the two amplifiers are cascaded, the operation delay is relatively large, and the application in the high frequency region remains limited.

It is an object of the present invention that even if the values of the resistance elements formed on the semiconductor substrate greatly vary, the variation in cutoff frequency is small and an extra large-scale frequency control function circuit is not required. An object is to provide a low-cost analog filter circuit and a variable capacitance circuit suitable for the analog filter circuit.

Another object of the present invention is conventionally 10 MH.
To provide an analog filter circuit of low power consumption and high frequency even if the complementary MOS technology, which is disadvantageous to other semiconductor processes, is used for a field requiring a relatively high cutoff frequency of z or higher. It is in.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

[Means for Solving the Problems]

[1] First, the outline of a typical invention disclosed in the present application will be briefly described as follows. That is, as illustrated in FIG. 1, as a capacitance element of the CR filter circuit, a variable capacitance circuit having a relatively small value in which the gain of the amplifier is inversely proportional to the value (R) of the resistance element (2) of the CR filter circuit. A variable capacitance circuit (30) is used in which a section (20, 3 ′) and a fixed capacitance circuit section (21, 3 ″) in which the gain of the amplifier is fixed are connected in parallel to the input signal (T1, VB). The equivalent capacitance value of the variable capacitance circuit (30) is proportional to the gain times of the amplifier (20), where the gain of the amplifier (20) is the value of the resistance element (2) of the CR filter circuit. Inversely proportional to (R) means that the amplifier (20) is formed on the semiconductor substrate on which the resistance element (2) of the CR filter circuit is formed, and the amplifier (20) is formed.
Means an example in which it has a resistance element formed on the semiconductor substrate, and the resistance value of this resistance element is made equal to the resistance value (R) of the resistance element (2) of the filter circuit. The point is that the differential gain of the amplifier (20) forming the variable capacitance circuit section is inversely proportional to the value of the resistance element included in the amplifier (20).

The fluctuation range of the value of the resistance element formed on the semiconductor substrate is set to, for example, about ± 30%, and the fluctuation range of the value of the capacitance element is set to about ± 10%. At this time, according to the above means, even if the value of the resistance element (2) of the CR filter circuit formed on the semiconductor substrate fluctuates largely within the above-mentioned range, the variable capacitance circuit (to cancel the fluctuation. The gain of the amplifier (20) constituting the circuit 30) is inversely proportional, and the value of the equivalent capacitance of the variable capacitance circuit changes so as to cancel the variation of the resistance element (2) of the CR filter circuit. Keep the cutoff frequency automatically and stable at the desired value. In the above means, the cutoff frequency is not corrected by the variation of the value of the capacitance element itself included in each of the variable and fixed capacitance circuit parts, but as described above, the manufacturing variation width of the capacitance value is far larger than that of the resistance element. Since it is small, if it is within the allowable variation range of the cutoff frequency, a relatively large scale is added to control the cutoff frequency of the filter circuit such as the PLL required for the prior art OTA-C filter. Since it is not necessary to use such a circuit and the amplifier gain is small, it is possible to operate with a low power supply voltage, and it is possible to reduce the cost and power consumption of the realized semiconductor integrated circuit.

A CR filter circuit is taken as an example in the above description of the means, and a variable capacitance circuit included therein and other filter circuit means using the variable capacitance circuit will be individually described below.

[2] As shown in FIG. 1, the basic form of the variable capacitance circuit is such that the variable capacitance circuit section (20, 3 ′) and the fixed capacitance circuit section (21, 3 ″) are input signals (T1, VB)
Are connected in parallel to. The variable capacitance circuit unit has a first input terminal of a first polarity (for example, an inverting input terminal (-)).
And a first differential amplifier (20) having a second input terminal of a second polarity (for example, a non-inverting input terminal (+)), and an output terminal of the first differential amplifier and the first input terminal. A first capacitive element (3 ') connected between
The differential gain of the differential amplifier is configured to be inversely proportional to the value of the resistance element (for example, the resistor RC0 in FIG. 10) included in the differential amplifier. The fixed-capacitance circuit unit is the third of the first polarity
Second differential amplifier (21) having an input terminal (eg, inverting input terminal (−)) and a fourth input terminal (eg, non-inverting input terminal (+)) of the second polarity, and the second difference The second terminal connected between the output terminal and the fourth input terminal of the dynamic amplifier
And a capacitive element (3 ″) of the second differential amplifier are fixed. The first differential amplifier (2
0) and the second differential amplifier (21) have a circuit configuration in which the inverting input terminal and the non-inverting input terminal are interchanged, so that the equivalent capacitance of the first differential amplifier (20) is C (1+
G), the equivalent capacitance of the second differential amplifier (21) is C (1-
G), and considering the parallel connection, the equivalent capacitance of the variable capacitance circuit can be obtained by appropriately determining the gain and capacitance of the differential amplifier (21) that constitutes the fixed capacitance circuit unit.
Is substantially proportional to any value of the gain (G). Furthermore, since the two differential amplifiers are connected in parallel to the input signal, the operation delay is smaller than in the case where two amplifiers are connected in cascade to form a variable capacitance circuit, and application in the high frequency region is limited. It has the advantage that it is not done.

In the basic form of the variable capacitance circuit, when the capacitances of both amplifiers (20, 21) are made equal, the differential gain of the second differential amplifier (21) of the fixed capacitance circuit section is set to 2. Good. With this mode, stable circuit operation can be expected.

[3] An analog filter circuit such as a low-pass filter to which the variable capacitance circuit of the above basic form is applied has a resistance element (one end of which is connected to the signal input terminal (1) as illustrated in FIG. 2) and the variable capacitance circuit, and the first input terminal of the first differential amplifier (20) and the fourth input terminal of the second differential amplifier (21) are connected to the resistance element (2). The second input terminal of the first differential amplifier (20) and the second differential amplifier (2
The third input terminal 1) is connected to a fixed potential (VB), respectively. The operation of this filter circuit is as described above.

Further, as illustrated in FIG. 4, such filter circuits are provided in parallel, and input signals (+ Vin, -Vi) whose polarities are inverted to each analog filter circuit are provided.
It is also possible to adopt a differential form in which n) is supplied differentially. Regarding the output, the output signals (+ Vout, -Vo) whose polarities are inverted to the output of each analog filter circuit
ut) is formed, the difference between the differential output signals can be used as the filter output. If a differential input is adopted, noise that is superimposed in phase with the input analog signal or noise that is generated and superimposed from a large-scale logic circuit formed and integrated on the same semiconductor substrate becomes a problem.
These effects can be reduced.

[4] The form of the variable capacitance circuit in consideration of the differential input is not limited to the basic form described above, but a variable capacitance circuit (31) illustrated in FIG. It can also be realized by a circuit form in which the amplifier (21) of the circuit section is also used as the amplifiers (20-1, 20-2) of the two variable capacitance circuit sections. That is, the fixed capacitance circuit section according to this configuration is a fixed-gain third differential amplifier (21) having a differential input and a differential output, one input of the third differential amplifier and the same polarity as that. The third connected between the output and
Capacitive element (3 "-1) and a third differential amplifier (2
1) includes a fourth capacitive element (3 ″ -2) connected between the other input and the output of the same polarity, and one input (+) of the third differential amplifier (21) and The input (−) of the amplifier (20-1) of the one variable capacitance circuit unit is coupled to each other with opposite polarities, and the other input (−) and the other variable capacitance of the third differential amplifier (21) are connected. Circuit part amplifier (20-2)
The input (-) is coupled to each other with the same polarity. With this configuration, the circuit scale of the fixed capacitance circuit section can be reduced.

At this time, assuming that the fixed differential gain of the third differential amplifier included in the fixed capacitance circuit section is 1, the case where the gain of the amplifier (21) in the basic type variable capacitance circuit is 2 is set. The same characteristics can be obtained.

As shown in FIG. 5, an analog filter circuit such as a low-pass filter to which the variable capacitance circuit (31) is applied has a variable capacitance circuit (31) and a non-inverting input signal terminal (1- 1) connected to the first resistor element (2-1) and one end of the inverted input signal terminal (1-
2) connected to the second resistance element (2-2). The variable capacitance circuit (31) has a non-inverting input terminal (T
1-1) is connected to the other end of the first resistance element, and its inverting input terminal (T1-2) is connected to the other end of the second resistance element.

[5] The analog filter to which the variable capacitance circuit is applied may be configured as a high pass filter. That is, as illustrated in FIGS. 7 and 8, the resistance element (2-1) that receives the input signal and the variable capacitance circuit (3
The analog filter circuit can be configured to obtain a high-pass filter characteristic by subtracting the output signal of the low-pass filter including 0, 32) from the input signal via the amplifier (7-1). Since the circuit configuration in which the variable capacitance circuits are connected in a non-grounded manner is not adopted, it is possible to easily realize a high-pass fill with low power consumption and high cutoff frequency.

By providing such analog filter circuits in parallel, a high-pass filter of the differential input type can be constructed. The output at that time is the differential output,
Alternatively, the difference between the differential output signals can be output.

[6] The variable capacitance circuit (32) having a further reduced circuit scale has a differential input and a differential output, as shown in FIG. A first differential amplifier (2 that is inversely proportional to the value of the included resistance element)
0), the first capacitive element (3 ′) connected between one input terminal of the first differential amplifier and the output of the opposite polarity.
-1), and a variable capacitance circuit section including a second capacitance element (3′-2) connected between the other input terminal of the first differential amplifier and the output of the opposite polarity. A fixed gain second differential amplifier (21) having a differential input and a differential output, connected between one input terminal of the second differential amplifier and an output of the same polarity A third capacitive element (3 "-1), and a fourth capacitive element (3" -2) connected between the other input terminal of the third differential amplifier and the output of the same polarity. And a fixed capacitance circuit section including. The differential input of the first differential amplifier (20) and the differential input of the second differential amplifier (21) are connected with mutually different polarities, and one connection node is a non-inverting input terminal. , The other connection node is configured as an inverting input terminal.

In this variable capacitance circuit (32), the non-inverting input terminal of the variable capacitance circuit is connected to the first resistance element (2-
The present invention can be applied to a low-pass filter formed by connecting the inverting input terminal of the variable capacitance circuit to the other end of 1) and the other end of the second resistance element (2-2). Further, as illustrated in FIG. 7, means (7) for subtracting the differential output signal of the analog filter circuit from the corresponding differential input signal.
-1, 7-2) can be further provided to obtain a high-pass filter characteristic.

[7] The differential amplifier applied to the various variable capacitance circuits has a first input voltage (ViP) and a second input voltage (ViM) as illustrated in FIGS. Voltage / current conversion unit (50) for converting the difference between the current signals into a current signal proportional thereto, and a current / voltage conversion unit (60, for converting the current signal converted by the voltage / current conversion unit into a voltage signal proportional thereto. 61) and. The voltage / current conversion unit (50) includes first and second PMOS transistors (MT) to which the first and second input voltages are supplied to a gate electrode.
1, MT2) and the first and second constant current sources (IB) connected to the source electrodes of the first and second PMOS transistors.
1, IB2)), a first resistance element (RC0) connected between the source electrodes and formed on the semiconductor substrate, and a third resistance element connected to the drain electrodes of the first and second PMOS transistors. , 4th constant current source (IB3, IB4)
And the first and second NMOS transistors (MT3, M3) in which the drain and gate electrodes are connected to the source and drain electrodes of the first and second PMOS transistors, respectively.
T4), the first and second NMOS transistors (MT3, MT4) have a difference between the first current source current and a third current source current, the second current source current and the second current source current. Four
Of the first input voltage (ViP) and the second input voltage (ViM), the difference between the first source voltage (ViP) and the second input voltage (ViM) is set to the value of the first resistance element (RC0). The signal current (is) divided by is complementarily added. The current / voltage conversion unit (60, 61) is configured to output the first N
A configuration including NMOS transistors (MT5, MT9) connected to generate a signal current proportional to the signal current generated in the MOS transistor, and resistance elements (RC1, RC3) connected between the transistors and a fixed potential. Then, a signal voltage (VGOP) proportional to the difference between the first input voltage and the second input voltage is output.

When the output of this differential amplifier is made differential,
The current / voltage converter (60, 61) further includes the second
NM connected to generate a signal current proportional to the signal current generated in the NMOS transistor (MT4) of
OS transistors (MT6, MT10) and resistance elements (RC2, RC) connected between the transistors and a fixed potential.
4) and a signal voltage (VGO) proportional to the difference between the first input voltage (ViP) and the second input voltage (ViM).
P, VGOM)) is output differentially.

According to such an amplifier, in the NMOS transistors (MT3, MT4), mutually complementary AC signal currents proportional to the differential input voltage and inversely proportional to the value of the first resistance element (RC0). And a resistance element (RC1, RC2, RC) for converting the AC signal current into a voltage.
3, RC4) and the ratio of the first resistance element (RC0), the gain of the amplifier can be determined.

To use this amplifier as a variable gain amplifier (20, 20-1, 20-2) of the variable capacitance circuit section,
0, the first current / voltage converter (6
0) is the resistance element (RC1, RC1) included in it.
2) is a resistance element having a characteristic that the resistance value variation is smaller than that of the first resistance element (RC0), for example, an external resistance element that is not formed on the same semiconductor substrate together with the first resistance element, A signal voltage proportional to the difference between the first input voltage and the second input voltage and inversely proportional to the value of the first resistance element may be output.

In order to use the amplifier as a fixed-gain amplifier (21) of a fixed capacitance circuit section, as shown in FIG. 11, the second current / voltage conversion section (61) includes the resistor included therein. The elements (RC3, RC4) are formed on the same semiconductor substrate as the first resistance element (RC0), and
The resistance element may have substantially the same resistance value variation as that of the first resistance element, and a signal voltage having a fixed gain proportional to the difference between the first input voltage and the second input voltage may be output.

In order to further reduce the circuit scale of the amplifier as the whole variable capacitance circuit including the variable capacitance circuit portion and the fixed capacitance circuit portion, as shown in FIG. 12, together with the voltage / current conversion portion (50). , The voltage / current converter (5
0), the first and second current / voltage converters (60, 6) for converting the current signal converted into a voltage signal proportional thereto.
The amplifier (22) is configured by adopting both of 1).

[8] A variable capacitance circuit (33) using the differential amplifier (22) in which the circuit scale of the amplifiers of the variable capacitance circuit section and the fixed capacitance circuit section is reduced in this way is typical in FIG. As shown in, the differential amplifier (22),
The non-inverting output of the first current / voltage converter (60) and the second current / voltage converter (6) of the differential amplifier (22).
1) The first and second capacitive elements (3′-1, 3 ″ −) respectively connected between the inverted output and the first input voltage.
1), the inverting output of the first current / voltage converter (60) and the non-inverting output of the second current / voltage converter (61) of the differential amplifier, and the second input voltage. Third and fourth capacitive elements (3'-2, 3'-2,
3 ″ -2) and.

[0034]

[9] The variable capacitance amplifier has a differential input voltage signal (+ Vin, −Vi) as illustrated in FIG.
n) means for shifting the DC voltage and attenuating the AC amplitude (RIP1, RIP2, RIM1, RIM2), and buffer means (6-1, 6-) for outputting the differential signal obtained by this means with low impedance. 2) and a resistance element (2-1, 2-
2) and the output signal of the low-pass filter including the variable capacitance circuit (33) from the input signal to the amplifiers (7-1, 7-).
It can be applied to an analog filter circuit configured to obtain a high-pass filter characteristic by reducing it in 2). The low-pass filter has a first resistance element (2-1) whose one end is connected to the output of the buffer means which receives the non-inverted signal of the differential signal at its input, and the first resistance element and a fixed potential ( VB), and a third resistance element (5-1) whose one end is connected to the output of the buffer means which receives the inverted signal of the differential signal at its input. -2) and a fourth resistance element (5-2) connected between the third resistance element and a fixed potential (VB).
And a variable capacitance circuit (33), wherein the first input terminal (inverting input terminal (−)) of the differential amplifier included in the variable capacitance circuit (33) is the first resistor. The second input terminal (non-inverting input terminal (+)) of the differential amplifier, which is connected to the connection point of the element and the second resistance element.
Is connected to the connection point of the third resistance element and the fourth resistance element.

[10] An analog filter circuit having a high-pass filter characteristic using the variable capacitance circuit (33) can obtain a high-pass characteristic in a relatively high frequency range up to 16 MHz. This analog filter circuit includes the analog filter circuit, and the frequency characteristic of the analog filter circuit approximates the inverse characteristic of the frequency characteristic of a signal received using a metal conductor cable as a transmission line, so that the analog filter circuit has a waveform for an ATM-LAN interface. It is most suitable for the equalization filter circuit (902). Furthermore, due to the low power consumption and high cutoff frequency of the filter circuit (902), an ATM including this filter circuit (902) is provided.
-CM for semiconductor integrated circuit for physical layer for LAN
It can be realized using OS circuit technology. By mounting such a semiconductor integrated circuit, it is possible to realize an IC card having a size mountable on a personal computer or an ATM-LAN interface card formed into a circuit board.

[0036]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an example circuit of an analog low-pass filter circuit using a variable capacitance circuit according to the present invention as a capacitance element and its equivalent circuit. The variable capacitance circuit 30 shown in the figure includes an inverting input type variable capacitance circuit section including a differential amplifier (hereinafter also simply referred to as an amplifier) 20 and a capacitance element 3 ′ as a main circuit.
A non-inverting input type fixed capacitance circuit section composed of 1 and a capacitance element 3 "is used as a sub circuit and is connected in parallel to the input (T1, VB). The inverting input type variable capacitance circuit section as the main circuit. (20, 3 ') is as described based on Fig. 2. The non-inverting input type fixed capacitance circuit section (21, 3 ") as the sub-circuit is, as shown in Fig. 3, For the variable capacitance circuit (that is, inverting input type) shown in,
The non-inverting input type capacitance circuit has a configuration in which the inverting input terminal (−) and the non-inverting input terminal (+) of the amplifier are replaced with each other. That is, the inverting input terminal (-) of the amplifier 21
Is arranged at the fixed potential VB between the non-inverting input terminal (+) and the output terminal, and the capacitive element 3 ″ having the capacitance value C is arranged. The equivalent capacitance of the non-inverting input type fixed capacitance circuit section is (1- G) C
Becomes

The gain of the amplifier 20 is made variable in order to make the capacitance value of the variable capacitance circuit section variable. The gain of the amplifier 21 is set to a fixed value in order to fix the capacitance value of the fixed capacitance circuit section. here,
That the gains of the amplifiers 20 and 21 are variable and fixed means that the gains of the amplifiers 20 and 21 are variable and fixed with a certain allowable range with respect to process variations of semiconductor integrated circuits in which the amplifiers are formed and changes in ambient temperature. Means Variable and fixed terms relating to the gain of various amplifiers are used in that meaning throughout the specification. Amplifier 2
Although the specific circuit configuration of 0 and 21 will be described in detail later, for example, the gain of the amplifiers 20 and 21 is the ratio of the resistance value of the second resistance element to the resistance value of the first resistance element (second
Of the resistance element / the resistance value of the first resistance element), in the case of the amplifier 20, the second resistance element is formed on the semiconductor substrate together with other circuit elements. The first resistance element is a resistance element formed on the semiconductor substrate together with other circuit elements. In the case of the amplifier 21, both the first and second resistance elements are resistance elements formed on the semiconductor substrate together with other circuit elements.

Although not particularly limited, in FIG. 1, the gain of the amplifier 21 of the sub circuit is set to a fixed value 2. As will be easily understood by considering the parallel connection of the equivalent circuits shown in FIGS. 2 and 3, respectively, in the circuit of FIG.
The equivalent capacitance GC of the circuit seen from is exactly proportional to any value of the gain G of the differential amplifier 20. Note that this relationship is not limited to the case where the gain of the amplifier 21 is 2, and is arbitrary in relation to the capacitance value of the capacitive element 3 ″. For example, the capacitance value of the capacitive element 3 ″ is C / 2, and the amplifier 21 The same is true even if the gain G is set to 3.

Therefore, the input / output transfer function of the filter circuit and the cutoff frequency fc can be expressed as Vout / Vin = 1 / {1 + sGCR} ... (Equation 5) fc = 1 / 2πGCR ... (Equation 6) it can.

Here, the gain G of the amplifier 20 is, for example, G
= R0 / R. R0 is a preselected value of a resistance element whose value varies little, but is not particularly limited, for example, a resistance element provided outside the semiconductor substrate and having a small temperature variation coefficient. R is a value of a resistance element (a resistance element formed on a semiconductor substrate and formed in the same process as the resistance element 2) included in the amplifier 20. Here, the resistance value of such a resistance element is not particularly limited, but the same value as the resistance value R of the resistance element 2 is assumed. Gain G of this amplifier 20 (= R0 / R)
Is inversely proportional to the value R of the resistance element having the resistance value R in the amplifier 20. When the resistance value R of the resistor 2 fluctuates with respect to the design value under the influence of process variations or the like, the resistance value of the resistance element having the resistance value R in the amplifier 20 also fluctuates accordingly. The specific value of the resistance value R0 is also not particularly limited, but R0 = R is set so that the center value of the gain of the amplifier 20 is, for example, G = 1. As a result, the above (formula 6) is rewritten as fc = 1 / 2πCR0 ... (Formula 6 ′).

Therefore, even if the resistance value R of the resistance element 2 of the filter circuit largely changes, the resistance value of the resistance element having the resistance value R in the amplifier 20 also changes at the same rate, so that the variable capacitance circuit 30. Equivalent capacitance value G
C automatically changes, and the cutoff frequency fc of the analog low-pass filter circuit can be kept stable and at a desired value. That is, in (Equation 6), when R changes, G changes in inverse proportion to it, and both fluctuations cancel each other out.

FIG. 4 shows the variable capacitance circuit 3 shown in FIG.
An example of a variable capacitance circuit 31 in the case where 0 has a differential configuration and an analog filter circuit to which the variable capacitance circuit 31 is applied is shown. Generally, the number of elements is approximately doubled in the differential configuration, but noise superimposed in phase with the input analog signal and generated by a large-scale logic circuit formed and integrated on the same semiconductor substrate are superimposed. When the generated noise becomes a problem, it is extremely effective as a means for reducing these effects. The differential configuration of FIG. 4 is realized by simply making the configuration of FIG. 1 parallel in two lines and supplying signals + Vin and −Vin, which are mutually inverted, to the respective input terminals. The differential output of the filter circuit is shown as + Vout, -Vout.

FIG. 5 shows the variable capacitance circuit 30 shown in FIG.
6 shows another example of the variable capacitance circuit 31 having a differential configuration and a differential analog filter circuit to which the variable capacitance circuit 31 is applied.
Shows an equivalent circuit of the filter circuit of FIG. In the case of FIG. 5, the fixed gain amplifier 21 forming the variable capacitance circuit 31 is used as a differential input of inverted and non-inverted signals, and the differential gain thereof is set to a fixed value 1. This can reduce the number of fixed gain amplifiers by one. The input / output transfer function and the cut-off frequency fc of this differential low-pass filter circuit are the above-mentioned (Equation 5), (Equation 6) or (Equation 6 ').
Is the same as In addition, the capacitive element 3'-1,
3'-2 corresponds to the capacitive element 3'of FIG.
-1, 20-2 correspond to the amplifier 20, respectively,
Capacitance elements 3 "-1, 3" -2 correspond to the capacitance element 3 ", and resistance elements 2-1 and 2-2 correspond to the resistance element 2. Also, in FIG. The side 31-1 and the inverting input side 31-2 refer to the variable capacitance circuit 31.

FIG. 7 shows a variable capacitance circuit 3 according to the third example.
2 and a high-pass filter circuit having a constant low frequency gain is shown as an example in which it is applied to a differential analog filter circuit. Generally, a non-grounded type capacitance element is used in a high pass filter circuit. To use the variable capacitance circuit as described in FIG. 1 as a high pass filter as the capacitance element, the amplifier of the variable capacitance circuit is used. Since a certain gain or more is required over a high frequency range, it is difficult to realize a high-pass filter with low power consumption and a high cutoff frequency. Therefore, in FIG. 7, the non-inverting and inverting output signals of the buffer amplifier 6 are subtracted from the non-inverting and inverting output signals of the differential low-pass filter by using the amplifiers 7-1 and 7-2, respectively,
A grounded variable capacitance circuit is used as the capacitance element of the low-pass filter. In this case, the resistance elements 2-1 and 5-
The variable capacitance circuit 30 of FIG. 1 or the variable capacitance circuit 31 of FIG. 5 may be connected to the connection point of No. 1 and the connection points of the resistance elements 2-2 and 5-2, but in FIG. The circuit 32 is used. In the variable capacitance circuit 32, the amplifier 20 of the main circuit and the amplifier 21 of the sub circuit are both configured as an amplifier 20 having an inverted and non-inverted differential input and differential output format.
The differential gain is set to half (G / 2) of that in the case of FIG. 5, and the sub-amplifier 21 is configured in the same manner as in the case of FIG. Therefore, the number of amplifiers required for the differential variable capacitance circuit is shown in FIG.
The number of amplifiers 20 is further reduced by one as compared with.

Since this high-pass filter has a constant gain even in the low frequency region, there are two cutoff frequencies. The input / output transfer function and the first cutoff frequency f
The first and second cutoff frequencies f2 are equal to the amplifiers 6 and 7-1.
When the gains of 7 and 7-2 are both set to 1, Vout / Vin = R2 (1 + sGCR1) / (R1 + R2 + sGCR1R2) (Equation 9) f1 = 1 / 2πGCR1 ... (Equation 10) f2 = (R1 + R2) / 2πGCR1R2 ... (Equation 10) It can be expressed as in Equation 11).

Here, the gain G of the differential amplifier 20 is, for example, G
= R0 / R1. R1 is the resistance value of the resistance element included in the amplifier 20, and is not particularly limited, but is equal to the resistance value R1 of the resistance elements 5-1 and 5-2 formed on the same semiconductor substrate together with this resistance. Has been done. R0
Is a resistance element whose value varies little, but is not particularly limited,
For example, a resistance element provided outside the semiconductor substrate and having a small temperature variation coefficient is a preselected value, and its specific value is not particularly limited, but the central value of the gain is, for example, G = 1. By setting R0 = R1 so that, the above equations (10) and (11) are respectively f1 = 1 / 2πCR0 ... (Equation 10 ′) f2 = {(R1 + R2) / R2} / 2πCR0. 11 ').

Therefore, even if the values R1 and R2 of the resistance elements 2 and 5 formed on the semiconductor substrate fluctuate, the first cutoff frequency f1 is stable as described above, and the resistance ratio (R1 + R2). Since / R2 is basically constant, the second cutoff frequency f2 is also stabilized. Further, the input / output gain of (Equation 9) is also expressed as R1 / (R1 + R2) for frequencies sufficiently lower than f1, and is stable for frequencies sufficiently higher than f2, so both are stable. You can In FIG. 7, the fixed potential VB is an analog ground. This fixed potential V
B can be a reference potential generated by a reference voltage generation circuit (not shown) that forms a stable voltage by using, for example, a band gap of silicon.

In FIG. 7, the inverting and non-inverting input terminals of the differential amplifier 6 are supplied with signals + Vin and -Vin whose phases are mutually inverted, but depending on the case, one of the input signals may be omitted. It is also possible to use it. The configuration of the high-pass filter circuit represented by FIG. 7 is not limited to the one having the differential inputs + Vin, −Vin and the differential outputs + Vout, −Vout,
For example, it is possible to configure as shown in FIG. In FIG. 8, the input signal Vin is received by a buffer amplifier 6 such as a source follower circuit, and the variable capacitance circuit 30 of FIG. 1 is connected to a fixed potential (VB) on the output side of the buffer amplifier 6 via a resistance element R2. It is arranged.

FIG. 9 shows a bias current circuit of the various amplifiers suitable for use in the variable capacitance circuit and the analog filter circuit according to the present invention. In FIG.
The transistors MP1 and MP2 and the resistance element Ri1 are
The external resistance element Rref constitutes an input protection circuit of the semiconductor integrated circuit for the external terminal TR0 connected between the external resistance element Rref and the ground potential terminal GND. In the amplifier OP1, the power-down control signal PD is low potential here and the transistor MA1
And MA2 are turned on, and transistors MA7 and MA
When the transistor 8 is turned off, a current having a value obtained by dividing the fixed potential VB supplied to the non-inverting input terminal (+) by the resistance value of the external resistance element Rref is used as the transistors MA5 and M5.
It operates to cause A3. This transistor M
The current flowing through A3 is generated by the transistors MA4, MA6, M
A9 sequentially generates a mirror current that is proportional to the dimension ratio of the transistors MA6 and MA10, drain voltages A3 and A4 of the transistors MA6 and MA10, a drain node A5 of the transistor MA12, and a drain node A6 of the transistor MA13. To form. As a result, the bias current of the differential amplifiers of FIGS. 10, 11 and 12 described later can be set to a desired value. At this time, the fixed potential VB can be a stable voltage generated by a reference voltage generating circuit (not shown), and an element having a relatively low price and a small temperature variation coefficient can be selected as the external resistance element Rref. Therefore, it is easy to set and hold the bias current of the amplifier shown in FIG. 9 and described later with relatively high precision and stability.

FIG. 10 shows a detailed example of the differential amplifiers 20, 20-1 and 20-2 having a variable gain suitable for use in the variable capacitance circuit and the analog filter circuit according to the present invention. . The amplifier shown in the figure includes a voltage / current conversion unit 50 that converts a differential component of the non-inverted voltage input signal ViP and the inverted voltage input signal ViM into a current signal is that is inversely proportional to the value of the resistance element RC0. A current / voltage conversion unit 60 for converting the current signal is into a voltage signal proportional thereto
It is composed of

In the voltage / current converter 50, the PMOS transistor MT1 whose gate is supplied with the non-inverted voltage input signal ViP, the constant current sources IB1 and IB3 connected to its source and drain, and the inverted voltage input signal to its gate. The PMOS transistor MT2 supplied with ViM, the constant current sources IB2 and IB4 connected to the sources and drains thereof, the drain and gate of the sources and drains of the transistors MT1 and MT2, respectively, and the source thereof to the ground potential GND. And the NMOS transistors MT3 and MT4 connected to each other, and the resistance element RC0 formed on the semiconductor substrate and connected between the sources of the transistors MT1 and MT2.

Here, the gates of the current source MOS transistors connected in series which form the constant current sources IB1 and IB2 are connected to the node A formed by the bias circuit of FIG.
4, the potential of the node A5 or A6 is supplied. The gate of the current source MOS transistor forming the constant current sources IB3 and IB4 is supplied with the potential of the node A3 formed by the bias circuit of FIG. As a result, the constant current sources IB1, IB2, IB3, IB4 are set so as to flow a mirror-multiplied current of the corresponding node A3, A4, A5 or A6. Constant current sources IB1 and IB3, IB
2 and IB4, IB1 = IB2, IB
3 = IB4 and IB1> IB3, and P
A constant current source I is always applied to the MOS transistors MT1 and MT2.
The constant currents of B3 and IB4 are flowing.

When the input voltage is ViP = ViM, the potentials of the nodes v1 and v2 are equal, so that the resistance element RC is used.
No current flows in 0, and IB1 to IB3 having the same difference current flows in the transistors MT3 and MT4. On the other hand, when the input voltages ViP and ViM change, for example, in the directions shown by the arrows in the figure, that is, when ViP> ViM, a potential difference equal to the difference voltage Δ = Vip−ViM also occurs between v1 and v2. A current of is = Δ / RC0 flows through RC0. As a result, the current of the transistor MT3 becomes i3 = IB1-IB3-is, and the current of the other transistor MT4 becomes i4 = IB1-IB3 + is.
Therefore, as is clear from the above, the transistor M
T3 and MT4 have a resistance element R proportional to the differential input voltage Δ.
AC signal currents ± is complementary to each other and inversely proportional (inversely proportional) to the value of C0 flow.

The current / voltage conversion unit 60 has the NMO
The NMOS transistors MT5 and MT6, which are set so as to pass the currents having the respective mirror ratio times the currents of the S transistors MT3 and MT4, and their drain nodes v
Constant current sources IB5 and IB6 connected to V5 and v6, for example, but not limited to, for example, external connection terminals TR1 and TR
2 and the fixed potential supply terminal TRAG, and provided outside the semiconductor substrate are resistance elements RC1 and RC2 having a small temperature variation coefficient and a resistance value preselected. Then, a source follower circuit composed of a PMOS transistor MT7 and a constant current source IB7 for outputting the respective voltages of the nodes v5 and v6 with low impedance, and P
A source follower circuit including a MOS transistor MT8 and a constant current source IB8 is provided. Where constant current source I
B5, IB6, IB7 and IB8 are the constant current sources IB
Like IB1 and IB2, the voltage of the node A4, A5 or A6 supplied from the bias circuit of FIG.

Specific values of the resistance elements RC1 and RC2 are as follows: the mirror ratio between the NMOS transistors MT3 and MT5, the mirror ratio between the NMOS transistors MT4 and MT6, the desired differential amplification gain G, and the resistance. Element R
Depending on the value of C0, various combinations are possible. For example, when the mirror ratio between the transistors MT3 and MT5 and the mirror ratio between the transistors MT4 and MT6 are 1, respectively, RC1 (= RC2) / RC0 is selected to be equal to the center value of the desired amplifier differential gain G. be able to. The central value of the gain of the amplifier shown in FIG.
To select = 1, RC1 = RC2 = RC0 may be set.
In this case, the transistors MT3, MT5 and MT
When the mirror ratio between 4 and MT6 is generally n, RC
It may be 1 = RC2 = RC0 / n. In these cases,
Since the absolute value of each resistance element is not directly related to the gain G, the value of each resistance element RC1, RC2, RC0 is
It may be determined so that the linear operation of each part of the circuit is possible and the power consumption is appropriate.

When the resistance value is set as described above and the resistance value of the resistance element RC0 changes 0.7 times or 1.3 times, the differential gain of the amplifier is G≈1.43, respectively.
It is set to 0.77. Further, in addition, when the resistance value of the resistance element RC0 changes 0.7 times or 1.3 times, the resistance of the resistance element formed on the same semiconductor substrate as the resistance element RC0, for example, forming an analog filter. The value is 0.
It fluctuates 7 times or 1.3 times.

FIG. 11 shows an embodiment of a differential amplifier 21 having a fixed gain suitable for use in the variable capacitance circuit and the analog filter circuit according to the present invention. The amplifier 21 is composed of a voltage / current conversion unit 50 and a current / voltage conversion unit 61 which have the same configuration as in FIG. However, resistance elements RC3 and RC4 formed on the same semiconductor substrate as the resistance element RC0 are connected to the current / voltage converter 61. The value of each resistance element in this case can be determined in exactly the same manner as in the case of FIG. 10 described above.
Mirror ratio of S-transistors MT3 and MT9, and NMO
When the mirror ratios of the S transistors MT4 and MT10 are each 1 and the differential gain of the amplifier 21 is G = 2, RC1 (= RC2) / RC0 = 2 may be set. In this case, the resistance elements RC3 and RC4 are the resistance elements RC0.
Therefore, even if the resistance element RC0 changes 0.7 times or 1.3 times, the differential gain remains constant at 2.

FIG. 12 shows an example of an amplifier 22 having differential outputs of variable gain and fixed gain which are suitable for use in the variable capacitance circuit and the analog filter circuit according to the present invention. This amplifier is realized by combining the circuits of FIG. 10 and FIG. 11, and the common voltage / current conversion unit 50 has a differential voltage V2OP having a fixed gain with respect to a change in the value of the resistance element RC0. , V2OM for outputting the current / voltage converting section 60 and a current / voltage converting section 61 for outputting the differential voltages VGOP and VGOM having the inverse proportional gain G with respect to the variation of the value of the resistance element RC0 are connected in parallel. Have. The operation of FIG. 12 and the value of each resistance element are the same as those described with reference to FIGS. 10 and 11, and the detailed description thereof will be omitted.

FIG. 13 shows the amplifier 22 shown in FIG.
As an application example of, a high-pass filter circuit having a constant gain in the low frequency region is shown. This filter circuit is suitable, for example, as a waveform equalization filter circuit that is indispensable for waveform reproduction of a transmission system using a metal conductor cable. Generally, in digital pulse signal transmission using a metal conductor cable as a transmission line, the higher the frequency and the longer the cable length, the greater the attenuation that is proportional to the square root of the frequency. Therefore, the signal pulse waveform decreases and distorts. It becomes difficult to receive data without error. Therefore, in order to receive the original signal with the minimum error rate, it is necessary to provide a waveform equalization filter having an inverse frequency characteristic of the transmission line on the reception side and correct the distortion of the transmission pulse waveform. Become.

In FIG. 13, RT1 is an external resistance element for matching termination of the impedance of the transmission line.
The differential signals received as + Vin and −Vin are supplied to the input terminals RXA and RXB, and the internal resistors RIP1, RIP2, RIM1 and RIM2 formed on the semiconductor integrated substrate cause the amplitude RIP2 around the fixed potential VB. Converted to an internal differential signal of Vin / (RIP1 + RIP2). In this way, the amplitude of the internal differential signal is
The reason why the amplitude of the input differential signal + Vin, −Vin is made smaller by the resistance voltage division is that the input differential signal + Vin,
Even when the amplitude of −Vin is large (when the length of the transmission line from the transmitting end is short), the input of the amplifier 22 arranged in the subsequent stage is prevented from being closer to the operating power supply voltage. is there. Also in this respect, it is considered that the amplifier 22 operates stably over a wide range of frequencies. Here, RIP1 = RIM1 and PIP2 = RIM
The fixed potential VB is 2, but is not particularly limited. For example, the power supply voltage VDD supplied to the semiconductor integrated circuit.
And a value approximately intermediate between the ground potential GND and the ground potential GND are supplied. The fixed potential VB can be formed by using a reference voltage generating circuit, although not particularly limited.

The above-mentioned internal differential input signal is supplied to the waveform equalizing filter 40 via amplifiers (for example, source follower circuits) 6-1 and 6-2 whose main purpose is impedance conversion. The waveform equalization filter 40 includes a variable capacitance circuit 33 using a differential amplifier 22 in which the circuit scale of the amplifiers of the variable capacitance circuit unit and the fixed capacitance circuit unit is reduced. The variable capacitance circuit 33 includes the differential amplifier 22, a non-inverted output VGOP of the first current / voltage converter 60 and an inverted output V2OM of the second current / voltage converter 61 of the differential amplifier 22. Capacitance elements 3'-1, 3 "-1 respectively connected between the inverting input terminal (-) of the amplifier 22 and the inverting output of the first current / voltage conversion unit 60 of the differential amplifier 22. VGOM and second current / voltage converter 6
1 non-inverting output V2OP and the non-inverting input terminal (+) of the amplifier 22 respectively connected to the capacitive element 3'-
2, 3 ″ -2. The waveform equalization filter circuit 40 is basically the same as the configuration of FIG.
Therefore, the input / output transfer function and the first cutoff frequency f1 and the second cutoff frequency f2 are
The gain up to (6-1, 6-2) and the amplifier 7 (7-1,
If the effect of the gain of 7-2) is omitted, the above (Equation 9),
They are the same as (Equation 10) and (Equation 11), respectively. However, in reality, the amplifiers 6-1, 6-2 and 7-1, 7-2
Attenuation of the gain in the high frequency region of the device itself causes a bandpass characteristic.

In FIG. 13, the amplifier 6-3 is added in order to avoid the influence of the DC offset voltage that is unavoidably generated in the amplifiers 6-1 and 6-2. The output is given to the connection point of the resistance elements 5-1 and 5-2, so that the influence of the offset voltage can be canceled at the time of subtraction by the amplifiers 7-1 and 7-2. Incidentally, such a configuration can be omitted depending on the characteristic specifications of the product. As the amplifiers 6-1 to 6-3 and 7-1 and 7-2, those realized by a conventionally known circuit format can be used.
Further, the amplifier 8 is the differential output of the waveform equalization filter 40+
Although it is added to convert Vout and -Vout into a single output, it may be a non-linear amplifier whose output 9 waveform is converted into a pulse, for example, a voltage comparator. Further, as a matter of course, the waveform equalization filter 40 can be realized also by using the variable capacitance circuit shown in FIG. 1, FIG. 5 or FIG. 7 as the variable capacitance circuit.

FIG. 14 shows an example of application of the waveform equalization filter circuit shown in FIG.
ATM-LAN (Asynchrono 6Mbit / s)
us Transfer Mode-Local Area Network) Physical layer line terminator (PMD = Physical)
The configurations of the Media Dependent) 90 and the transformer module 91 are shown. The line terminating device 90 is not particularly limited, but may be formed by a MOS semiconductor integrated circuit manufacturing technique.
It is formed on each semiconductor substrate, and is simply referred to as PMD-L below.
Also referred to as SI (Large Scale Integration) 90. The transformer module 91 is configured as a hybrid module or a hybrid integrated circuit.

In FIG. 14, TX-Data is a data signal of characters, images, etc. handled in, for example, a personal computer, and a latch circuit (Data Latch) 900 of the PMD-LSI 90 at the transmission clock TX-CLK.
Are output from the transmission driver circuit 901, and are output via a transmission waveform template filter (transmission filter) 910 that limits the output pulse waveform within a specified value, and a transmission transformer 911. This transmission output signal is a UT with a maximum length of 100 m and a characteristic impedance of 100Ω.
It is transmitted via a transmission line 92 such as P (unshielded twisted pair wire) or STP (shielded twisted pair wire) of 120Ω or 150Ω. On the other hand, from the transmission line 92 through the receiving transformer 912 to the PMD-LSI.
The received signal input to 90 is reproduced into a pulse waveform by the waveform equalization filter circuit 902 having the circuit configuration of FIG. 13, for example. ATM-L with a transmission rate of 25.6 Mbit / s
In the AN system, 4B / 5B converted NRZI (No
Since the n-Return to Zero Inverse) code is used, the maximum signal actually transmitted is 32 Mbit / sec.
Frequency components up to 6 MHz are included. Therefore, the waveform equalization filter circuit 902 described above requires high-pass characteristics in the frequency range up to 16 MHz.

Clock extraction PLL (Phase-Locked Loo)
p) 903 is for synchronously extracting a stable clock of 32 MHz as RX-CLK from the output signal of the waveform equalization filter circuit 902. This clock RX-C
LK outputs the output of the waveform equalization filter circuit 902 to a data Rx-D via a latch circuit (Data Latch) 904.
The data is output from the PMD-LSI 90. A loopback 905 in the figure substitutes the transmission signal when the reception signal detecting means (not shown) detects disconnection of the reception signal during communication, and substitutes the transmission signal for a certain time. At the same time, it is used as a function to prevent unnecessary signals from being sent out during non-transmission immediately after the PMD-LSI 90 is powered on. A reference voltage generation circuit 906 is a circuit that generates a reference potential (a substantially constant stable voltage that does not depend on a temperature change or the like) such as a fixed potential VB used in the waveform equalization filter circuit.

FIG. 15 shows an example of an ATM-LAN interface card to which the PMD-LSI 90 and the transformer module 91 are applied. This ATM-LA
In the N interface card, a PMD-LSI 90 as an application example of the waveform equalization circuit shown in FIG. 14 is arranged side by side with a transformer module 91 and other integrated circuits.
For example, an ATM having a transmission speed of 25.6 Mbit / sec, which is realized by being mounted on a so-called type 2 standard card 100 of 5.6 mm, length 54.0 mm, and thickness 5.0 mm.
An interface card which is an IC card for LAN. A transmission / reception signal of the transformer module 91 is connected to a first terminal group (not shown) provided on the card body 100 and a connector 1 detachably connected to the first terminal group.
It is connected to a twisted pair wire 92 having a maximum length of 5 m via 01, and the twisted pair wire 92 is provided with a specified jack / socket 102 and has a maximum length of 90 m of the UTP or STP.
Connected to 103. On the other hand, the card body 100 is inserted into, for example, a notebook type personal computer body, and the second terminal group 10 provided in the card body 100.
4 to PCMCIA (Personal Computer Memory Card)
It is directly or indirectly connected to a microprocessor mounted in a main body of a personal computer (not shown) through a bus interface or the like, and enables transmission / reception, display, and processing of various data using this LAN card.

TC (Transmission Convergence) in the figure
The unit 93 constitutes the physical layer of the ATM-LAN together with the PMD-LSI 90, and scrambles / transmits data cells.
Descramble, 4-bit / 5-bit conversion, NRZ / N
It realizes functions such as RZI code conversion. The ATM controller unit (ATM-LSI) 94 includes a microprocessor (MCU) 95, a ROM 96 holding an operation program of the microprocessor 95 and constant data or a constant table, and a temporary storage area in the work area or data of the microprocessor 95. RAM97,
And a buffer memory 98 including a DRAM and the like
At the same time, functions such as conversion of various data of variable-length packets and fixed-length ATM cells, interface conversion of various bus formats, and the like are realized.

Regarding the functional specifications of PMD, TC, etc., from 1994 to 1995, ATM Fo
Physical Inte issued by rum Technical Committee
rface Specification for 25.6Mb / s over Twisted Pair
More on Cable.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto and needless to say, various modifications can be made without departing from the scope of the invention. Yes.

For example, the differential amplifier shown in FIGS. 10, 11 and 12 has PMOS transistor inputs and differential outputs, but it may have NMOS transistor inputs and may have a single output according to the filter configuration. Good.
A person skilled in the art can easily change the circuit configuration for that purpose. Further, the resistance elements provided outside the semiconductor substrate connected to the current / voltage conversion circuits of those amplifiers and having a small temperature variation coefficient are the external connection terminals TR1 and TR2.
The resistance element connected between the fixed potential supply terminal TRAG and the fixed potential supply terminal TRAG has been described. However, the resistance element is not limited to the resistance element. The value may be finely adjusted by trimming) or the like, and in that case, an external connection terminal is not necessary and connection is possible within a package that seals the integrated circuit.

The present invention also relates to FIG. 1, FIG. 4, FIG. 5, FIG.
Although the first-order filter is described in FIGS. 8 and 13,
It goes without saying that it is also applicable to the filters of the following or higher. In addition, PM in the application example of FIG. 14 and FIG.
It is easy to form the D-LSI 90 and the TC 93 on one semiconductor chip, and further form the other peripheral functions 94 to 97 on one semiconductor chip 99 as shown in FIG. Is also possible.

Furthermore, the present invention has been described with the variable gain G in the variable capacitance circuit shown in FIGS. 10 to 12 as the center value of 1 and the fixed gain amplifier as 2 or 1. The gain of each amplifier may be set to 3, and the value of the capacitive element connected to its output may be halved.

Furthermore, according to the present invention, the value of the capacitance element by the variable capacitance circuit is automatically changed with respect to the variation of the value of the resistance element of the analog filter circuit to keep the cutoff frequency at the desired value. Although it has been described that the cutoff frequency cannot be corrected by the fluctuation of the capacitance element itself, a plurality of variable capacitance circuits of the present invention are connected in parallel and a means for externally adjusting the gain of at least one variable capacitance circuit is added. By doing so, it is possible to correct the cutoff frequency due to the initial fluctuation of the capacitive element itself.

In the above description, the case where the invention made by the present inventor is mainly applied to a filter circuit which is a field of application which is the background of the invention has been described. However, the present invention is generally applied to analog integrated circuits having a capacitive element. You can

[0075]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, in the case of a semiconductor integrated circuit, it is possible to easily and economically realize an analog filter in which the variation in the cutoff frequency is small even if the values of capacitance and resistance vary.

A low-cost analog filter circuit in which even if the values of the resistance elements formed on the semiconductor substrate greatly vary, the variation in cutoff frequency is small and an extra large-scale frequency control function circuit is not required to be added. , And a variable capacitance circuit suitable therefor can be realized.

Conventionally, in the field where a relatively high cut-off frequency of 10 MHz or more is required, even if the complementary MOS technology, which is disadvantageous to other semiconductor processes, is used, low power consumption and high frequency signals are obtained. An applicable analog filter circuit can be realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first circuit example of a variable capacitance circuit according to the present invention and an analog filter circuit using the variable capacitance circuit and its equivalent circuit.

FIG. 2 is an explanatory diagram of a variable capacitance circuit section as a main circuit portion included in the variable capacitance circuit of FIG.

3 is an explanatory diagram of a fixed capacitance circuit section as a sub circuit portion included in the variable capacitance circuit of FIG.

FIG. 4 is a circuit diagram showing a second circuit example of a variable capacitance circuit and an analog filter circuit using the variable capacitance circuit.

FIG. 5 is a circuit diagram showing a circuit example in which the circuit scale is reduced with respect to the second circuit example of the variable capacitance circuit and the analog filter circuit using the variable capacitance circuit.

6 is an equivalent circuit diagram of FIG.

FIG. 7 is a circuit diagram showing a differential input / output type high-pass filter circuit as a third circuit example of a variable capacitance circuit and an analog filter circuit using the variable capacitance circuit.

FIG. 8 is a circuit diagram showing a high-pass filter circuit of another circuit type as a third circuit example of a variable capacitance circuit and an analog filter circuit using the variable capacitance circuit.

9 is a circuit diagram of an example of a bias circuit that supplies a bias voltage to a constant current source of the differential amplifier of FIGS. 10, 11 and 12. FIG.

FIG. 10 is a circuit diagram of an example of a differential amplifier having a variable gain.

FIG. 11 is a circuit diagram of an example of a differential amplifier having a fixed gain.

FIG. 12 is a circuit diagram of an example of a differential amplifier having both variable gain and fixed gain.

13 is a circuit diagram showing a variable capacitance circuit using the differential amplifier shown in FIG. 12 and an analog filter circuit using the variable capacitance circuit as a capacitance element.

14 is a PMD-LS for ATM-LAN using the analog filter circuit shown in FIG. 13 as a waveform equalizing circuit.
It is a functional block block diagram of I and a transformer module.

15 is a PM for ATM-LAN shown in FIG.
ATM-L equipped with D-LSI and transformer module
It is a block diagram of an AN card.

FIG. 16 is a circuit diagram showing an example of a CR analog filter circuit.

[Explanation of symbols]

1 (1-1, 1-2) Filter input 2 (2-1, 2-2), 5 (5-1, 5-2) Resistance element 3 '(3'-1, 3'-2), 3 "(3" -1, 3 "-
2) Capacitance element 4 (4-1, 4-2) filter output 6, 7, 8, 20 (20-1, 20-2), 21, 22
Differential amplifier 30, 31, 32, 33 Variable capacitance circuit 40 Waveform equalization filter 50 Voltage / current conversion circuit 60, 61 Current / voltage conversion circuit MT1, MT2 PMOS transistors MT3, MT4 NMOS transistors MT5 to MT12 NMOS transistors IB1 to IB12 Constant current source RC0 to RC4 Resistance element is Current signal ViP, ViM Differential input voltage signal VGOP, VGOM Differential output voltage V2OP, V2OM Differential output voltage 90 PMD-LSI 91 Transformer module 100 Standard card

Front page continued (72) Inventor Sadahiro Mioda 1 Horiyamashita, Hadano City, Kanagawa Prefecture Hitachi Computer Engineering Co., Ltd. (72) Inventor Yoshiharu Nagayama 2326 Imai, Ome City, Tokyo Hitachi Device Development Co., Ltd. In the center

Claims (24)

[Claims] 1. A first differential amplifier having a first input terminal of a first polarity and a second input terminal of a second polarity, and an output terminal of the first differential amplifier and the first input. A variable capacitance circuit section including a first capacitive element connected between the terminal and a terminal, wherein a differential gain of the first differential amplifier is inversely proportional to a value of a resistive element included in the differential amplifier; A second differential amplifier having a third input terminal of one polarity and a fourth input terminal of second polarity; and a second differential amplifier connected between the output terminal and the fourth input terminal of the second differential amplifier. And a fixed capacitance circuit unit having a fixed differential gain of the second differential amplifier, the variable capacitance circuit unit and the fixed capacitance circuit unit having a fixed capacitance circuit unit with respect to an input signal. A variable capacitance circuit characterized by being connected in parallel with each other. 2. The variable capacitance circuit according to claim 1, wherein the differential gain of the second differential amplifier of the fixed capacitance circuit section is set to 2. 3. The variable filter according to claim 1, wherein the capacitance element is an analog filter circuit including a resistance element having one end connected to a signal input terminal and a capacitance element having one end connected to a fixed potential. Using a capacitance circuit, the first
The first input terminal of the differential amplifier and the fourth input terminal of the second differential amplifier to the other terminal of the resistive element, and the second input terminal of the first differential amplifier to the second input terminal of the second differential amplifier. An analog filter circuit, wherein the third input terminal of the differential amplifier is connected to a fixed potential, respectively. 4. The analog filter circuits according to claim 3 are provided in parallel, input signals whose polarities are inverted to each other are differentially supplied to the respective analog filter circuits, and polarities are inverted to the output of each analog filter circuit. An analog filter circuit, which forms an output signal. 5. A first differential amplifier having a first input terminal having a first polarity and a second input terminal having a second polarity, and an output terminal of the first differential amplifier and the first input. A first variable capacitance circuit unit including a first capacitance element connected between the terminal and a terminal, and a differential gain of the first differential amplifier is inversely proportional to a value of a resistance element included in the differential amplifier. And a second differential amplifier having a first input terminal of the first polarity and a second input terminal of the second polarity, and between the output terminal and the first input terminal of the second differential amplifier A second capacitive element connected to the second differential amplifier, wherein the differential gain of the second differential amplifier is inversely proportional to the value of the resistive element included in the differential amplifier.
A variable-capacitance circuit section, a third differential amplifier having a fixed gain having a differential input and a differential output, and is connected between one input of the third differential amplifier and an output having the same polarity as that of the third differential amplifier. A fixed capacitance circuit section including a third capacitance element and a fourth capacitance element connected between the other input of the third differential amplifier and the output having the same polarity as the third input; The one input terminal of the differential amplifier 3 is the first
The variable capacitance circuit section is connected to the first input terminal so as to have different polarities, and the other input terminal of the third differential amplifier is connected to the differential amplifier input terminal of the second variable capacitance circuit section. Are connected so that they have the same polarity, and one of the first input terminal of the first variable capacitance circuit section and the first input terminal of the second variable capacitance circuit section is a non-inverting input terminal,
A differential signal input type variable capacitance circuit characterized in that the other is formed as an inverting input terminal. 6. The variable capacitance circuit according to claim 5, wherein the fixed differential gain of the third differential amplifier included in the fixed capacitance circuit section is set to 1. 7. A first resistance element having one end connected to the non-inverting input signal terminal, a second resistance element having one end connected to the inverting input signal terminal, and a capacitance element having one end connected to a fixed potential. In an analog filter circuit including, the variable capacitance circuit according to claim 5 or 6 is used as the capacitance element, and the non-inverting input terminal of the variable capacitance circuit is at the other end of the first resistance element, The inverting input terminal of the variable capacitance circuit is connected to the other end of the second resistance element, and the second input terminals of the first and second differential amplifiers are connected to a fixed potential, respectively. An analog filter circuit characterized by the above. 8. An analog filter circuit configured to obtain a high-pass filter characteristic by subtracting an output signal of a low-pass filter including a resistance element and a capacitance element receiving an input signal from the input signal, wherein the capacitance element is an analog filter circuit. An analog filter circuit using the variable capacitance circuit according to item 1 or 2. 9. The analog filter circuits according to claim 8 are provided in parallel, input signals whose polarities are inverted to each other are differentially supplied to each analog filter circuit, and polarities are inverted to the output of each analog filter circuit. An analog filter circuit characterized in that an output signal is formed differentially. 10. A first differential amplifier having a differential input and a differential output, the differential gain of which is inversely proportional to the value of a resistance element included in the differential amplifier, and the first differential amplifier of the first differential amplifier. A first capacitive element connected between one input terminal and an output of opposite polarity, and a second capacitive element connected between the other input terminal of the first differential amplifier and an output of opposite polarity. A variable-capacitance circuit section including a capacitive element, a fixed-gain second differential amplifier having a differential input and a differential output, one input terminal of the second differential amplifier, and the same polarity as the input terminal. Fixed comprising a third capacitance element connected between the output and a third capacitance element, and a fourth capacitance element connected between the other input terminal of the third differential amplifier and the output of the same polarity. A capacitive circuit section, and the differential input of the first differential amplifier and the differential input of the second differential amplifier are mutually connected. Connect with each other sexually different things, one of the non-inverting input terminal connected node, the differential signal input type variable capacitance circuit, characterized in that those comprising the other connection node as an inverting input terminal. 11. A variable resistance circuit according to claim 10, wherein a first resistance element having one end connected to the non-inverting input signal terminal, a second resistance element having one end connected to the inverting input signal terminal, and the variable capacitance circuit according to claim 10. An analog filter circuit including the variable capacitance circuit, wherein the non-inverting input terminal is at the other end of the first resistance element, and the inverting input terminal of the variable capacitance circuit is at the other end of the second resistance element. , An analog filter circuit characterized by being connected to each other. 12. An analog filter circuit configured to obtain a high pass filter characteristic, further comprising means for subtracting the differential output signal of the analog filter circuit according to claim 11 from the corresponding differential input signal. 13. A voltage / current converter for converting a difference between a first input voltage and a second input voltage into a current signal proportional thereto, and a current signal converted by the voltage / current converter proportional thereto. A first current / voltage conversion unit for converting the voltage signal into a first voltage / current conversion unit, the voltage / current conversion unit having first and second input voltages supplied to a gate electrode. And first and second constant current sources connected to the source electrodes of the first and second PMOS transistors, and a first resistance element connected between the source electrodes and formed on a semiconductor substrate. , Third and fourth constant current sources connected to the drain electrodes of the first and second PMOS transistors, and drain and gate electrodes at the source and drain electrodes of the first and second PMOS transistors, respectively. Connected first, first Of and a NMOS transistor, the first,
In the second NMOS transistor, the difference between the first current source current and the third current source current and the difference between the second current source current and the fourth current source current are respectively bias currents. At this time, the signal currents obtained by dividing the difference between the first input voltage and the second input voltage by the value of the first resistance element are complementarily added, and the first current / voltage The conversion unit includes a third NMOS transistor connected to generate a signal current proportional to the signal current generated in the first NMOS transistor, and a second resistance element connected between the transistor and a fixed potential. And a signal amplifier that outputs a signal voltage proportional to the difference between the first input voltage and the second input voltage. 14. A fourth NM connected to the first current / voltage conversion unit so as to generate a signal current proportional to the signal current generated in the second NMOS transistor.
Differentially outputting a signal voltage proportional to the difference between the first input voltage and the second input voltage, further including an OS transistor and a third resistance element connected between the transistor and a fixed potential 14. The differential amplifier according to claim 13, wherein: 15. In the first current / voltage conversion unit, the second resistance element included in the first current / voltage conversion section has a characteristic that the resistance value variation is smaller than that of the first resistance element, and the first input 14. The differential amplifier according to claim 13, wherein the differential amplifier outputs a signal voltage that is proportional to the difference between the voltage and the second input voltage and is inversely proportional to the value of the first resistance element. 16. The first current / voltage conversion unit has a characteristic that the second and third resistance elements included in the first current / voltage conversion section have less variation in resistance value than the first resistance element. 15. The differential amplifier according to claim 14, wherein a signal voltage that is proportional to the difference between the first input voltage and the second input voltage and that is inversely proportional to the value of the first resistance element is differentially output. 17. In the first current / voltage conversion unit, the second resistance element included in the first current / voltage conversion unit is formed on the same semiconductor substrate as the first resistance element, and is substantially the same as the first resistance element. 14. The differential amplifier according to claim 13, wherein the differential amplifier outputs the signal voltage having a fixed gain proportional to the difference between the first input voltage and the second input voltage. 18. The first current / voltage conversion unit, wherein the second and third resistance elements included therein are formed on the same semiconductor substrate as the first resistance element, and the first resistance element is formed. 15. A signal voltage having a fixed gain, which has substantially the same resistance value variation as that of the first input voltage and is proportional to the difference between the first input voltage and the second input voltage, is differentially output. Differential amplifier. 19. A second current / voltage conversion unit for converting the current signal converted by the voltage / current conversion unit into a voltage signal proportional thereto, wherein the second current conversion unit includes the first current / voltage conversion unit. A fifth NMOS transistor connected to generate a signal current proportional to the signal current generated in the NMOS transistor, and a fourth resistance element connected between the transistor and a fixed potential. A resistance element is formed on the same semiconductor substrate as the first resistance element and has substantially the same resistance variation as the first resistance element, and the first input voltage and the second input voltage are the same. 16. The differential amplifier according to claim 15, wherein the differential amplifier outputs a signal voltage having a fixed gain proportional to the difference between the two. 20. A second current / voltage conversion unit for converting the current signal converted by the voltage / current conversion unit into a voltage signal proportional thereto, wherein the second current conversion unit is the first current / voltage conversion unit. And a second NMOS
A fifth and sixth NMOS transistor connected to generate a signal current proportional to the signal current generated in the transistor, and fourth and fifth resistance elements connected between the transistor and a fixed potential; The fourth and fifth resistance elements are formed on the same semiconductor substrate as the first resistance element and have substantially the same resistance variation as the first resistance element, and the first input voltage 17. The differential amplifier according to claim 16, which differentially outputs a signal voltage having a fixed gain proportional to the difference between the input voltage and the second input voltage. 21. A differential amplifier according to claim 20, a non-inverted output of the first current / voltage converter and an inverted output of a second current / voltage converter of the differential amplifier, and the first amplifier. First and second capacitive elements respectively connected between an input voltage, an inverting output of the first current / voltage converting section of the differential amplifier and a non-inverting output of the second current / voltage converting section A variable capacitance circuit comprising: a third capacitance element and a fourth capacitance element respectively connected between an output and the second input voltage. 22. A means for shifting the DC voltage of the differential input voltage signal and attenuating the AC amplitude, a buffer means for outputting the differential signal obtained by this means with a low impedance, and an output of the buffer means. An analog filter circuit configured to obtain a high-pass filter characteristic by subtracting an output signal of a low-pass filter including a resistance element and a capacitive element as an input signal from the input signal, wherein the low-pass filter is a differential signal of the differential signal. A first resistance element whose one end is connected to the output of the buffer means that receives a non-inverted signal at its input; a second resistance element connected between the first resistance element and a fixed potential; and the differential signal. A third resistance element whose one end is connected to the output of the buffer means for receiving an inverted signal of the input, and between the third resistance element and a fixed potential. 22. The variable capacitance circuit according to claim 21, and the variable capacitance circuit according to claim 21, wherein the first input terminal of the differential amplifier included in the variable capacitance circuit is the first resistance element and the second resistance. The second input terminal of the differential amplifier is connected to a connection point with an element, and the second input terminal of the differential amplifier is connected to a connection point between the third resistance element and the fourth resistance element. Analog filter circuit. 23. A CMOS comprising the analog filter circuit according to claim 22, wherein the frequency characteristic of the analog filter circuit approximates an inverse characteristic of a frequency characteristic of a signal received using a metal conductor cable as a transmission line. A semiconductor integrated circuit for a physical layer for ATM-LAN realized by using the technology. 24. An ATM-LAN having a size mountable in a personal computer, comprising at least the semiconductor integrated circuit according to claim 23 mounted thereon, and formed into an IC card or a circuit board. Interface card.