JPH09274513A - Programming device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a program preparing function with which a circuit combining three kinds of flow of a ladder chart, sequential function chart(SFC) and function block(FB) drawing can be prepared. SOLUTION: A symbol common for respective expression forms and dedicated symbols are provided and the symbol, for which it is not necessary to be provided especially for each expression form, is commonly provided so that ladder chart dedicated symbols can be defined as a contact (a), contact (b), coil, set and coil, SFC dedicated symbols can be defined as transition and step and FB drawing dedicated symbols can be defined as function and dot. Thus, even the circuit combining symbols in different expressions such as a circuit mixing the ladder chart and the FB drawing can be described.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for creating a program circuit diagram for operating a programmable controller, and more particularly to a programming device for a circuit display in a program loader, which is particularly effective for an expression mixed circuit. A compilation method for creating well and expanding to an intermediate language.

[0002]

2. Description of the Related Art Conventionally, a circuit created for a programmable controller (hereinafter referred to as PLC) has a ladder diagram 221, a function block diagram (hereinafter referred to as FB diagram) 222, and a sequential function as shown in FIG.・ Chart (hereinafter referred to as SFC) 223
Is generally known. Details of these three main forms of expression are as follows. 1. [Ladder diagram 221] ... A circuit that is used when creating a sequence circuit and that combines a-contact, b-contact, a coil, and the like. 2. [FB diagram 222] ... This is a developed circuit of the ladder diagram, in which processing such as addition and subtraction is expressed as one box. 3. [SFC223] ... This is a circuit in which the process is divided for each box and these are illustrated in a flowchart image.

In terms of data flow, the ladder diagram 221 is a power flow in the sense that electricity flows, the FB diagram 222 is a data flow in the sense that data flows, and the SFC 223 is for processing. Since it means control, it can be called a control flow.

Each circuit can be described / compiled by the algorithm shown in FIG. 25, as long as it has a symbol structure whose expression form is unified as one circuit. Further, this figure shows an algorithm for developing (compiling) a circuit diagram described by a program loader into a machine language operable by PLC. That is, in FIG.
Then, in step 21, one circuit is taken out from the circuit creation screen, and in step 22, it is determined whether or not the circuit is a ladder diagram representation. If it is a ladder diagram representation, the ladder diagram is compiled in step 22a. Is performed, and the process ends in step 25. If the circuit is not the ladder diagram representation in step 22, the process proceeds to step 23, it is determined whether the circuit is the SFC representation, and if it is the SFC representation, the SFC is compiled in step 23a,
The process ends in step 25. Also, step 23
If the circuit is not in SFC expression, the process proceeds to step 24, the FB diagram is compiled, and the process ends in step 25. In this way, one circuit is composed of only a specific expression format, and each time the circuit has a function of expanding to an intermediate language by a compiler of the specific expression format. As described above, conventionally, there is a compiler for each expression format of each circuit, and each circuit is expanded into an intermediate language. Further, conventionally, a symbol for exclusive use of ladder diagram = a contact, b contact, coil, set, coil, function,
Dot. SFC symbols = transitions, steps, dots. FB diagram dedicated symbol = function, dot. As described above, the ladder diagram, the SFC, and the FB diagram were not designed to have symbols that need not be provided for each expression format.

[0005]

However, since the program created by the above program loader accesses the auxiliary information and displays it to the user, if one module composed of a large circuit exists, the access is performed. There is a problem in that the efficiency is low and the program creation efficiency is reduced for the user. A common problem of the present invention is to improve access efficiency, and for that purpose (1) provides a program creation function capable of creating a circuit that combines the three types of flows of the ladder diagram, SFC, and FB diagram described above. To do. (2) To provide a programming device capable of compiling an SFC circuit described as one SFC circuit, instead of describing a transition condition as a hierarchical part. (3) For one circuit that combines the ladder diagram and the FB diagram, a compile error occurs, so there is a great need as a user to compile a circuit with mixed expressions, but at present it has not been realized. (EN) Provided is a circuit for ladder diagram representation, a circuit for FB diagram representation, a circuit for mixed representation of ladder diagram and FB diagram, and a compile system capable of expanding any of the above circuits into an intermediate language. (4) In the program creation, the intermediate language is visually expressed, and therefore the symbols are described and created. For this reason, the symbol has an input terminal and an output terminal, and the positions of the input terminal and the output terminal are fixed. To realize a program that allows you to freely specify this terminal position, Provide terminal information managed by. (5) In program creation, even when one module is created, information access related to it is performed. As the size of one module increases, the number of times of information access also increases proportionally. Therefore, it is an object of the present invention to provide a program creation device capable of improving this efficiency. (6) Since there are hierarchical symbols and transitions / macrosteps / actions in SFC that can be hierarchically described, it is necessary to provide a compiling method for synthesizing separately existing hierarchical parts into one module. . (7) When a program is created, it is always necessary to create it in module units. Therefore, a program creation device that can create a program in multiple circuit units rather than in module units is provided. thing. (8) It is to provide a module combining function for finally creating one module by combining the plurality of circuits created in (7) above.

[0006]

In order to solve the above problems, the first means of the present invention uses a ladder diagram symbol and an FB diagram symbol in a program loader for creating a program that operates on a PLC, The feature is that it is possible to compile a ladder diagram circuit and expression mixed circuit in which circuits are arbitrarily combined into an intermediate language.
The second means is a sequential function chart program of the program loader created on the PLC, and the transition condition part of the circuit directly linked to the transition is not used as the hierarchical description of the transition condition of the transition. It is characterized by having a compiler that cuts out and expands into an intermediate language. Therefore, as a first means, (1) a symbol common to each expression format and a dedicated symbol are provided, and the ladder diagram dedicated symbol =
S contact, a contact, b contact, coil, set, coil, SFC
Dedicated symbols = transitions, steps, FB diagram dedicated symbols = functions, dots, etc. By not giving symbols that do not need to be provided for each expression format in common, mixed circuits such as ladder diagrams and FB diagrams can be used. , So that it is possible to describe even a circuit of a combination of symbols of different expressions, and (2) pay attention to the circuit of the transition condition linked to the transition, and
Compile the FC circuit. As a transition condition part, a transition is cut out and the transition is compiled as an output operand. Finally, the transition position is embedded in the corresponding transition. (3) Based on the mixed circuit of the ladder diagram and the FB diagram, the separation position of the expression form is determined. As the separation position, a mark at the beginning position and a mark at the end position are set for each symbol, and by taking the marks, the ladder diagram portion to be connected to the link in the FB diagram is determined (in this embodiment, it is set as Circuit)). The start position is determined by checking that the FB diagram symbol is on the input side of the ladder diagram symbol (FB diagram symbol is the start position).
Make sure that there is no symbol linked to the input side of the ladder diagram symbol (the ladder diagram symbol itself is the start position). To determine the final position, use F on the output side of the ladder diagram symbol.
If there is a B diagram symbol, the ladder diagram symbol itself is the final position. If there is no symbol linked to the output side of the ladder diagram symbol, the symbol itself is the final position. When there is an FB diagram symbol on the output side of the dot symbol and only the ladder diagram symbol is input to the dot symbol, the dot symbol is the final position.

Further, according to the second means of the present invention, the ladder diagram notation part is converted into the representation of the FB diagram for the sub-circuit detected by the above-mentioned first means, and then the compiler of the FB diagram. To develop mixed expression circuits. Here, three processes are performed. (1) Expansion of parallel condition part to FB diagram [Case 1] In the case where there is a ladder diagram symbol in parallel between dot symbols, and an AND function and an OR function appearing in the process of the second means Put together in an OR function. [Case 2] Although it does not correspond to Case 1, if there is a dot symbol having at least one head position on the input side, it is combined into an OR function.

Expansion of the serial condition part to the FB diagram: Pay attention to the ladder diagram symbol and the AND function and OR function that appeared in the process of the second means, and when they are linked in series. Are combined into an AND function.

Expansion of the temporary condition to the FB diagram ... When the following condition is satisfied, processing equivalent to the summarization to the AND function is performed, that is, (1) the link destination on the output side of the ladder diagram symbol is a dot symbol. If there is. (2) There is one input of the dot symbol of (1) described above. (3) When there are two or more link destinations on the output side of the dot symbol.

When the above three conditions are satisfied, AND
Create a new function and change the link. By the above means, the ladder diagram notation part in the mixed circuit is
It can be expanded to the link of the figure, and can be expanded to the intermediate language by the FB figure compiler after that. Means 1 and 2
19 and 20 show the algorithm of the compiler including the above. In FIG. 19, starting at step 300, a ladder symbol is designated as a starting point for tracing the input side at step 300a, the input side of the ladder diagram symbol is traced at step 301, and input at step 302. It is determined whether the side is the FB diagram symbol. If it is an FB drawing symbol, the FB drawing symbol is set to the head position in step 302a, and if it is not an FB drawing symbol, step 30
At 3, the presence / absence of a link on the input side is determined. If there is no link, the process returns to step 301 to trace the input side of the ladder diagram symbol. If there is a link, in step 302b,
Set the ladder diagram symbol as the start position. When the processes of 302a and 302b are completed, the process proceeds to step 304, the ladder diagram symbol is designated as a starting point for tracing the output side, the output side of the ladder diagram symbol is traced at step 305, and the process proceeds to step 306. Then, it is determined whether or not the output side is the FB figure symbol. If it is the FB figure symbol, the ladder figure symbol is set as the head position in step 306a. If it is not an FB diagram symbol, the process proceeds to step 307 to determine whether or not there is a link on the output side. If there is no link, the process proceeds to step 307a to set the ladder diagram symbol as the head position. If there is a link, the process returns to step 305.
When the steps 306a and 307a are completed, the process is completed in step 308.

Further, as shown in FIG. 20, the processing of the means 1 takes out one circuit from the circuit creation screen in step 41, and judges the presence or absence of the ladder diagram symbol in step 41a. If there is a symbol, the sub-circuit is extracted in step 42, the process proceeds to step 42a, it is determined that the FB plotting for all sub-circuits is completed, and if it is not completed, the process proceeds to step 43 and the ladder Figure symbol AN
D-linking is performed, and in step 44, the ladder diagram symbol is OR-linked, and the process proceeds to step 45 where the ladder diagram symbol is made temporary, and the process proceeds to step 45a where it is determined whether or not the above three processes are performed. If there is, the process returns to step 43 to execute the above three processes. If not, it returns to step 42a and it is determined that the FB plotting for all the sub-circuits is finished. If it is finished, the symbol type of the ladder diagram symbol is changed at step 46, and the routine proceeds to step 47 and FB The compile for the figure circuit is called, and the processing ends.

The basic processing in the means 2 is, as shown in FIG. 21, (1) shows the FB diagram expansion of the serial condition part. Of the ladder diagram symbols 51a, 51b, 51c, the ladder diagram symbols 51b, 51c are AND functions. It is shown that it is a processing target of No. 51. (2) shows the FB diagram expansion of the parallel condition part, and the ladder diagram symbols 52a, 52b, 52c, 5
Of 2d, the ladder diagram symbols 52b and 52c are to be processed by the OR function 52. (3)
The FB diagram expansion of the temporary condition is shown, and it is shown that the ladder diagram symbols 53a, 53b, and 53c are to be processed by the AND function 53. (4) The input terminal information and the output terminal information of the symbol, which has been fixedly provided in the past, are combined into one and common terminal information having a terminal number and an input / output classification is provided, which allows the terminal position to be variably changed. It was possible to specify. (5) A layer part symbol that means the connection within one module is provided, and at the time of program creation,
It seems as if one module is created, but in reality, it is possible to create it by dividing it into multiple sheets. (6) The following two processes are performed. Compile for each sheet and create an intermediate language. However, in the case of a layer portion symbol, the intermediate language including the pseudo instruction and the sheet name corresponding to the layer portion is expanded. With respect to the compilation results of all the sheets that make up one module, the hierarchical part is synthesized, and thereby one module is completed.
(7) One module is managed so as to be composed of a plurality of sheets (pages), so that one module can be created separately. (8) A module combining process for connecting to one module is performed by providing a table for managing an intermediate language obtained by the result of (7) and referring to the table. Therefore, by converting the ladder diagram symbol into the FB diagram symbol, it is possible to convert the FB diagram into the ladder diagram or the ladder diagram into the FB diagram without considering the mixed circuit of the ladder diagram and the FB diagram. Become. Therefore, regardless of whether the circuit is a ladder diagram symbol only circuit, an FB diagram symbol only circuit, or a circuit in which a ladder diagram and an FB diagram are mixed, it is only necessary to relink the ladder diagram symbol section and use the FB diagram compiler. It becomes possible to expand to an intermediate language.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. In the figure, the same reference numerals are used for the same components as in the conventional example. In FIG. 1, 1
2 is a ladder diagram similar to that of the conventional example, and 2 is an FB diagram that operates similarly to the conventional example. Although the dot symbols 1a and 1b are used in the ladder diagram 1, these dot symbols 1a and 1b are AN depending on the connection state of the contact symbols.
It should be interpreted as D, OR. Comparing the ladder diagram 1 and the FB diagram 2 with each other, the timer function (TONh) 1c of the ladder diagram 1 and the timer function (TON of the FB diagram 2 shown in FIG.
h) As for the description method of 2a, the way of holding the symbol for the ladder diagram 1 is prepared similarly to the dot symbols 1a and 1b. However, from the user's point of view, both circuits have the same operation and may be mixed circuits. Therefore, in this embodiment, like the circuit 3, the ladder diagram 1 and the FB diagram 2 are allowed to coexist at a certain position. In order to satisfy the requirement for the ladder diagram notation 3a, the program device describes the dot symbol and the function symbol as the same treatment, so that any mixed circuit can be described. It represents what you have done. FIG. 2 shows the transition condition S
FIG. 3 is a diagram showing an algorithm for compiling a circuit mixed with an FC circuit, and FIG. 3 is a circuit showing a specific example of the algorithm. In FIG. 2, by step 21,
First, the SFC1 circuit is compiled, the transition condition circuit part is separated in step 22, the transition condition part is compiled in step 23, and the transition condition part is embedded in the SFC circuit in step 24. . The circuit corresponding to steps 21 to 24 is S shown in FIG.
In the FC circuit, the transition condition part 31a is described as a ladder diagram in this figure, but the compilation result of this SFC circuit is (S31),

[0014]

[Equation 1]

## EQU1 ## Next, the transition condition part is separated (S
32). TRANSITIO for this transition condition part
Replace N (D) with a normal operand symbol (S
33). Next, the separation circuit with this symbol replaced is compiled. The result of compiling this transition condition is (S3
4). Finally, the transition condition is embedded in the SFC circuit.
The result is

[0016]

[Equation 2]

## EQU1 ## Hereinafter, description will be made based on the circuits 41 to 43 in FIG. In the figure, 41 is a conventional ladder diagram circuit, 41a is a ladder diagram a contact symbol, 4
1b is also a coil symbol. 42 is an example of a circuit (part 1) in which a simple ladder diagram and FB diagram are mixed.
a is a ladder diagram a contact symbol, 42b is an operan symbol, and 42c is a function symbol. 43 is an example of processing of a circuit (part 2) in which a complicated ladder diagram and FB diagram are mixed,
43a corresponds to the contact symbol 41a of the ladder diagram a, and 43b to 43d represent symbols of the ladder diagram, 43e, 4 and 4.
3f is equivalent to the dot symbol in the ladder diagram, 4
3g corresponds to the function symbol of the ladder diagram. When these are applied to the conventional algorithm shown in FIG. 25 described above, it is impossible to compile except for the ladder diagram circuit 41, but in the present embodiment, the algorithm of FIG. 15 expands to an intermediate language. is there. In FIG. 15, the constituent elements of one circuit of the unfolding method (1) of (1) are the a-contact (input 1, input 2) of the ladder diagram symbol and the coil (output 1) of the ladder diagram symbol. In S42 of FIG. 15, a sub circuit that is a unit for converting a ladder diagram symbol into an FB diagram symbol is extracted. Since all are ladder diagram symbols, the number of sub-circuits is 1 (circuit 51 in FIG. 5). Next, the AND function is added and the a contact is relinked by the process of S43 (circuit 52 in FIG. 5). Next, by the processing of S46,
The a-contact symbol and the coil symbol are changed to the operand symbol (circuit 53 in FIG. 5). Finally, F of S47
It is expanded into an intermediate language by the compiler in FIG. B (circuit 54 in FIG. 5).

The components of one circuit of the expansion method (2) of (2) are the a-contact (input 1, input 2) 61a of the ladder diagram symbol and the operand symbol (input 3) 61b of the FB diagram symbol in FIG. , The function symbol 61c. By S42 of FIG. 15, the number of sub-circuits = 1 (circuit 61 of FIG. 6). Next, S4 in FIG.
By the processing of 3, the AND function is added and the a contact is relinked (circuit 62 in FIG. 6). Next, S46 in FIG.
By the processing of 1, the a contact symbol is changed to the operand symbol (circuit 63 of FIG. 6). Finally, S4 in FIG.
It can be expanded into an intermediate language by the FB diagram compiler of FIG. 7 (64 in FIG. 6).

The sub-circuit in the expansion method (3) of (3) is, as shown in FIG. 7, a sub-circuit 1 (72a) = a contact symbol (inputs 1 to 5,
Input 8) + dot symbol 1, 2 + coil symbol (output 1) Sub circuit 2 (72b) = a contact symbol (inputs 6 and 7) Sub circuit 3 (72c) = function symbol (F1) + a contact symbol (input 9) + Coil symbol (output 2) It is not a ladder diagram symbol like the sub-circuit 3 (72c), but if the output of the function symbol is linked to the ladder diagram symbol, it is included as a processing target symbol. FIG.
In S42, the sub-circuit, which is a unit for converting the ladder diagram symbol into the FB diagram symbol, is extracted. In this circuit, the number of sub-circuits = 3 (circuit 72 in FIG. 7). In this case, the function symbol (F1) is an FB diagram symbol, but three sub-circuits are detected at the boundary.

Next, the re-linking for the sub-circuits will be performed, and FIG. 8 and FIG. 9 are developments of the processing relating to the sub-circuit 1 (72a) in FIG. As actual processing, in FIG. 8, for the sub-circuit 1 (circuit 81), the ladder diagram symbol is AND-linked (circuit 82) ... Input 4 and input 5 are the target ladder diagram symbol OR-link (circuit 83). ) ...
Input 4 and input 5 are targets. In FIG. 9, the ladder diagram symbol is AND-linked (circuit 91) ... Input 3 and OR function 5 is the target ladder diagram symbol OR-link (circuit 92) ...
Dot symbol 1 is targeted Temporization of ladder diagram symbol (circuit 93) ...
The target is the dot symbol 2. As described above, the sub circuit is expanded to the FB diagram symbol.

FIG. 10 is a process relating to the circuit 101 corresponding to the sub-circuit 2 (72b) in FIG. 7. Input 6 and input 7 of the target sub-circuit 101 are A of the ladder diagram symbol.
It can be processed only by the ND link circuit 102.

FIG. 11 shows the processing of the circuit 111 corresponding to the sub-circuit 3 (72c) of FIG. 7, which can be processed only by the AND linking circuit (112) of the ladder diagram symbol.

FIG. 12 (121) shows the connection of the circuit diagrams of the above three sub-circuits after relinking.
22) is an intermediate language obtained as a compilation result. (4) In FIG. 13 and FIG. 14, FIG. 13 shows a conventional circuit diagram and information about its symbol. The symbol terminals are divided into an input terminal and an output terminal. In addition, the terminal order expanded to the intermediate language for each input terminal and output terminal gives meaning to the link order of the terminal information, and the terminal number for compilation is
It means the order of operands for expanding the operands for the function into an intermediate language. In the symbol information of this embodiment, first, the terminal information is collected into one terminal information without being divided into input and output. Further, by adding the terminal number and the input / output classification to the terminal information, it is possible to normalize the information on the symbol and the terminal. When the terminals of the function symbol are freely described, the order of the input / output terminals can be identified by determining only the terminal number and the input / output section, and thus the compilation becomes possible.

(5) In FIG. 15, when a circuit diagram is created by an ordinary program creating device, information about operands is mainly displayed and written at the time of writing the circuit, and access to many related information occurs. To do. Therefore,
When creating a large-scale program, it is necessary to take measures to improve the efficiency of the device. As in the circuit 151 shown in the figure, a hierarchical portion symbol is provided in a program that is considered to be large in scale to some extent. This is for dividing and creating a program that is actually one. With this symbol, for example, when a part of the circuits 152 in the hierarchical portion symbol is modified, conventionally, information about all circuits including it is accessed, whereas in the present embodiment, the information in the hierarchical portion symbol is accessed. You only need to access information about the sheet. Therefore, the efficiency of program creation is improved. (6) FIG. 16 shows an algorithm up to the synthesis of the hierarchical portion using the circuit of FIG. (S161)
Thus, it is determined that the sheet 1 and the sheet 2 are the corresponding sheets, and the next compile result is obtained by (S162).

Compile result of sheet 1 Compile result of sheet 2

[0026]

(Equation 3)

At (S163), the pseudo instruction [FROM 7] is extracted from the compilation result of the sheet 1,
By (S164), the following compilation result is obtained.

[0028]

(Equation 4)

(7) FIG. 17 shows a conventional program generation device, and the minimum unit created by this device is one module (171a), (171b). However, what the user ultimately needs is not that one module is fixed, but that it is managed as a document. Therefore, it does not matter what order the components of one module are.

In FIG. 18, one module can be divided into a plurality of sheets to be created. In other words, when creating a program, it is possible to describe the circuit on a sheet so that it can be easily understood as a document.

(8) In order to combine a plurality of sheets prepared in (7) described above and to prepare a necessary module,
The connection table shown in FIG. 18 is prepared. While referring to this table, it becomes possible to create a module which is the final form by a function called module combination.

FIG. 22 is a diagram showing the structure of the symbol (OR node symbol) of the present invention. Comparing this figure with the structure of the conventional symbol (OR node symbol) of FIG.
It can be seen that a layer portion sheet 220a is added to the symbol of the present invention in order to link with the layer portion, and “input / output” is unified to combine the terminal symbols into one.

FIG. 23 is a diagram showing the structure of the terminal symbol of the present invention. Comparing this figure with the structure of the conventional terminal symbol of FIG. 27, conventionally, the link order of the terminal symbols means the terminal number. On the other hand, in the case of the present invention, the terminal symbol is given the terminal number 230a. Further, instead of tracing from the node symbol as in the conventional case, the terminal symbol is provided with the I / O section 230b. Further, the present invention assumes that a plurality of terminal symbols of one node symbol are linked to the same node symbol, and has a node symbol pointer 203c in order to link the terminal symbols.

[0034]

As described above, according to the present invention, there is provided a program creating function capable of creating a circuit in which three kinds of flows of a ladder diagram, an SFC, and an FB diagram are combined, and transition conditions are hierarchized. Since it is possible to provide a programming device capable of compiling an SFC circuit described as one SFC circuit rather than as a part, it is possible to improve access efficiency. In addition, a compilation error does not occur for one circuit that combines the ladder diagram and the FB diagram, and one circuit that represents the ladder diagram,
One circuit for FB diagram representation, one circuit for mixed representation of ladder diagram and FB diagram, any of the above circuits can be expanded into an intermediate language, and even if there is one module composed of a large circuit, access to it It is possible to improve efficiency.

[Brief description of drawings]

FIG. 1 is a diagram of a description example regarding a mixed circuit of a ladder diagram and an FB diagram in an embodiment.

FIG. 2 is a diagram of an algorithm for combining transition condition parts of an SFC circuit in an embodiment.

FIG. 3 is a diagram in which a transition condition part of the SFC circuit in one example is described in a ladder diagram representation.

FIG. 4 is a diagram of a description example of a mixed expression circuit according to an embodiment.

FIG. 5 is a diagram illustrating a process of developing one circuit example of only a ladder diagram representation in one embodiment.

FIG. 6 is a diagram illustrating a process of developing one circuit of the expression mixed circuit according to the embodiment.

FIG. 7 is a diagram illustrating a process of developing one circuit of the expression mixed circuit in one embodiment.

FIG. 8 is a diagram illustrating a process of developing one circuit of the expression mixed circuit in one embodiment.

FIG. 9 is a diagram illustrating a process of developing one circuit of the expression mixed circuit according to the embodiment.

FIG. 10 is a diagram illustrating a process of developing one circuit of the expression mixed circuit in one embodiment.

FIG. 11 is a diagram illustrating a process of developing one circuit of the expression mixed circuit according to the embodiment.

FIG. 12 is a diagram illustrating a process of developing one circuit of the expression mixed circuit according to the embodiment.

FIG. 13 is a diagram showing an example of a conventional circuit and its symbol information.

FIG. 14 is a diagram showing an example of a circuit and its symbol information in one embodiment.

FIG. 15 is a diagram of an example of module separation using hierarchical symbols in one embodiment.

FIG. 16 is a diagram illustrating an algorithm for compiling a hierarchical portion symbol and synthesizing the hierarchical portion symbol according to an embodiment.

FIG. 17 is a diagram of an example of creating a conventional module.

FIG. 18 is a diagram of an example of joining modules from sheets in one embodiment.

FIG. 19 is a diagram illustrating an algorithm of sub-circuit extraction regarding means 1 according to an embodiment.

FIG. 20 is a diagram illustrating a compilation algorithm according to an embodiment.

FIG. 21 is a diagram illustrating an algorithm for extracting a sub-circuit related to the means 2 in the embodiment.

FIG. 22 is a diagram of symbols in one embodiment.

FIG. 23 is a diagram of terminal symbols in one embodiment.

FIG. 24 is a diagram of a circuit description example for each conventional expression format.

FIG. 25 is a diagram illustrating a conventional circuit compilation algorithm.

FIG. 26 is a diagram of a conventional symbol.

FIG. 27 is a diagram of a conventional terminal symbol.

[Explanation of symbols]

 1 Ladder Diagram 1a Dot Symbol 1b Dot Symbol 2 FB Diagram Circuit 2a TONh 3 Mixed Circuit 3a Ladder Diagram Notation 31 Circuit 32 Separation of Transition Conditions 33 Transition Condition Compilation 41 1 Circuit Only Ladder Diagram Expression 42 Mixed Expression Circuit 43 Mixed Expression Circuit 51 Extraction of Sub Circuits 52 AND Linking of Ladder Diagram Symbols 53 Changing Symbol Types of Ladder Diagram Symbols 54 Compiling of FB Diagrams 61 Extraction of Sub Circuits 62 Making AND Link of Ladder Diagram Symbols 63 Changing Symbol Types of Ladder Diagram Symbols 64 FB Diagrams Compilation of

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Haruhiko Haga Inventor, Fuji Town, Hino City, Tokyo 1 Fuji-Facom Control Co., Ltd.

Claims (8)

[Claims] 1. In a program loader for creating a program that operates on a programmable controller, a ladder diagram circuit and expression mixed circuit in which circuits are arbitrarily combined are compiled into an intermediate language without using a ladder diagram symbol and a function block diagram symbol. A programming device characterized by improving access efficiency by making it possible. 2. A sequential function chart program of a program loader created on a programmable controller, wherein a transition condition part is cut out for a circuit directly linked to a transition, not as a hierarchical description of the transition condition. A programming device characterized by having a compiler for expanding to an intermediate language to improve access efficiency. 3. In a program loader for creating a program that operates on a programmable controller, when compiling a mixed circuit of a ladder diagram and a function block diagram, the notation range as a ladder diagram is determined and the ladder diagram notation part is set as a function. It is developed into a block diagram, and by converting it into a circuit of a function block diagram that corresponds one-to-one with an intermediate language, it has the function of compiling a mixed expression circuit and improves access efficiency. Programming device. 4. In a program loader for creating a program that operates on a programmable controller, terminal information managed for each symbol is set so that the terminal position of each symbol of the created circuit can be freely set. A programming device characterized by providing a symbol data structure for both input and output, enabling free designation of symbol patterns, and improving access efficiency. 5. A program loader for creating a program that operates on a programmable controller is provided with hierarchical symbols as symbols that make up the program, and one module is separated into a plurality of sheets by the symbol to improve program creation efficiency. Let
A programming device characterized by improved access efficiency. 6. In a program loader for creating a program that operates on a programmable controller, a circuit in which hierarchical symbols are described is expanded into an intermediate language in which a pseudo instruction as a marker of hierarchical symbols is added to the compilation result of each sheet. A programming device characterized in that access efficiency is improved by searching the pseudo instructions and synthesizing all of the compiled results of the sheet to create one module. 7. A program loader for creating a program that operates on a programmable controller, comprising:
Programming that is characterized by dividing a module into modules and storing them so that a circuit that constitutes one module can be divided and stored in an intermediate language to improve the access efficiency. apparatus. 8. The access efficiency is improved by combining the intermediate languages divided according to claim 7 into one module so as to have a module combining function for creating a module operating on a programmable controller. And programming equipment.