JPH09270993A - Audio and video data recording device and its method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To record audio and video data by compensating a difference of a delay time between compressed video data and non-compression audio data without the need for a delay memory. SOLUTION: A pack circuit 180 stores compression video data received with a delay with respect to non-compression audio data to four sectors in order in a memory circuit 16. On the other hand, the pack circuit 180 stores audio data to an idle area of a preceding sector to the compression video data, in order to compensate a time required for compression coding processing. When the pack circuit 180 stores the compression video data corresponding to the audio data stored in the idle area precedingly, an external code encoder 184 moves the audio data in the idle area to a prescribed area of a recording block to add an error correction code (external code). The audio data with the external code added thereto and the compression video data are recorded on a VTR tape 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an audio / video data recording apparatus and method for compressing and encoding at least input video data and recording the same with input audio data in a recording medium such as a video tape.

[0002]

2. Description of the Related Art For example, in a video cassette tape recorder (VCR device), audio data and video data (audio / video data) collected and photographed at the same time are converted to a video tape (VTR tape). When recording, video data having a very large data amount (a very high data rate) is usually compression-encoded at a high compression rate. In general, when video data is compression-encoded at a high compression rate, the processing time required for compression-encoding becomes long and a large delay occurs. On the other hand, since the original audio data having a small data amount is recorded uncompressed or after being compressed and encoded at a low compression rate and then recorded, only a very short delay time is given.

Further, recently, in order to obtain a high compression rate while maintaining a high image quality, MPEG (moving) for compressing and encoding image data so that a plurality of frames have a correlation.
In many cases, compression coding is performed by a method such as picture expert group). In this way, multiple frames (GOP; grp
When the video data is compression-encoded in units of up of pictures, the time required for the compression encoding process becomes longer, and the video data after the compression-encoding process has a large delay.

In order to compensate for the difference in delay time between the audio data and the video data described above, a method of giving a delay to the input audio data and adjusting the timing with the compressed video data after the compression process is used. Conceivable. As described above, in order to give a delay to the audio data, a method of providing a delay memory for delaying the input audio data is often adopted in the audio data input stage.

However, if the difference in delay time between audio data and video data becomes very large, the capacity of the delay memory provided in the input stage also increases. Further, if an attempt is made to compensate for the difference in delay time by providing a delay memory in the input stage, the capacity of the delay memory is changed each time the compression rate for audio data and video data is changed, or
It becomes necessary to change the read address and the write address. That is, every time the compression rate for audio data and video data is changed, the hardware of the VCR device must be changed.

The present invention has been made in view of the above-mentioned problems of the prior art. The present invention eliminates the difference between the delay times of video data and audio data without using a delay memory for compensating the compression processing time of video data. An object of the present invention is to provide an audio / video data recording device and method capable of compensation.

Further, the present invention provides an audio / video data recording apparatus and method capable of compensating for the difference in delay time even if the difference in delay time between audio data and video data becomes very large. The purpose is to provide. Also,
SUMMARY OF THE INVENTION It is an object of the present invention to provide an audio / video data recording apparatus and method capable of changing the compression ratio for audio data and video data without changing the hardware.

[0008]

In order to achieve the above object, an audio / video data recording apparatus according to the present invention compresses input video data to obtain a compressed video having a delay time with respect to the input video data. Compression means for generating data,
Storage means for storing the input audio data corresponding to the input video data and the generated compressed video data, and error correction for adding an error correction code by associating the stored input audio data with the compressed video data. It has a code adding means and a recording means for accommodating the input audio data and the compressed video data to which the error correction code is added in a recording block and recording the same on a recording medium.

Preferably, the compression means compresses and encodes the input video data in GOP units, and the storage means stores the compressed video data of a predetermined number of GOPs and at least the delay time of the compressed video data. GO more than the specified number
The input video data corresponding to P is stored.

The audio / video data recording apparatus according to the present invention records compressed video data and uncompressed audio data on a recording medium such as a VTR tape. In the audio / video data recording apparatus according to the present invention, the compression means compression-codes the input non-compressed video data in GOP units by a compression coding method such as MPEG to generate compressed video data. . The generated compressed coded data is subjected to compression coding processing on the uncompressed video data at the time of input and the uncompressed input audio data that has a corresponding relationship with the uncompressed video data. There is a delay due to the time required.

The storage means is a memory used for error correction code addition processing for error correction during reproduction. Assuming that the compression encoding processing time for the input video data is equal to, for example, the input audio data corresponding to k GOPs and the time when the input video data is input to the audio / video data recording device, the storage means has a predetermined number. (n + k) input audio data are stored together with compressed video data corresponding to n GOPs. The error correction code adding means is, for example, i
Second, the voice data stored in the storage means and (i + k)
Next, the compressed video data stored in the storage means is associated with each other and the timing is adjusted, and an error correction code in a product code format is added to the associated audio data and compressed video data. The recording means accommodates the recording block of the audio data and the compressed video data to which the error correction code is added, and VT
Record on R tape.

In the audio / video data recording method according to the present invention, the input video data is compressed, compressed video data having a delay time with respect to the input video data is generated, and the generated compressed video data is predetermined. Of the input audio data corresponding to the input video data,
At least the stored compressed video data and a data amount corresponding to the delay time of the compressed video data are stored,
The stored compressed video data and the input audio data are associated with each other to add an error correction code, and the input audio data and the compressed video data to which the error correction code is added are accommodated in a recording packet and recorded in a recording medium. .

[0013]

Embodiments of the present invention will be described below. FIG. 1 shows an audio / video data recording apparatus 1 according to the present invention.
FIG. 3 is a diagram showing the configuration of FIG. In FIG. 1, components that are not directly related to the description of the embodiment of the present invention are omitted. As shown in FIG. 1, the audio / video data recording device 1 includes a recording unit 10, a recording head 20, a reproducing head 22, and a reproducing unit 30.

The recording section 10 comprises a compression encoding section 12, a first memory circuit 14, a second memory circuit 16 and an ECC encoder (ECC ENCODER) 18.
The compression encoding unit 12 is a compression encoding circuit (BIT RATE REDUCT
ION ENCODE) 120 and a memory circuit 122. The ECC encoder 18 is a pack circuit (PACK) 18
0, outer code encoder (OUTERECC ENCODER) 184, F
It is composed of an IFO circuit 188, a FIFO circuit 190 and an inner code encoder (INNER ECC ENCODER) 192.

The reproducing unit 30 includes an inner code decoder 32 (INNER
ECC DECODE), outer code decoder (OUTER ECC DECODER)
34, a JOG memory 36, and a decompression decoding unit 38. The outer code decoder unit 34 includes a non-tracking control circuit (NON TRACKING CONTROL) 340 and a memory circuit 34.
2, outer code decoder 344, JOG memory control circuit 34
6 and a depacking circuit 348. The decompression decoding unit 38 includes a delay memory 380, a decompression decoding circuit 382, and a memory circuit 384.

With these components, the audio / video data recording apparatus 1 compresses and encodes only the video data among the input uncompressed video data and audio data, and outputs the VT.
Record on R-tape 2. Further, the audio / video data recording device 1 reproduces the recorded audio data and the compressed video data, decompresses and reproduces the reproduced compressed video data, and outputs it together with the reproduced audio data.

In the audio / video data recording device 1, the compression coding circuit 120 of the compression coding unit 12 uses the memory circuit 122 to external devices such as a video data editing device and a video data transmission device (not shown). The uncompressed video data (INPUT VIDEO) input from the two frames (I frame and B frame) by the MPEG system, for example.
It is compression-encoded in units of GOPs, and is output to the pack circuit 180 of the ECC encoder 18 as compressed video data (REDUCTION DATA).

The time required for the compression encoding process of the compression encoding circuit 120 is, for example, GOP for the compression encoding circuit 120 and k uncompressed video data (INPUT VIDE).
O) corresponds to the time entered. Therefore, compressed video data (REDUCTION DATA) is not compressed video data (INPUT
VIDEO) and non-compressed audio data (AUDIO) input from an external device, a delay time corresponding to the time corresponding to the compression encoding processing of the compression encoding circuit 120 is generated. In other words, the compressed video data (REDUCTION DATA) has a delay time corresponding to k GOPs.

The pack circuit 180 of the ECC encoder 18
Using the memory circuit 14, compression encoded data (REDUCTION DATA) input from the compression encoding unit 12, uncompressed audio data (AUDIO) input from an external device, and system data shown in FIG. SYTEM AUX) is accommodated in a predetermined recording block and stored in the memory circuit 16.

2A to 2C are diagrams showing recording areas of audio data and compressed video data (recording blocks) stored in the memory circuit 16 shown in FIG. The memory circuit 16 is, for example, a 16 Mbit synchronous dynamic RAM (SDRAM) having a (512 × 2,048) word × 16 bit configuration, which has a 16-bit wide data bus.
As shown in FIG. 2C, the storage area of the memory circuit 16 is logically or physically divided into four sectors of (256 × 1,024) words for use.

As shown in FIG. 2B, each of the four sectors of the memory circuit 16 includes 1 GOP worth of audio data, video data, and an error correction code (outer code; ECC) generated by the outer code encoder 184. , Error Reduction Cod
It has a recording capacity for storing e), and these data are stored. Further, as shown in FIG. 2A, each segment obtained by dividing each sector into four in the column direction stores an error correction block composed of video data and an error correction code in order from the beginning in the row direction. Error correction block area (VIDEO ECC) and an error correction block area (AUDIO CH1, CH2,., CH4;
AUDIO CHx ECC) and a system data area (SYSTEM AUX AREA) that stores system data used for system control of the audio / video data recording device 1, and data corresponding to each of these areas is stored. . In the recording block, the recording unit in which the error correction code is associated with the audio data and the compressed video data is also referred to as an error correction block.

The dummy area (DUMMY) in FIG. 2 (A)
The audio packing area (AUDIO PACKING AREA) is actually an empty area. As can be seen from FIG. 2B, the audio packing area (AUDIO PACKING AREA) is 1
It has a capacity to store GOP's worth of voice data and error correction data, and therefore two G's are provided for each sector.
The voice data of OP can be stored together with the error correction code, and the memory circuit 16 as a whole can store voice data of eight GOPs together with the error correction code.

The outer code encoder 184 is the memory circuit 1
The audio data and the compressed video data stored in 6 are associated with each other. That is, the memory circuit 16 is the same GO
P compressed video data and audio data are associated with each other, an outer code is generated for the associated compressed video data and audio data, and the corresponding audio data and compressed video data are generated in a predetermined area of the recording block shown in FIG. Memorize with.

FIFO circuit 188 and FIFO circuit 1
Reference numeral 90 denotes a system clock signal (Sys.Freq .; system frequency) synchronized with uncompressed video data (INPUT VIDEO) and uncompressed audio data (AUDIO), and VT.
It operates in synchronization with a recording clock signal (REC Freq .; recording frequency) used for recording data on the R tape 2, and the outer code encoder 184 adds the outer code and is included in the recording block stored in the memory circuit 16. The audio data, the compressed video data, and the outer code are buffered and output to the inner code encoder 192.

The inner code encoder 192 adds an inner code to the audio data, the compressed video data, and the outer code input via the FIFO circuit 188 and the inner code encoder 192, and stores them in a recording block. A recording signal is generated by performing processing such as the above, and azimuth recording is performed on the VTR tape 2 via the recording head 20.

The reproducing head 22 is actually composed of, for example, two pairs of reproducing heads each having a positive azimuth angle and a negative azimuth angle (a positive azimuth head, a negative azimuth head, not shown). Further, the positive azimuth head and the negative azimuth head are two reproducing heads of the same azimuth angle, which are arranged on a drum (not shown) at intervals of one helical track for recording of the VTR tape 2. Have. Therefore, the reproducing head 22 has a total of 4
Each of these four reproducing heads reproduces the recording signal recorded on the VTR tape 2 by the recording unit 10 and outputs it as a reproducing signal to the inner code decoder 32.

In the reproducing section 30, the reproducing head 22
The reproduced signals reproduced by the respective reproducing heads are converted into digital audio data, compressed video data, and error correction code. Further, the inner code decoder 32 performs error correction on the compressed video data and audio data using the inner code included in the error correction code, and the non-tracking control circuit 340 of the outer code decoder unit 34 stores the data in the recording block. Output to. Such processing of the non-tracking control circuit 340 is also called non-tracking control.

The non-tracking control circuit 340 detects the audio data, the compressed video data and the error correction code obtained from each of the reproduced signals of the four reproducing heads of the reproducing head 22, and the inner code decoder 32 detects a few data errors. In order, a high priority is given and the data is stored in the memory circuit 342 in a format accommodated in the recording block.

The outer code decoder 344 performs error correction on the audio data and the compressed video data stored in the memory circuit 342 via the non-tracking control circuit 340 using the outer code included in the error correction code. The JOG memory control circuit 346 is used in the format in which the recording blocks are stored in order of priority in the order of occurrence of errors.
It is stored in the memory 36.

The JOG memory control circuit 346 controls writing and reading of audio data and compressed video data with respect to the JOG memory 36, and performs special reproduction such as so-called jog shuttle reproduction and frame advance reproduction in addition to normal reproduction. Perform processing. The JOG memory control circuit 346 outputs the audio data and the video data read from the JOG memory 36 to the depacking circuit 348 in a format accommodated in a recording block.

The depacking circuit 348 separates the audio data and the compressed video data contained in the recording block, outputs the separated audio data (AUDIO) to the delay memory 380, and decompresses the compressed video data in the decompression decoding section 38. Output to the decompression decoding circuit 382. The decompression decoding circuit 382
Decompression decoding processing is performed on the compressed video data input from the depacking circuit 348 by a method corresponding to the compression coding circuit 120 of the compression coding unit 12 to obtain uncompressed video data.
Output to external device as (OUTPUT VIDEO). The delay memory 380 delays the audio data (AUDIO) input from the depacking circuit 348 by a time corresponding to the decompression / decoding process of the compressed video data in the decompression / decoding circuit 382, and outputs the uncompressed audio data (AUDIO) as external data. Output to the device.

Hereinafter, referring to FIG. 3 and FIG.
The operation of the video data recording device 1 will be described. FIG.
FIG. 6 is a diagram showing an operation of the audio / video data recording device 1 shown in FIG. The compression encoding circuit 120 (FIG. 1) of the compression encoding unit 12 compression-encodes the uncompressed video data (INPUT VIDEO) at the timing shown in FIG.
8 to the pack circuit 180.

On the other hand, the uncompressed audio data (AUDIO) is input to the pack circuit 180, and at the timing shown in FIG.
The audio pack area (AUDIO
PACKING AREA) (Fig. 2). On the other hand, Fig. 3 (C) (Video Data Packing, System AUX Data Packi
ng), the compression encoding process in the compression encoding circuit 120 requires a time corresponding to, for example, about 2 GOPs (k = 2, to be exact, 3.5 frames).

Therefore, compressed video data (REDUCTION DATA)
The system data (SYSTEM AUX) is input to the pack circuit 180 with a delay of about 2 GOP from the uncompressed audio data (AUDIO). The pack circuit 180 inputs the compressed video data (REDUCTION DATA) and the system data (SYSTEM AUX) into the predetermined error correction block area of the sector preceding the uncompressed video data (FIG. 3A) by 2 GOP. (VIDEO ECC) and system data area (S
YSTEM AUX AREA). That is, the pack circuit 18
As shown in FIG. 3C, 0 indicates the compressed video data (REDUCTION DAT) in a predetermined area of each sector in the order of sector 0, sector 1, sector 2 and sector 3 of the memory circuit 16.
A) and system data (SYSTEM AUX) are stored.

In this way, the pack circuit 180 converts the compressed video data (REDUCTION DATA) and the like into the uncompressed video data (AUD
I / O) is stored in a sector that is two sectors ahead of the stored sector, so that audio data, compressed video data (REDUCTION DATA), and system data (SYSTEM AUX) included in the same GOP are stored in the memory circuit. It will be stored in the same 16 sectors.

The outer code encoder 184 operates as shown in FIG.
uter Encode), the audio data stored in the audio packing area (AUDIO PACKING AREA) of the memory circuit 16 in the order of sector 3, sector 0, sector 1, sector 2 ... AUDIO CH1, CH2,
Move to CH3, CH4; AUDIO ECC) and store. Further, the outer code encoder 184 is configured to detect the error correction block area.
An outer code is added to the compressed video data and the moved audio data stored in (VIDEO ECC, AUDIO ECC). The FIFO circuits 188 and 190 output the audio data, the compressed video data and the error correction code (outer code) stored in the memory circuit 16 to the inner code encoder 192.

As shown in FIG. 3D, the PAL system (6
(25/50 mode) when adding an inner code to audio data, video data and an outer code, the inner code encoder 192 first adds the outer code to the outer code encoder 184, and then the PAL audio data. , The video data and the system data are recorded on the VTR tape 2 after an internal code is added after a lapse of 2 GOP. Further, as shown in FIG. 3 (E), the NTSC system (525 /
In the case of adding the inner code to the audio data, the video data and the outer code in the 60 mode), the inner code encoder 1
In the numeral 92, after the outer code encoder 184 adds an outer code, the inner code is added to the PAL audio data, video data, and system data after a lapse of 1 GOP, and then recorded on the VTR tape 2. To do.

The processing of each component of the ECC encoder 18 for the audio data, video data, system data and error correction code (outer code) stored in the memory circuit 16 will be further described with reference to FIG. FIG. 4 (A)
3 to (D) are the memory circuit 16 at the time point a in FIG.
It is a figure which shows the memory content of (FIG. 1). As shown in FIG. 4A, at the time point a in FIG.
Is the audio pack area (AUDIO P
ACKING AREA), the compressed video data (REDUCTI) is stored in the error correction block area (VIDEO ECC) and system data area (SYSTEM AUX AREA) of sector 3 of the memory circuit 16.
ON DATA) and system data (SYSTEM AUX) are stored (point a in Fig. 3 (C), Video Data Packing, SYTEM Da)
ta Packing).

As shown in FIG. 4B, the outer code encoder 184 is in parallel with the processing of the pack circuit 180 shown in FIG. 4A and is in parallel with the audio packing area (AUDIO PACKING AREA) of the sector 2 of the memory circuit 16. ) Move the audio data stored in) to the error correction block area (AUDIO ECC), and move the audio data and the error correction block area (VIDEO ECC).
And an outer code for the video data and system data stored in the system data area (SYSTEM AUX AREA) is generated and added (time a between FIG. 3 (C) and (D),
Outer Encode). Note that when the outer code is generated, the data stored in the memory circuit 16 is read once. At this time, an error correction code is added to the voice data, and the voice data is stored in an address different from the original storage address of the memory circuit 16. By such processing, data movement is performed inside the memory circuit 16. In other words, using the process to add the outer code,
Change the data storage address. Therefore, there is an advantage that no special circuit is required for changing the data storage address.

As shown in FIG. 4C, when the uncompressed audio data (AUDIO) and the uncompressed video data (INPUT VIDEO) input to the audio / video data recording device 1 are PAL system data. The pack circuit 180 is shown in FIG.
In parallel with the processing of the pack circuit 180 shown in FIG.
PACKING AREA) (point a in FIG. 3B). Further, the inner code encoder 192 parallelizes the processing of the pack circuit 180 shown in FIG. 4A, and the compressed video data (REDUCTION DATA) stored in the error correction block (VIDEO ECC, AUDIO ECC) of the sector 1 And voice data, and
An inner code for the system data (SYSTEM AUX) stored in the system data area (SYSTEM AUX AREA) is generated and added (time a in FIG. 3D).

Further, as shown in FIG. 4D, uncompressed audio data (AUD) input to the audio / video data recording apparatus 1 is input.
IO) and uncompressed video data (INPUT VIDEO) are NTSC
In the case of system data, the inner code encoder 192
Parallel to the processing of the pack circuit 180 shown in FIG. 4A, the error correction block (VIDEO ECC, AUDIOEC
C) Compressed video data (REDUCTION DATA) and audio data, and system data area (SYSTEM
AUX AREA) stored system data (SYSTEM AU
The inner code for X) is generated and added (time a in FIG. 3E). As described above, the audio data and the video data to which the error correction code is added by the ECC encoder 18 are converted into recording signals by the inner code encoder 192 and recorded on the VTR tape 2.

The reproducing head 22 reproduces four reproducing signals from the VTR tape 2 by each of the four reproducing heads.
The inner code decoder 32 converts the four reproduced signals input from the reproducing head 22 into a digital format, and further performs error correction using the inner code. The non-tracking control circuit 340 performs non-tracking control processing on each of the four audio data and compressed video data.

The outer code decoder 344 performs error correction processing using the outer code on the four audio data and video data which have been subjected to the non-tracking control processing, and determines which of the data errors is less likely to occur. select. The JOG memory control circuit 346 performs processing for the outer code decoder 344 to realize special reproduction such as normal reproduction or so-called jog shuttle reproduction and frame advance reproduction.

The depacking circuit 348 is used in the JOG memory 36.
Video data (REDUC
TION DATA) and audio data (AUDIO) are separated. The expansion decoding circuit 382 expands and decodes the separated compressed video data and outputs it as non-compressed video data (OUTPUT VIDEO). The delay memory 380 stores the separated audio data (AUD
Gives a delay to IO) and outputs it in time with uncompressed video data (OUTPUT VIDEO).

As described above, in the memory circuit 16, three sectors (in the PAL system shown in FIG. 4, in the PAL system shown in FIG. 4) are excluded, except for the sector which is the target of the error correction code by the inner code encoder 192 at that time. Sectors 0, 1,
3) can be used for delaying voice data. FIG.
In (A) to (E), as described above, three sectors are used for delay of audio data, and, for example, 0.5 frame after the pack circuit 180 starts storing in the memory circuit 16 of a new GOP. The case where the outer code encoder 184 starts to generate the outer code when the time of minutes has elapsed and the time required for the outer code generation is set to 0.25 frames per GOP is shown.

Under the conditions shown in FIGS. 3A to 3C,
As shown in FIGS. 3D and 4C, when the memory circuit 16 performs the processing on the PAL system data, as described above, the same GOP audio data and compressed video data are stored in the memory circuit 16. By storing the system data and the system data in the same sector, as shown in FIG. 3 (F), the video data (REDUCTION DATA) and the system data, which have a maximum delay of 5.25 frames with respect to the audio data, are generated. Range from (SYSTEM AUX) to video data (REDUCTION DATA) and system data (SYSTEM AUX) which precedes audio data by 0.5 frame, as shown in FIG. 3 (G). Then, the video data (REDUCTION D
It is possible to compensate for the time difference between the audio data and the system data (SYSTEM AUX).

As described above, in the audio / video data recording apparatus 1 according to the present invention, the order of storing audio data and compressed video data (REDUCTION DATA) in each sector of the memory circuit 16 is changed by an instruction from software. The compressed video data having a delay in the range of −0.5 to +5.25 frames with respect to the audio data can be matched with the timing of the audio data.

The compressed video data (R), which is delayed by 3.5 frames with respect to the uncompressed audio data (AUDIO).
EDUCTION DATA), as shown by the dotted line in FIG. 1, when the delay memory 124 is provided in the compression encoding unit 12 and the timing of these data is adjusted, the capacity of the delay memory 124 becomes PAL (625 / 50) system requires 430 Kbytes, and NTSC (525/60) system requires 320 Kbytes. On the other hand, the delay memory 124 is not necessary in the method for adjusting the timing by utilizing the empty area of the memory circuit 16 described above.

In addition to the embodiments described above, the multimedia network system 1 includes, for example, the reproducing unit 3.
0, the JOG memory 36 is used to match the timings of the audio data and the video data, and the delay memory 380 is used.
It is possible to adopt various configurations such as omitting.

[0050]

As described above, according to the audio / video data recording apparatus and method according to the present invention, the video data and the audio data are recorded without using the delay memory for compensating the compression processing time of the video data. It is possible to compensate for the difference in the delay time. Further, according to the audio / video data recording apparatus and the method thereof according to the present invention, even if the difference in delay time between audio data and video data becomes very large, the difference in delay time can be compensated. . Further, according to the audio / video data recording apparatus and the method thereof according to the present invention, the compression rate for audio data and video data can be changed without changing the hardware.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an audio / video data recording apparatus according to the present invention.

2A to 2C are diagrams showing recording areas of audio data and compressed video data (recording blocks) stored in the memory circuit shown in FIG. 1;

3A to 3G are diagrams showing an operation of the audio / video data recording device shown in FIG.

4 (A) to (D) show that at time point a in FIG.
It is a figure which shows the memory content of a memory circuit (FIG. 1).

[Explanation of symbols]

1 ... Audio / video data recording device, 2 ... VTR tape, 1
0 ... Recording unit, 12 ... Compression encoding unit, 120 ... Compression encoding circuit, 122 ... Memory circuit, 14, 16 ... Memory circuit,
18 ... ECC encoder, 180 ... Pack circuit, 184
... Outer code encoder, 188, 190 ... FIFO circuit,
192 ... Inner code encoder, 20 ... Recording head, 22 ...
Reproducing head, 30 ... reproducing unit, 32 ... inner code decoder, 3
4 ... Outer code decoder section, 340 ... Non-tracking control circuit, 342 ... Memory circuit, 344 ... Outer code decoder,
346 ... JOG memory control circuit, 348 ... Depack circuit, 36 ... JOG memory, 38 ... Decompression / decoding section, 380 ...
Delay memory, 382 ... decompression decoding circuit, 384 ... memory circuit

Claims (3)

[Claims] 1. A compression unit for compressing input video data to generate compressed video data having a delay time with respect to the input video data, input audio data corresponding to the input video data, and the generated compression. Storage means for storing video data; error correction code adding means for adding an error correction code by associating the stored input audio data with the compressed video data; and the input audio data with an error correction code added, An audio / video data recording apparatus having a recording unit for storing compressed video data in a recording block and recording the compressed video data on a recording medium. 2. The compression means GOPs input video data.
Compression encoding in units, the storage means stores a predetermined number of GOP compressed video data,
The audio / video data recording apparatus according to claim 1, wherein input video data corresponding to more GOPs than the predetermined number is stored at least by a delay time of the compressed video data. 3. Input video data is compressed, compressed video data having a delay time with respect to the input video data is generated, and the generated compressed video data is stored in a predetermined data amount. Corresponding input audio data is stored by at least the stored compressed video data and a data amount corresponding to the delay time of the compressed video data, and the stored compressed video data and the input audio data are associated with each other and an error correction code is stored. The audio / video data recording method in which the input audio data and the compressed video data to which the error correction code is added are housed in a recording block and recorded in a recording medium.