JPH09270681A - Signal change detection amplifier circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a decay difference of a wire where a delay difference between a near end and a remote end of the wire is large while minimizing the increase in wiring. SOLUTION: A remote end node N12 of a wire where a delay difference between a near end and a remote end of the wire is large is connected to two inverters 14, 15 whose threshold levels differ and an exclusive OR of the outputs is used for an output enable signal E of a clocked inverter 13 and the clocked inverter 13 drives the node N12 of the wire in an increasing direction of the change. A latch circuit 12 latches a level of the node N12 at a time when the enable signal E of the clocked inverter 13 is received and its inverted signal drives the node N12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a signal change detecting / amplifying circuit which is incorporated in a semiconductor device and detects a change in the potential of a signal line inside the semiconductor device to accelerate the change in the signal potential. .

[0002]

2. Description of the Related Art In recent years, as represented by a semiconductor memory, the scale of a semiconductor device has been remarkably increased, and with the increase in size of a chip, an internal signal wiring is lengthened and its load is increasing. Further, particularly in semiconductor memories, miniaturization has progressed with the progress of manufacturing process technology, and as a wiring material, a material having high resistance has come to be used as a wiring layer in terms of easiness of manufacturing.

For this reason, some internal wirings have increased resistance and capacitance, and the delay of signal transmission due to the internal wirings is an obstacle to stabilizing and speeding up the operation of the semiconductor device.

Such an increase in wiring delay is a serious problem especially in a circuit such as a semiconductor memory in which a large number of load circuits must be driven at high speed and at uniform timing by internally generated signals. Is becoming.

As a conventional technique for solving such a problem, for example, Japanese Patent Laid-Open No. 3-217918 discloses a clock signal generating circuit capable of reducing the timing delay of a clock signal due to wiring delay and the timing difference between nodes. For the purpose of providing, a plurality of load drive circuit blocks having a signal generated by the timing generation circuit block as a common input are provided, and the plurality of load drive circuit blocks are arranged at substantially equal intervals along the clock signal wiring. There has been proposed a clock signal generation circuit having a configuration in which outputs of a plurality of load drive circuit blocks are arranged in parallel and are connected in parallel on a clock signal wiring near the arrangement position of each load drive circuit block. The conventional load drive circuit described in Japanese Patent Laid-Open No. 3-217918 will be described below.

FIG. 8 is a diagram showing a circuit configuration of a load drive circuit and a load circuit described as a conventional technique in Japanese Patent Laid-Open No. 3-217918. In FIG. 8, 1 is a timing generation circuit, 2 is a load drive circuit block, 3 is a clock signal generation circuit, which is composed of the timing generation circuit 1 and the load drive circuit block 2, and 4 is a load circuit. The load circuit 4 is composed of a wiring resistance such as an aluminum wiring, a wiring capacitance, and various circuit elements (gate electrodes of MOSFET, etc.) connected on the wiring, but the resistance (resistance value R _L ) and the capacitor ( Only the capacitance value _CL ) is shown.

In the circuit shown in FIG. 8, the potential waveform of each node (node) when the reference clock input signal rising from 0V to the power supply voltage is applied to the input node N1 of the timing generation circuit block 1 is shown in FIG. It will be something like. The input end node N3 of the load circuit 4 is low (Lo
When the w level changes to the high level, this signal is transmitted to the end node N7 of the load through the load circuit 4.

If the output impedance of the inverter G4 of the load drive circuit block 2 is sufficiently small,
The signal delay time tdmax from the node 3 to the node N7 having the largest signal delay in the load circuit 4 is given by the following equation (1) as a first-order approximation.

Tdmax≈1 / 2 (4R _L × 5C _L ) (1)

FIG. 10 shows a clock signal generating circuit proposed in the above-mentioned Japanese Patent Laid-Open No. 3-217918. Referring to FIG. 10, in this clock signal generation circuit, the output of timing generation circuit 3 is also connected to wiring 5 that bypasses load circuit 4, and load drive block 2 is also connected to terminal node N7 side of load circuit 4. Is provided, the delay between the respective nodes in the load circuit 4 is reduced. In this configuration, the node N5 located at the center of the load circuit 4 has the worst delay. At this time, the delay of the node N5 with respect to the node N3 is about 1/2.
Is a _{(2R L × (5/2) C} L), 1/4 of the equation (1)
The value is doubled.

[0011]

By the way, the delay at the far end (signal delay) in the signal line becomes remarkable especially in the wiring for driving the sense amplifier row of the semiconductor memory as shown in FIG. It is an obstacle.

FIG. 11 is a diagram showing a circuit configuration of a cell array portion in a semiconductor memory. Also, FIG.
It is a figure showing the composition of the 1 sense amplifier. In FIG. 11, 6 is a memory cell array portion, and 7 is a sense amplifier row.

Referring to FIG. 11, in each sense amplifier, when the column selection signal YSWn (where n = 0 to N) and the write switch signal WSW are different, the write bus (WT, WT, WN).

When the column selection signal YSWn becomes high level, the read transfer gate 8 for inputting the high level bit line of the bit line pair BL, BLB to the gate in the sense amplifier shown in FIG. 12 is turned on,
A differential potential is generated on the read buses (RT, RN).

Referring again to FIG. 11, the read amplifier 9 which inputs the common read buses (RT, RN) of a plurality of sense amplifiers amplifies the difference potential of the read buses (RT, RN) at the time of reading and Output as data RDATA.

In the write buffer circuit 10, the write enable signal WE becomes high level and the write mask signal W
When MASK_B (Low active) is at the high level, one of the write buses (WT, WN) is dropped to the low level according to the value of the write data WDATA to write to the selected sense amplifier.

The semiconductor memory is provided with a plurality of circuits (write buffer circuit 10 and the like) shown in FIG. 11, and each circuit inputs the write mask signal WMASK_B separately to write / not write (write mask). Some have a function that can be controlled for each bit.

In this case, the write switch signal WSW is
Even in the write operation, it does not necessarily become the high level (that is, when the write mask signal WMASK_B is active), so that the data writing is controlled for each block.

By the way, the wiring such as the write switch signal WSW and the write bus (WT, WN) is made as thin as possible in view of the capacitance value and the chip area, and many sense amplifiers are connected on the wiring. , A non-negligible delay difference occurs between the near-end node N8 and the far-end node N12.

Recently, from the viewpoint of ease of manufacturing, wiring materials such as light buses (WT, WN) are becoming higher in resistance than before, and as a result, the delay difference at the near and far ends is increasing. It tends to expand.

FIG. 13 shows a timing waveform of the operation of the semiconductor memory shown in FIG. 11 at the time of writing. In the following, the above-mentioned delay difference at the near and far ends of the wiring will be described using the write switch signal WSW as an example.

The load of the write bus (WT, WN) is the diffusion layer capacitance, and the load is light and the delay difference is small as compared with the write switch signal WSW in which the gate capacitance is the load.

When the write enable signal WE, which is a signal for controlling the write operation, changes to high level (active), the write switch signal WSW becomes high level at the near end node N8. Then, the far-end node N12 becomes high level after the time td.

If the selected sense amplifier is connected to the near end node N8, the bit line BL / BL of FIG.
The sense amplifier is written with the signal waveform of B <8>. On the other hand, the selected sense amplifier is the far end node N.
If connected to 12, bit line BL / BLB <1
Writing is performed with the signal waveform of 2>. At that time, bit line BL / BLB <8> and bit line BL / BLB <12>
, A delay as shown in FIG. 13 appears.

As described above, the wiring delay seriously affects the characteristics of the semiconductor device, and therefore a solution is required.

However, in the structure proposed in the above-mentioned Japanese Patent Laid-Open No. 3-217918, one bypass wiring must be provided for one wiring, and therefore FIG.
In a product such as a semiconductor memory having a plurality of circuits (for example, 128 to 256 in the 16 Mb class), for example, the number of write switch lines and write bus lines is doubled, which is difficult to practically use in terms of chip area. is there.

In most of such products, the chip area is often determined by the number of wires.

Therefore, the present invention has been made in view of the above circumstances, and an object of the present invention is to suppress the increase in the number of wirings in a semiconductor device while minimizing the delay difference between the near end and the far end of the wirings. It is an object of the present invention to provide a signal change detection / amplification circuit that reduces a delay difference in a wiring having a large voltage.

[0029]

In order to achieve the above object, the present invention provides a means for monitoring the potential of a wire and detecting a change in the potential of the wire, and a means for changing the potential of the wire from one logic level to another logic level. And a means for driving the wiring at the other logic level in the direction of promoting the transition of the wiring when the semiconductor device is transited to.

The present invention is characterized by comprising means for holding the logic level of the wiring potential before the potential of the wiring changes.

In the present invention, the means for monitoring the potential of the wiring and detecting the change in the potential of the wiring connects the input terminal to a predetermined node of the wiring and has a plurality of inverters having different thresholds. It is characterized by including.

Further, according to the present invention, preferably, a plurality of inverters each having an input terminal connected to a wiring inside the semiconductor and having different threshold values, and a latch circuit for holding the state before the potential change of the wiring are provided. The present invention provides a signal change detecting / amplifying circuit, characterized in that the inverter senses a potential change of the wiring and drives the wiring in a direction opposite to a state held by the latch circuit.

[0033]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a circuit configuration of a semiconductor memory for explaining an embodiment of the present invention. A signal change detecting / amplifying circuit according to the embodiment of the present invention and this signal change detecting / amplifying circuit. 2 shows a configuration of a load circuit driven by the.

In FIG. 1, 6 is a memory cell array section,
Reference numeral 7 denotes a sense amplifier row, and each sense amplifier has a write bus (WT, WN) when a column selection signal YSWn (where n = 0 to N) and a write switch signal WSW are set to a high level. Connected with.
When the column selection signal YSWn goes high,
In the sense amplifier, a read transfer gate (not shown) for inputting a high-level bit line of the bit line pair BL, BLB to the gate is turned on, and a differential potential is generated in the read bus (RT, RN). . The read amplifier 9 that receives the common read buses (RT, RN) of a plurality of sense amplifiers as input receives the read buses (RT, R).
The differential potential of N) is amplified and output as read data RDATA.

In the write buffer 10, the write enable signal WE becomes high level and the write mask signal WMA
If SK_B (low active) is at the high level, the write bus (W
Writing to the selected sense amplifier is performed by dropping one of T and WN) to the low level.

Referring to FIG. 1, an embodiment of the present invention,
1 is different from the conventional semiconductor memory shown in FIG. 11 in that the farthest end node N12 of the write switch signal WSW in FIG. 1 is a signal for detecting a change in the node N12 and accelerating the transition operation thereof. That is, the change detection amplifier circuit 11 is provided.

That is, the signal change detection / amplification circuit 11 will be described with reference to FIG.
The signal potential of 12 is input, its output is connected to the node Q, the level of the node N12 is held at the high level of the signal E, and the level of the node N12 is transmitted to the node Q when the signal E is at the low level.

The clocked inverter 13 having the output of the latch circuit 12 as its input has its output in a high impedance state while the signal E input as an output enable signal to its control terminal is at a low level, and the signal E becomes While it is at the high level, a signal obtained by inverting the logic level of the output node Q of the latch circuit 12 is output.

Further, the outputs of the inverters 14 and 15 which have their input terminals commonly connected to the node N12 and have different threshold values (also called logic inversion voltage and logic threshold voltage) from each other are subjected to exclusive OR ( The exclusive OR gate 16 outputs a high level when the outputs of the inverters 14 and 15 are different from each other, and the output signal of the exclusive OR gate 16 is the latch circuit as the signal E described above. 12 latch control signals and clock enable inverter 13 output enable signals.

The signal change detection / amplification circuit 11 according to the embodiment of the present invention will be described in more detail with reference to an embodiment. FIG.
FIG. 4 is a diagram showing a configuration of inverters 14 and 15 according to an embodiment of the present invention.

Referring to FIG. 2, both inverters 14 and 15 are CMOS inverters, and the logical threshold value (logical inversion) of inverter 14 is set by inclining the current driving capability ratio of P-channel MOS transistor and N-channel MOS transistor. Voltage) is low and the logic threshold value of the inverter 15 is set high.

That is, the ratio (beta ratio) of β (gain coefficient) between the N-channel MOS transistor and the P-channel MOS transistor is β _R = β _N / β _P , and the logic inversion voltage in the input / output voltage characteristic of the CMOS inverter is It decreases as β _R increases. In addition, β _N of NMOS is (W
/ L) _N μC _ox (W: gate width, L: gate length, μ: carrier mobility, C _ox : gate capacitance per unit area). The same applies to PMOS.

Here, assuming that the current capacity per unit gate width of the P-channel MOS transistor is half that of the N-channel MOS transistor, the logical threshold value of the inverter 14 is expressed by the following equation (2) ) Is given. That is, as shown in FIG.
The gate width of each of the MOS and NMOS transistors is 5
μm and 10 μm, and the beta ratio β _R of the inverter 14 is β _R = β _N / β _P = 10 / (5/2) = 4,
The following expression (2) approximates the logical threshold value by VCC / (β _R +1).

[0045]

[Equation 1]

However, 1/5 · VCC> N channel MOS
The threshold value of the transistor (gate threshold voltage V _TN ) is used.

The logical threshold value of the inverter 15 is
The first approximation is given by the following equation (3). That is, the beta ratio β _R of the inverter 15 is β _R = β _N / β _P = 2.5
It is given by / (20/2) and becomes 1/4, and the logic threshold voltage is approximated by VCC / (β _R +1) to (4/5) VCC.

[0048]

[Equation 2]

However, -1 / 5.VCC <P channel MO
S-transistor threshold (gate threshold voltage V _TP )
And

FIG. 3 shows a timing waveform diagram for explaining the operation of the embodiment of the signal change detecting / amplifying circuit.

When the write enable signal WE shifts to the high level, the far end node N12 of the write switch signal WSW wiring is blunted and the voltage is changed from the GND (ground) level to the VC level.
The transition to the C (power) level begins.

When the potential of the node N12 exceeds the logical threshold value of 1 / 5.VCC, the output of the inverter 14 is inverted and the output node N1 of the inverter 14 is inverted.
3 falls to low level.

At this time, since the logic threshold value of the inverter 15 is at 4 / 5.VCC, the node N14 which is the output node of the inverter 15 maintains the high level. Therefore, the logic levels of the nodes N13 and N14 are different, and the output signal E of the exclusive OR gate 16 becomes high level.

At this time, the latch circuit 12 is connected to the node N12.
Holds the value of In the configuration of the input portion of the latch circuit 12, since the capacity ratios of the P-channel and N-channel MOS transistors are made equal, the node N12 is detected as low level, and the output node Q of the latch circuit 12 becomes the far end node. The logic level (low level) before the transition of N12 is maintained. Therefore, the output signal E of the exclusive OR gate 16
Becomes high level, the clocked inverter 13
Drives the node N12 to a high level which is the inverted output level (low level) of the latch circuit 12.
Then, the node N12 quickly transits to the high level. As a result, the delay difference between the near-end node N8 and the far-end node N12 can be reduced.

When the node N12 quickly transitions to the power supply potential VCC side (rises) and exceeds 4/5 · VCC, the output of the inverter 15 is inverted and the node N14 becomes high level, and the output signal of the exclusive OR gate 16 is output. Since E becomes low level, the output of the clocked inverter 13 becomes high impedance state. Further, with the transition of the signal E from the high level to the low level, the data of the node N12 (high level) is transmitted to the output node Q of the latch circuit 12.

As shown in FIG. 3, the write switch signal W
Even when SW changes from high level to low level,
The operation is similar except that the operations of the nodes N13 and N14 are reversed.

In this way, in the embodiment of the present invention, it is possible to suppress an increase in wiring and to reduce the delay of the near-far end difference of many signals.

Next, a second embodiment of the present invention will be described.

FIG. 4 shows the configuration of a semiconductor memory for explaining the second embodiment of the present invention. The signal change detection / amplification circuit and the signal change detection / amplification circuit according to the second embodiment of the present invention are shown in FIG. It shows a circuit configuration of a load circuit to be driven.
4, the same elements as those of FIG. 1 referred to for the description of the first embodiment are designated by the same reference numerals, and the description of the same elements will be appropriately omitted to avoid duplication. .

Referring to FIG. 4, also in this embodiment, as in the first embodiment shown in FIG. 1, the signal change detecting / amplifying circuit 11 is provided at the farthest end node N12 of the write switch signal WSW. Are connected.

This embodiment differs from the first embodiment in that the latch circuit 12 shown in FIG. When D is high level, the level of the far end node N12 is held, and the signal WE D is low level to convey the level of the far end node N12 to the node Q, and the signal WE That is, the signal E, which is input to the control terminal of the clocked inverter 13 and acts as an output enable signal, becomes active only while D is at a high level. That is, the signal WE_D is input to the latch control terminal of the latch circuit 12, and the output signal of the exclusive OR gate 16 is input to the control terminal of the clocked inverter 13 by the AND gate having the signal WE_D as a gate signal input. Have been entered through.

The logic thresholds of the inverters 14 and 15 are set to (1/5) VCC and (4/5) VCC, respectively, as described in the first embodiment. And

FIG. 5 shows timing waveforms for explaining the operation of this embodiment of the signal change detecting / amplifying circuit.

When the write enable signal WE goes high, the far-end node N12 begins to transition from the GND level to the VCC level while rounding.

When the potential of the node N12 exceeds 1 / 5VCC, the output of the inverter 14 is inverted and the output node N13 of the inverter falls to the low level.

The threshold value of the inverter 15 is 4/5 · VC
Since it is C, the node N14 maintains the high level. Since the logic levels of the nodes N13 and N14 are different, the node N16 which is the output of the exclusive OR gate 16 becomes high level.

Signal WE D is a write enable signal W
Since the signal becomes a high level when E changes, the node Q that is the output of the latch circuit 12 holds the logic level (low level) before the transition of the node N12, and the output of the clocked inverter 13 The enable signal E becomes high level.

Therefore, the clocked inverter 13 is
The node N12 is driven to a high level, which is the inverted logic level of the node Q, and the node N12 quickly transits to a high level, so that the delay difference between the nearest end node N8 and the farthest end node N12 can be reduced. .

When the node N12 rapidly transitions to the power supply potential VCC side (rises) and exceeds 4/5 · VCC, the output of the inverter 15 is inverted, the output node N14 becomes low level, and the exclusive OR gate 16 is provided. Output becomes low level. Therefore, the output enable signal E becomes low level, and the output of the clocked inverter 13 becomes high impedance state. Also, the signal WE When D goes low, the data of the far end node N12 (high level) is transmitted to the node Q.

Even when the write switch signal WSW changes from the high level to the low level, the nodes N13 and N1
The operation is the same as when changing from the low level to the high level, except that the operation of 4 is reversed.

Here, the signal WE The generation circuit of D can be realized by a circuit configuration shown in FIG. 6, for example.

Referring to FIG. 6, Φw is a reference signal for write operation, 17 is a delay element, and 18 is an exclusive OR gate. FIG. 7 shows a timing waveform chart for explaining the operation of the circuit shown in FIG. The reference signal Φw is a signal (node N1) obtained by delaying the reference signal Φw by the delay element 17 for a predetermined time.
5) together with the exclusive OR gate 18.

Referring to FIGS. 6 and 7, when the reference signal Φw for the write operation changes, the write enable signal WE also changes after an arbitrary delay time (eg, determined by the number of inverter stages). When the reference signal Φw changes, the logical levels of the reference signal Φw and the delayed signal input to the exclusive OR gate 18 differ by the delay time determined by the delay element 17, so that the exclusive OR gate 18 outputs Signal WE which is an output signal D becomes high level.

The advantage of this embodiment is that even if the inverters 13 and 14 malfunction due to noise at the time when the write switch signal WSW does not change and the node N16 becomes high level, the clocked inverter 13 remains. That is, it is configured not to work.

In this way, only one additional wire runs over a long distance, and it is possible to stably reduce the near-end difference of many signals against noise.

[0076]

As described above, according to the present invention, miniaturization,
In an internal signal in which the wiring delay of a highly integrated semiconductor device is not negligible, a plurality of inverter circuits with different thresholds connected to the far end thereof and a latch circuit for holding the value before the potential change of this wiring are provided, By detecting the potential change of the wiring by two inverter circuits and driving the wiring in the direction opposite to the value held by the latch circuit, the far end of the signal is driven quickly and the delay of the difference between the near and far ends is reduced. You can

Further, according to the present invention, the wiring that runs a long distance can be a minimum of 0 (no additional wiring) regardless of the number of driven signals, and the speed of the semiconductor device can be increased while minimizing the chip area. Can be achieved.

[Brief description of drawings]

FIG. 1 is a diagram for explaining a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of the inverter in the embodiment of the present invention.

FIG. 3 is a diagram schematically showing operation waveforms according to an embodiment of the present invention.

FIG. 4 is a diagram for explaining a second embodiment of the present invention.

FIG. 5 is a diagram for explaining a second embodiment of the present invention.

FIG. 6 is a diagram showing an example of an enable signal generation circuit according to a second embodiment of the present invention.

FIG. 7 is a timing chart for explaining the operation of the circuit of the enable signal generation circuit of FIG.

FIG. 8 is a diagram showing a conventional circuit cited from Japanese Patent Laid-Open No. 3-217918.

9 is an operation timing chart of the circuit of FIG.

FIG. 10 is a diagram showing a circuit proposed in Japanese Patent Laid-Open No. 3-217918.

FIG. 11 is a diagram showing an example of a circuit configuration of a conventional semiconductor memory.

12 is a diagram showing an example of a sense amplifier of the semiconductor memory of FIG.

FIG. 13 is a timing diagram for explaining the operation of the conventional semiconductor memory.

[Explanation of reference numerals] 6 memory cell array section 7 sense amplifier section 8 read transfer gate 9 read amplifier 10 write buffer 11 signal change detection amplification circuit 12 latch circuit 13 clocked inverters 14 and 15 inverter 16 exclusive OR gate 17 delay element 18 Exclusive OR gates BL, BLB, BL <8>, BLB <8>, BL <1
2>, BLB <12> bit line SAP, SAN sense amplifier activation signal YSWn column selection signal RT, RN read bus WT, WN write bus N8 to N15 circuit node Q, E circuit node WMASK B write mask signal WDATA write data bus WE write enable signal Φw write reference signal WE D signal change detection amplifier enable signal

Claims (5)

[Claims] 1. A plurality of inverters each having an input terminal connected to a wiring inside a semiconductor and having different threshold values, and a latch circuit for holding a state before a potential change of the wiring.
A signal change detection / amplification circuit comprising: a plurality of inverters for detecting a potential change of the wiring, and driving the wiring in a direction opposite to a state held by the latch circuit. 2. A means for monitoring the potential of a wiring to detect a change in the potential of the wiring, and urging the transition of the wiring when the potential of the wiring changes from one logic level to another logic level. And a means for driving the wiring at the other logic level in a direction. 3. The semiconductor device according to claim 2, further comprising means for holding a logic level of the wiring before the potential of the wiring changes. 4. A means for holding the logic level of the wiring before the potential of the wiring changes, a means for monitoring the potential of the wiring and detecting a change in the wiring potential (referred to as "potential change detecting means"). Based on the output, latches the logic level before the change of the potential of the wiring, and at the time of the transition of the logic level of the wiring potential, under the control of the output of the potential change detection means, 4. The semiconductor device according to claim 3, wherein the wiring is driven by a logic level which is the logic level obtained by inverting the logic level before the potential change. 5. A means for monitoring the potential of the wiring and detecting a change in the potential of the wiring includes a plurality of inverters each having an input terminal connected to a predetermined node of the wiring and having different threshold values. The semiconductor device according to claim 2.