JPH09270503A - Solid state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid state image pickup device which can sufficiently suppress smear generation. SOLUTION: A frame interline solid state image pickup device has a vertical over flow drain structure forming a p-well which is provided with photosensitive pixels P(1,1)∼P(n,m), perpendicular CCDs 110-1∼110-m for transfer, perpendicular CCDs 120-1∼120-m for storage and a horizontal CCD 130 in an n-type semiconductor substrate and such a voltage as all signal electric charge which is generated by the photosensitive pixels P(1,1)∼P(n,m) during the time when the perpendicular CCDs 110-1∼110-m for transfer are transfer being exhausted into the n-type semiconductor substrate is continuously applied to the n-type semiconductor substrate. During the time when the perpendicular CCDs 110-1∼110-m for transfer are not transfer, such a voltage as a signal electric charge volume only which exceeds a saturated electric charge volume of what is generated by the photosensitive pixels P(1,1)∼P(n,m) being exhausted into the n-type semiconductor substrate is continuously applied to the n-type semiconductor substrate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame inter-line type solid-state image pickup device and an inter-line type solid-state image pickup device.

[0002]

2. Description of the Related Art The structure of a conventional solid-state image pickup device will be described by taking an inter-line type solid-state image pickup device having a vertical overflow drain structure as an example.

FIG. 4 is a plan view conceptually showing the structure of such a solid-state image pickup device, and is for explaining the "inter-line type".

As shown in FIG.
Photosensitive pixels P (1,1) that generate signal charges according to the amount of received light
P (n, m) are arranged in a matrix. In addition, in the photosensitive section 410, these photosensitive pixels P (1,1) to P
For each (n, m) column, a vertical CCD (Charge Coupled Devic
e) 410-1 to 410-m are formed. These vertical CCDs 410-1 to 410-m are provided for each photosensitive pixel P.
Signal charges are simultaneously taken in from (1,1) to P (n, m) and transferred in the column direction. For example, the vertical CCD 410-1 is used to capture and transfer the signal charges of the photosensitive pixels P (1,1) to P (n, 1) in the same column.

The horizontal CCD 420 is a vertical CCD 410.
Signal charges of 1 bit each from −1 to 410-m are simultaneously taken in, transferred in the row direction, and output to the outside via the buffer 430.

The sweep drain 440 is used for transferring and sweeping out the charges remaining in the vertical CCDs 410-1 to 410-m before reading the signal charges.

FIG. 5 is a partial cross-sectional view for explaining a "vertical overflow drain structure" of a conventional solid-state image pickup device.

As shown in the figure, an n-type semiconductor substrate 51 is provided.
At 0, a p well 511 is formed. The p-well 511 has a photosensitive pixel P (i, j) and a vertical CC.
D410-j is formed. Although not shown, all the photosensitive pixels P (1,1) to P (n, m), all the vertical CCDs 410-1 to 410-m, and the horizontal CCD 420.
And the drain 440 is formed in the same P well 511.

The photosensitive pixel P (i, j) has p ⁺ regions 521 and n.
It is composed of a photodiode including a mold region 522. The vertical CCD 410-j also includes an n-type region 531 and a control electrode 532.

The power supply 540 is provided on the n-type semiconductor substrate 510.
A bias voltage φES is applied. In addition, the power source 550 is
A control voltage φV is applied to the control electrode 532.

FIG. 6 is a timing chart for explaining the operation of the solid-state image pickup device shown in FIGS. 4 and 5. Further, FIG. 7 is also a diagram for explaining the operation of the solid-state imaging device, and shows the energy levels on the AA ′ plane of FIG.

As shown in FIG. 1, the n-type semiconductor substrate 510 is provided before the solid-state imaging device starts reading the signal charges.
Is applied with a DC voltage V _OFD as a bias voltage φES. At this time, the potential distribution of the solid-state imaging device is in the state shown by the curve A in FIG. As a result, the signal charges Q generated in the photosensitive pixels P (1,1) to P (n, m) are directly stored in the n-type region 522 in the photosensitive pixels (see FIG. 5).

The description of the sweeping operation will be omitted.

Next, each vertical CCD 410-1 to 410-
A positive pulse φV ⁺ is applied as the control voltage φV to the m control electrode 532. As a result, each photosensitive pixel P (1,1)
~ The signal charge generated in P (n, m) is applied to each vertical CCD 410.
-1 to 410-m.

Subsequently, each of the vertical CCDs 410-1 to 410
A negative pulse φV ₁ ⁻ is applied as a control voltage φV to the −m control electrode 532 at a constant interval T ₁ . As a result, the signal charges generated in the photosensitive pixels P (1,1) to P (n, m) are transferred to the horizontal C in each vertical CCD 410-1 to 410-m.
It is transferred to the CD 420 side. Then, the signal charge is also transferred by the horizontal CCD 420 at this timing (not shown).

The pulse voltage V _ES is superimposed on the bias voltage φ _ES of the n-type semiconductor substrate 510 at the same timing as the application of the pulse φ V ₁ ⁻ to the control electrode 532. That is, the bias voltage of the n-type semiconductor substrate 510 at this time is φES = V _OFD +
It becomes V _ES . At this time, the potential distribution of the solid-state imaging device is in the state shown by the curve B in FIG. As a result, excess charges generated in the p well 511 are discharged to the n-type semiconductor substrate 510, and smear generation is reduced.

Here, when the potential distribution becomes like the curve B, the signal charge Q generated in the photosensitive pixels P (1,1) to P (n, m) is as shown by the arrow C in FIG. , As it is n
The semiconductor substrate 510 is discharged. Therefore, the vertical CC
The amount of signal charge captured in D410-1~410-m during from time t ₁ to the pulse voltage V _ES was last superimposed application in the previous transfer operation to a positive timing t ₂ of the pulse .phi.V ⁺ is applied It becomes an electric charge generated at (elapsed time T ₂ ). Therefore, the exposure time is determined by appropriately selecting the timing t _{1 at} which the pulse voltage V _ES is finally superimposed and applied. This function is generally called an electronic shutter function.

[0018] Incidentally, the superposition of the pulse voltage V _ES control pulse .phi.V ₁ ^- carried out at the same timing, the control pulse .phi.V ₁ ^- equivalent application timing of the horizontal blanking interval of the image display device (not shown) Because it does. When the pulse voltage V _ES is applied to the n-type semiconductor substrate 510 at a timing other than the blanking period, noise is generated, which causes deterioration of image quality. However, during the blanking period, the supply of signal charges to the image display is interrupted. Therefore, even if noise is generated, the image quality is not likely to deteriorate.

[0019]

However, in such a conventional solid-state image pickup device, the occurrence of smear could not be sufficiently reduced for the following reasons.

As described above, in the conventional solid-state imaging device, the pulse voltage V _ES and the negative control pulse φV ₁ ⁻ are supplied at the same timing, but in this case, some smear components are n-type semiconductors. Vertical CC without being discharged to the substrate 510
It is transferred by D410-1 to 410-m. Therefore, when the light intensity is weak and the amount of smear component generated is small, it is possible to suppress the occurrence of smear to a negligible amount, but when the light intensity is very strong and the amount of smear component generated is extremely large, It was not possible to completely prevent the occurrence of smear.

Further, in the conventional solid-state image pickup device, the time T required for the photosensitive pixels P (1,1) to P (n, m) to accumulate the signal charges.
_The pulse voltage V _ES cannot be applied during the period of time ₂ , and therefore, the smear cannot be prevented during the time period T ₂ . Therefore, it is desirable to shorten the exposure time T ₂ in order to reduce the probability that smear occurs, but this reduces the signal charge. That is, it was difficult to prevent the occurrence of smear while making the exposure time T ₂ sufficiently long.

The present invention has been made in view of the above drawbacks of the prior art, and an object of the present invention is to provide a solid-state image pickup device capable of sufficiently suppressing the occurrence of smear.

[0023]

[Means for Solving the Problems]

(1) A solid-state image pickup device according to a first aspect of the present invention includes a photosensitive pixel arranged in a matrix, and a first transfer shift register that takes in signal charges from these photosensitive pixels for each column and transfers them in the column direction. And a storage shift register for temporarily storing the signal charges transferred by these first transfer shift registers, and signal charges of the same row are simultaneously taken in from these storage shift registers and transferred in the row direction. Second
A frame-inter-line solid-state image pickup device having a vertical overflow drain structure, the first conductivity type well having a transfer shift register for transfer of the first type is formed in a second conductivity type semiconductor substrate. During the transfer time of the first transfer shift register, a voltage is continuously applied to the semiconductor substrate so that all the signal charges generated in the photosensitive pixel during this time are discharged to the semiconductor substrate, and During the non-transfer time of the first transfer shift register, a voltage is continuously applied so that only a portion of the signal charges generated in the photosensitive pixels during this time that exceeds the saturated charge amount is discharged to the semiconductor substrate. It is characterized by further comprising substrate voltage applying means for applying to the semiconductor substrate. (2) A solid-state imaging device according to a second aspect of the present invention is a solid-state imaging device, wherein the photosensitive pixels arranged in a matrix form, and a first transfer shift register for taking in signal charges from these photosensitive pixels for each column and transferring the signal charges in the column direction. And a second transfer shift register for simultaneously taking in the signal charges transferred by these first transfer shift registers for each same row and transferring them in the row direction. In an inter-line type solid-state image pickup device having a vertical overflow / drain structure formed in a vertical semiconductor substrate, during a predetermined time from the start of transfer of the first transfer shift register, A voltage is continuously applied to the semiconductor substrate so that all the signal charges generated in the photosensitive pixels are discharged to the semiconductor substrate, and the first transfer shift is performed after the predetermined time has elapsed. During the time until the next transfer start by the transistor, a voltage is continuously applied to the semiconductor substrate so that only the amount of the signal charge generated in the photosensitive pixel exceeding the saturated charge amount is discharged to the semiconductor substrate during this time. It is characterized by further comprising a substrate voltage applying means for applying to the substrate.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the First Invention An embodiment of the first invention will be described below with reference to the drawings.

In this embodiment, as the solid-state image pickup device, a frame inter-line type solid-state image pickup device having a vertical overflow drain structure is used.

FIG. 1 is a plan view conceptually showing the structure of such a solid-state image pickup device for explaining the "frame inter line type".

In such a solid-state image pickup device, the photosensitive section 11
The configuration of 0 is the same as in the case of the inter-line type solid-state image pickup device (see FIG. 4), and the photosensitive pixels P (1,1) to P (n, m) and the photosensitive pixels P (1,1) to P (n, m) are arranged in a matrix. P (1,1) ~ P
Transfer vertical CCDs provided adjacent to each (n, m) column
110-1 to 110-m.

The accumulating section 120 is a vertical CCD 11 for each transfer.
It is provided with m vertical CCDs 120-1 to 120-m for accumulation, which are provided corresponding to 0-1 to 110-m. These storage vertical CCDs 120-1 to 120-m take in the signal charges transferred from the transfer vertical CCDs 110-1 to 110-m as they are and temporarily store them.

The horizontal CCD 130 is a vertical CCD for each storage.
Signal charges of 1 bit each are simultaneously taken from 120-1 to 120-m, transferred in the row direction, and output to the outside via the buffer 140.

The sweep drain 150 is the same as in the case of the inter-line type solid-state image pickup device (see FIG. 4), and before the signal charge is read out, the transfer vertical CCD 110-1.
It is used to transfer and sweep away the residual charge at ~ 110-m.

Further, the solid-state image pickup device according to the present embodiment is
It has a vertical overflow drain structure. This structure is the same as in the case of the conventional solid-state imaging device (see FIG. 5), and thus the description thereof will be omitted.

Next, the operation of the solid-state image pickup device according to this embodiment will be described. FIG. 2 is a timing chart showing the operation of the solid-state imaging device.

As shown in the figure, before the solid-state image pickup device starts reading the signal charge, the n-type semiconductor substrate 510 is formed.
The point that the DC voltage V _OFD is applied as the bias voltage φES is similar to the conventional case (see FIG. 6). As a result, the potential distribution of the solid-state imaging device is shown by the curve A in FIG.
As shown in, the photosensitive pixels P (1,1) to
The signal charge Q generated by P (n, m) is directly stored in the n-type region 522 (see FIG. 5) in the photosensitive pixel. At this time, when the amount of charge accumulated in the n-type region 522 exceeds the saturated charge amount, the excess charge is discharged to the n-type semiconductor substrate 510, as indicated by an arrow D in FIG. By thus discharging the excess charges, blooming can be reduced.

Next, each transfer vertical CCD 110-1 to 110-1
A positive pulse φV ′ is applied as a control voltage φV to the 10-m control electrode 532. As a result, the sweep operation can be performed.

The transfer vertical CCDs 110-1 to 110-1
A control voltage φV is applied to the control electrode 532 of 110-m,
A positive pulse φV ⁺ is applied. As a result, the signal charge generated in each of the photosensitive pixels P (1,1) to P (n, m) is taken into each of the transfer vertical CCDs 110-1 to 110-m.

Subsequently, the pulse voltage V _ES is superimposed on the bias voltage φES of the n-type semiconductor substrate 210. That is, n
The bias voltage of the semiconductor substrate 210 is φES = V _OFD
+ V _ES As a result, the potential distribution of the solid-state imaging device becomes as shown by the curve B in FIG. 7, so that the charges generated in the p well 211 are discharged to the n-type semiconductor substrate 210, and the generation of smear is reduced. Can be planned.

Next, each transfer vertical CCD 110-1 to 11
A negative pulse φV ₁ ⁻ is applied as a control voltage φV to the 0-m control electrode 532 at a constant interval T ₃ . As a result, the signal charges generated in the photosensitive pixels P (1,1) to P (n, m) are transferred to the transfer vertical CCDs 110-1 to 110-m.
The data is transferred to the storage vertical CCDs 120-1 to 120-m. Since the solid-state imaging device according to this embodiment is a frame inter-line type, the transfer vertical CCD 110-
It is not necessary to perform the transfer operation of 1-110-m in synchronization with the transfer timing of the horizontal CCD 130. Therefore, the transfer from the transfer vertical CCDs 110-1 to 110-m to the storage vertical CCDs 120-1 to 120-m is performed by
Compared with the case of the line type solid-state image pickup device, the transfer can be performed at a very high transfer rate.

The transfer vertical CCDs 110-1 to 110-1
Vertical CCDs for storage 120-1 to 120-m from 10-m
When the transfer of charges to the n-type semiconductor substrate 210 is completed, the bias voltage of the n-type semiconductor substrate 210 is returned to φES = V _OFD . As a result, the potential distribution returns to the state of the curve A in FIG. 7, so that the signal charges generated in the photosensitive pixels P (1,1) to P (n, m) after that are accumulated as they are.

In this embodiment, the n-type semiconductor substrate 2
Since the signal charge is not sent to the image display device when the bias voltage of 10 is returned to φES = V _{OF D} , the generation of noise due to the fall of the bias voltage φES does not deteriorate the image quality. Therefore, the bias voltage φES can be lowered at any timing.

Then, the vertical CCDs for storage 120-1 to 120-1
A negative pulse φv ₁ ⁻ is applied as a control voltage φv to a 120-m control electrode (not shown) at a constant interval T ₄ . As a result, the signal charges generated in the photosensitive pixels P (1,1) to P (n, m) are transferred to the storage vertical CCDs 120-1 to 120.
-M is transferred to the horizontal CCD 130 side. And
The signal charge is also transferred by the horizontal CCD 130 at this timing (not shown). It should be noted that smear does not occur when the signal charges in the storage vertical CCDs 120-1 to 120-m are being transferred. Therefore, the bias voltage of the n-type semiconductor substrate 210 is fixed at φES = V _OFD .

As described above, in the solid-state image pickup device according to the present embodiment, the transfer vertical CCDs 110-1 to 110-.
Since the bias voltage of the n-type semiconductor substrate 210 is fixed to φ _ES = V _OFD + V _ES while the signal charge is being transferred by m, the smear component is a vertical CCD for transfer.
It is not transferred in 110-1 to 110-m. Therefore, even when the amount of smear component generated is extremely large, the generation of smear can be completely prevented.

In the solid-state image pickup device of this embodiment, smear is not likely to occur when the signal charges in the storage vertical CCDs 120-1 to 120-m are being transferred. Vertical CCD 110-1 to 1
The signal charge amount taken into 10-m is the charge amount accumulated during the elapsed time T ₅ from the timing t ₃ when φES = V _OFD is returned to the timing t ₄ when the positive pulse φV ⁺ is applied. Therefore, the accumulation time can be made longer than in the case of the conventional solid-state imaging device (elapsed time T _{2 in} FIG. 6).

That is, according to the solid-state imaging device of the present embodiment, it is possible to completely prevent the occurrence of smear while making the exposure time sufficiently long.

Embodiment of Second Invention Hereinafter, one embodiment of the second invention will be described with reference to the drawings.

In this embodiment, an inter-line type solid-state image pickup device having a vertical type overflow drain structure is used as the solid-state image pickup device. The vertical overflow drain structure and the inter line are the same as those in the case of the conventional solid-state imaging device (see FIGS. 4 and 5), and thus the description thereof is omitted.

Next, the operation of the solid-state image pickup device according to this embodiment will be described. FIG. 3 is a timing chart showing the operation of the solid-state imaging device.

As shown in the figure, also in the solid-state imaging device according to the present embodiment, the bias voltage φES of the n-type semiconductor substrate 510 (see FIG. 5) is read before the solid-state imaging device starts reading the signal charge. As a result, a DC voltage V _OFD is applied. As a result, the potential distribution of the solid-state image pickup device becomes as shown by the curve A in FIG. 7, so that the signal charge Q generated at each of the photosensitive pixels P (1,1) to P (n, m) remains unchanged. It is accumulated in the n-type region 522 (see FIG. 5) in the photosensitive pixel. Note that the point that blooming can be reduced by discharging excess charges is the same as in the case of the first invention.

Next, each vertical CCD 410-1 to 410-
A positive pulse φV ′ is applied as the control voltage φV to the m control electrode 532 (see FIG. 5). As a result, the sweep operation can be performed.

Then, each vertical CCD 410-1 to 410
A positive pulse φV ⁺ is applied as a control voltage φV to the −m control electrode 532. As a result, each photosensitive pixel P (1,
1) ~ The signal charge generated at P (n, m) is transferred vertically CC
It is taken into D410-1 to 410-m.

Next, the bias voltage φ of the n-type semiconductor substrate
By superimposing the pulse voltage V _ES on _ES , φES = V _OFD + V
_ES . As a result, as in the case of the first invention, it is possible to reduce the occurrence of smear. Since no signal charge is sent to the image display device at this point in time, the occurrence of noise due to the rise of the bias voltage φES does not deteriorate the image quality. Therefore, the bias voltage φES
Can be started at any timing.

Next, each vertical CCD 110-1 to 110-
A negative pulse φV ₁ ⁻ is applied as a control voltage φV to the m control electrode 532 at a constant interval T ₆ . As a result, the signal charges generated in the photosensitive pixels P (1,1) to P (n, m) are transferred to the horizontal C in each vertical CCD 410-1 to 410-m.
It is transferred to the CD 420 side. Then, the signal charge is also transferred by the horizontal CCD 420 at this timing (not shown).

Here, the bias voltage of the n-type semiconductor substrate 210 is φES = V _OFD at a predetermined timing during the transfer of signal charges by the vertical CCDs 110-1 to 110-m.
Is returned to. As a result, the potential distribution returns to the state of the curve A in FIG. 7, so that the photosensitive pixels P (1,1) to
The signal charge generated at P (n, m) is stored as it is. The exposure time −T ₇ is determined by appropriately selecting the timing t ₅ for returning to φES = V _OFD .

In the present embodiment, the n-type semiconductor substrate 2
Since the signal charge is sent to the image display device when the bias voltage of 10 is returned to φES = V _{OF D} , in order to prevent the generation of noise and ensure high image quality, the bias voltage φES
It is desirable to match the falling timing of (1) with the horizontal blanking period of the image display (not shown).

As described above, in the solid-state image pickup device according to this embodiment, the transfer vertical CCDs 110-1 to 110-.
The bias voltage of the n-type semiconductor substrate 210 is changed to φES = V _{OFD for} a predetermined period while the signal charge is transferred by m.
Since it is fixed to + V _ES , the smear component is not transferred by the transfer vertical CCDs 110-1 to 110-m during this period. Therefore, even if the amount of smear component generated is extremely large, the occurrence of smear can be prevented.

[0055]

As described in detail above, according to the present invention, it is possible to provide a solid-state image pickup device capable of sufficiently suppressing the occurrence of smear.

[Brief description of drawings]

FIG. 1 is a plan view conceptually showing the structure of a solid-state imaging device according to an embodiment of the first invention.

FIG. 2 is a timing chart showing the operation of the solid-state imaging device shown in FIG.

FIG. 3 is a timing chart showing an operation of the solid-state imaging device according to the embodiment of the second invention.

FIG. 4 is a plan view conceptually showing one configuration example of a conventional solid-state imaging device.

FIG. 5 is a partial cross-sectional view conceptually showing one configuration example of a conventional solid-state imaging device.

FIG. 6 is a timing chart for explaining the operation of the solid-state imaging device shown in FIGS. 4 and 5.

FIG. 7 is a diagram showing energy levels on the AA ′ plane of FIG. 5.

[Explanation of symbols]

 110 Photosensitive part 120 Storage part 130 Horizontal CCD 140 Buffer 150 Sweep drain P (1,1) to P (n, m) Photosensitive pixel 110-1 to 110-m Transfer vertical CCD 120-1 to 120-m for storage Vertical CCD

Claims (2)

[Claims] 1. A photosensitive pixel arranged in a matrix, a first transfer shift register for taking in a signal charge from each of these photosensitive pixels for each column and transferring the same in a column direction, and a first transfer register for these. An accumulation shift register that temporarily accumulates the signal charges transferred by the shift register, and a second transfer shift register that simultaneously takes in the signal charges of the same row from these accumulation shift registers and transfers them in the row direction. A frame inter-line solid-state imaging device having a vertical overflow drain structure, in which a first conductivity type well provided therein is formed in a second conductivity type semiconductor substrate, wherein the first transfer shift register comprises: During the transfer time, a voltage is continuously applied to the semiconductor substrate such that all the signal charges generated in the photosensitive pixel during this time are discharged to the semiconductor substrate, and On the other hand, during the non-transfer time of the first transfer shift register, the voltage such that only the amount of the signal charges generated in the photosensitive pixels during the time exceeds the saturated charge amount is discharged to the semiconductor substrate. The solid-state imaging device further comprising a substrate voltage applying unit that continuously applies the voltage to the semiconductor substrate. 2. Photosensitive pixels arranged in a matrix, a first transfer shift register for taking in signal charges from these photosensitive pixels for each column and transferring them in the column direction, and these first transfer shift registers. The second well of the first conductivity type is provided with a second transfer shift register that simultaneously takes in the signal charges transferred by the shift register for each same row and transfers them in the row direction.
In an inter-line type solid-state imaging device having a vertical overflow drain structure formed in a conductive semiconductor substrate, a predetermined time from the start of transfer of the first transfer shift register A voltage is continuously applied to the semiconductor substrate so that all the signal charges generated in the photosensitive pixel are discharged to the semiconductor substrate, and after the elapse of the predetermined time, the next transfer by the first shift register for transfer is performed. During the time until the transfer is started, a voltage is continuously applied to the semiconductor substrate so that only the amount of the signal charge generated in the photosensitive pixel that exceeds the saturated charge amount is discharged to the semiconductor substrate during this time. A solid-state image pickup device further comprising: substrate voltage applying means for controlling.