JPH09270429A - Ball-array substrate and array head - Google Patents

Ball-array substrate and array head

Info

Publication number
JPH09270429A
JPH09270429A JP3127497A JP3127497A JPH09270429A JP H09270429 A JPH09270429 A JP H09270429A JP 3127497 A JP3127497 A JP 3127497A JP 3127497 A JP3127497 A JP 3127497A JP H09270429 A JPH09270429 A JP H09270429A
Authority
JP
Japan
Prior art keywords
array
array substrate
substrate
ball
diameter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3127497A
Other languages
Japanese (ja)
Other versions
JP3819984B2 (en
Inventor
Hideji Hashino
英児 橋野
Kenji Shimokawa
健二 下川
Kohei Tatsumi
宏平 巽
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Steel Corp
Original Assignee
Nippon Steel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP03127497A priority Critical patent/JP3819984B2/en
Application filed by Nippon Steel Corp filed Critical Nippon Steel Corp
Priority to PCT/JP1997/003011 priority patent/WO1998034273A1/en
Priority to EP97937832A priority patent/EP0964442B1/en
Priority to US09/355,517 priority patent/US6571007B1/en
Priority to EP10174137A priority patent/EP2256793B1/en
Priority to DE69740081T priority patent/DE69740081D1/en
Priority to TW086112433A priority patent/TW365682B/en
Priority to MYPI97004781A priority patent/MY119459A/en
Publication of JPH09270429A publication Critical patent/JPH09270429A/en
Application granted granted Critical
Publication of JP3819984B2 publication Critical patent/JP3819984B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To provide a ball-array substrate and array head which form ball bumps more reliably than conventional bump formation by improving positional precision in bump formation. SOLUTION: An array substrate l, for arraying micro conductive balls 3 at positions corresponding to electrodes 4 on a semiconductor device or a substrate, comprises a glass substrate having array holes 2 having a diameter smaller than that of the micro conductive balls 3 (preferably, 1/3 ⊖ (diameter of array hole/diameter of micro conductive ball) ⊖ 4/5). Preferably, the array substrate 1 is a photosensitive glass substrate having a thickness of 0.3mm ⊖thickness of array substrate <1.0mm. An array head includes the array substrate 1, and array-substrate holding means having pressure reducing spaces 7 and 8 on its surface opposite to the surface of the array substrate 1 holding the micro conductive balls 3. The positional precision of ball arrayal is greatly improved by improving precision of hole positions of array holes to suck-hold the micro conductive balls 3 and precision of hole shape.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子又は基
板等の電極部に対し、多数の微小導電性ボールからバン
プを形成するための微小導電性ボールの配列基板及び配
列用ヘッドに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array substrate and array head of minute conductive balls for forming bumps from a large number of minute conductive balls on an electrode portion such as a semiconductor element or a substrate. .

【0002】[0002]

【従来の技術】半導体装置の製造工程において、半導体
素子の電極部(電極パッド)と、プリント配線板等の電
極部或いはTABテープのインナーリード等とを接続す
るための方法として、微小導電性ボールで形成されたバ
ンプを介して両者を接合する方法が知られている(所謂
ボールバンプ法)。このバンプを形成する際に、半導体
素子の電極部に対応する多数の配列孔を有し、各配列孔
に微小導電性ボールを列設配置するようにした配列用基
板が使用される。
2. Description of the Related Art In a manufacturing process of a semiconductor device, a fine conductive ball is used as a method for connecting an electrode portion (electrode pad) of a semiconductor element to an electrode portion of a printed wiring board or an inner lead of a TAB tape. There is known a method of joining the two via a bump formed in (a so-called ball bump method). When forming the bumps, an array substrate is used which has a large number of array holes corresponding to the electrode portions of the semiconductor element, and the minute conductive balls are arrayed in each array hole.

【0003】このバンプ形成において、例えば半導体素
子の電極パッドにバンプを形成する場合、真空吸引等の
方法により配列基板を下側にしてその配列孔に微小導電
性ボールを吸引させて保持し、その状態でバンプ接合用
ステージまで搬送する。その後、接合用ステージにて電
極パッドに微小導電性ボールを熱圧着させることによっ
てバンプを形成する。或いはまた、プリント配線板等の
電極部に低融点金属から成るバンプを形成する場合は、
電極部に予めフラックスを供給しておき、微小導電性ボ
ールを電極部に配列した後リフローする方法が一般的で
ある。
In forming the bumps, for example, when forming bumps on the electrode pads of the semiconductor element, the array substrate is placed downward by a method such as vacuum suction to attract and hold the minute conductive balls in the array holes. In this state, it is transported to the bump bonding stage. Then, bumps are formed by thermocompression-bonding the minute conductive balls to the electrode pads on the bonding stage. Alternatively, when forming bumps made of a low melting point metal on the electrode part of a printed wiring board or the like,
In general, a flux is previously supplied to the electrode part, and the fine conductive balls are arranged on the electrode part and then reflowed.

【0004】従来の配列用基板では、例えば、特開平4
−250643号公報に記載されているようにステンレ
ス等の金属或いはセラミック等を材料とし、各配列孔が
精密放電加工、レーザー照射、エレクトロフォーミン
グ、エッチング等によって加工形成されるというもので
あった。
A conventional arraying substrate is disclosed in, for example, Japanese Patent Laid-Open No.
As described in JP-A-250643, a metal such as stainless steel or a ceramic is used as a material, and each array hole is formed by precision electric discharge machining, laser irradiation, electroforming, etching, or the like.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、配列基
板がステンレス等の金属である場合、Siとの大きな熱
膨張係数差に起因して、接合時の熱による配列基板の熱
膨張によってボール配列時に電極と配列孔の位置ずれが
生じるという問題があった。また、レーザー照射、放電
加工による孔開け法では、配列孔周辺の肉が盛り上が
り、吸引ボールの高さのバラツキや吸引性能の低下等が
発生するという問題があった。
However, when the array substrate is made of a metal such as stainless steel, due to a large thermal expansion coefficient difference with Si, thermal expansion of the array substrate due to heat at the time of bonding causes the electrodes to be arranged during ball alignment. However, there is a problem that the position of the array holes is displaced. Further, in the method of making holes by laser irradiation and electric discharge machining, there is a problem that the meat around the arrayed holes rises and variations in height of the suction balls and deterioration of suction performance occur.

【0006】さらに、従来の配列孔開け加工では孔径1
00μm以下の場合、汎用装置での精密な加工が困難で
あり、それ以下の孔径が必要な場合、孔開け加工後メッ
キによって孔径を窄める方法がとられており、製造工程
が増える上に孔径が不均一になる等の問題があった。ま
た、孔形状も真円形に揃わないためにボールの配列位置
が微妙にずれ、バンプ形成対象(半導体素子やTABの
インナーリード、プリント配線板等)が微細ピッチとな
った場合に、ボールの搭載位置精度が悪くなる等の問題
があった。
Further, in the conventional array drilling process, the hole diameter is 1
If it is less than 00 μm, it is difficult to perform precise processing with a general-purpose device, and if a hole diameter of less than that is required, the method of narrowing the hole diameter by plating after hole processing is adopted, which increases the number of manufacturing processes. There were problems such as non-uniform pore size. In addition, the holes are not aligned in a perfect circle, so the ball positions are slightly deviated and the balls are mounted when the bump formation target (semiconductor element, TAB inner lead, printed wiring board, etc.) has a fine pitch. There was a problem such as poor position accuracy.

【0007】本発明の目的は、バンプ形成位置精度を向
上させ、従来よりも確実にボールバンプを形成し得るボ
ール配列基板及び配列ヘッドを提供するものである。
An object of the present invention is to provide a ball array substrate and an array head which can improve the accuracy of the bump formation position and can form the ball bumps more reliably than before.

【0008】[0008]

【課題を解決するための手段】本発明のボール配列基板
は、半導体素子または基板の電極に対応する位置に微小
導電性ボールを配列するために、前記微小導電性ボール
の径よりも小さい径の配列孔を設けたガラスより成る配
列基板であって、前記配列孔の前記微小導電性ボールを
配列する側の配列孔の径が前記微小導電性ボールの径に
比較して 1/3≦(配列孔の径/微小導電性ボールの径)≦4/
5 なる条件を満足し、かつ前記配列基板の厚みが 0.3mm≦配列基板の厚み≦1.0mm を満足するガラス配列基板である。
The ball-arranged substrate of the present invention has a diameter smaller than that of the micro-conductive balls in order to arrange the micro-conductive balls at positions corresponding to the electrodes of the semiconductor element or the substrate. An array substrate made of glass provided with array holes, wherein the diameter of the array holes on the side of the array holes on which the micro conductive balls are arrayed is 1/3 ≦ (array Hole diameter / micro conductive ball diameter) ≦ 4 /
5 is a glass array substrate that satisfies the condition 5 and the thickness of the array substrate satisfies 0.3 mm ≦ the thickness of the array substrate ≦ 1.0 mm.

【0009】また、本発明のボール配列基板において、
前記ガラス製の配列基板が感光性ガラスを用いて作製さ
れたことを特徴とするガラス配列基板である。
In the ball array substrate of the present invention,
It is a glass array substrate characterized in that the glass array substrate is made of photosensitive glass.

【0010】或いはまた、本発明の配列ヘッドは、前記
配列基板の下側に前記微小導電性ボールを配列保持する
前記微小導電性ボール配列手段と、前記配列基板を保持
する手段であって、前記配列基板における前記微小導電
性ボールを保持する面とは反対側に減圧空間を設けた配
列基板保持手段と、を含んでいる。
Alternatively, the arraying head according to the present invention comprises the minute conductive ball arraying means for arraying and holding the minute conductive balls under the arraying substrate, and the means for holding the arraying substrate. An array substrate holding means having a reduced pressure space provided on the side of the array substrate opposite to the surface holding the minute conductive balls is included.

【0011】本発明によれば、配列基板の材質をガラス
にし、ボールを吸引保持する配列孔の開孔位置と孔形状
の精度を上げることで、ボール配列位置精度を格段に向
上することができる。
According to the present invention, the accuracy of the ball array position can be remarkably improved by using glass as the material of the array substrate and increasing the accuracy of the opening position and hole shape of the array holes for sucking and holding the balls. .

【0012】[0012]

【発明の実施の形態】以下、図面に基づき、本発明によ
るボール配列基板及び配列ヘッドの好適な実施の形態を
説明する。
BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of a ball array substrate and an array head according to the present invention will be described below with reference to the drawings.

【0013】本発明の微小導電性ボールの配列基板は、
例えば図1に示されるように半導体素子や基板の電極部
に対応するように形成された複数の配列孔を有し、半導
体素子等の電極部に形成されるべき微小導電性ボール
を、配列孔に吸引等により保持し得るようになってい
る。特に、基板材質としてステンレス等の金属に比べ熱
膨張率が低く、Siの熱膨張係数に近いガラスを用いる
ことにより、高温の熱圧着に際しても微小導電性ボール
と電極部の位置ずれを低減させることができる。
The array substrate of the minute conductive balls of the present invention is
For example, as shown in FIG. 1, it has a plurality of array holes formed so as to correspond to the electrode parts of the semiconductor element or the substrate, and the minute conductive balls to be formed in the electrode part of the semiconductor element are arranged in the array holes. It can be held by suction or the like. In particular, by using glass, which has a coefficient of thermal expansion lower than that of metal such as stainless steel and has a coefficient of thermal expansion close to that of Si, as a material for the substrate, it is possible to reduce the positional deviation between the minute conductive balls and the electrode portion even at the time of high temperature thermocompression bonding. You can

【0014】ガラスより成る配列基板を用いると、例え
ば加圧転写する際に圧力をかけ過ぎて配列基板の開孔部
にボールが食い込んだ場合に、酸あるいはアルカリ等の
金属を溶解する溶液に浸すことにより容易にその食い込
んだ微小金属ボールを除去することができる。金属製の
配列基板の場合は配列基板自身が金属であるため、溶解
液に溶けてしまい食い込んだ微小ボールを完全に除去す
るのは困難である。
When an array substrate made of glass is used, for example, when pressure is applied excessively and pressure is applied to the balls to dig into the openings of the array substrate, the array substrate is immersed in a solution that dissolves a metal such as acid or alkali. This makes it possible to easily remove the fine metal balls that have bitten. In the case of an array substrate made of metal, since the array substrate itself is a metal, it is difficult to completely remove the fine balls that have melted into the dissolution liquid and invaded.

【0015】本発明のガラス配列基板の熱膨張係数は1
〜100(×10-7/℃)の範囲、望ましくはSiの熱
膨張係数(約40×10-7/℃)程度からその2倍程度
までの熱膨張係数の値20〜90(×10-7/℃)であ
れば、金属製の配列基板に比べ配列時の位置ずれをかな
り小さくすることができる。また、ガラスのうちでも特
に感光性ガラスを用いることにより、孔形状の良い微細
配列孔を位置精度よく開孔させ、ボールバンプを微細ピ
ッチ(300μm以下、特に100μm以下のピッチ)
においても位置ずれなく形成することができる。
The thermal expansion coefficient of the glass array substrate of the present invention is 1
˜100 (× 10 −7 / ° C.), preferably a thermal expansion coefficient of Si (about 40 × 10 −7 / ° C.) to about twice that of 20 to 90 (× 10 − 7 / ° C.), the positional displacement during the array can be made considerably smaller than that of the metal array substrate. In addition, among the glasses, particularly by using photosensitive glass, fine array holes having a good hole shape are opened with high positional accuracy, and ball bumps have a fine pitch (pitch of 300 μm or less, particularly 100 μm or less).
Also in the above, it can be formed without displacement.

【0016】さらに、感光性ガラスを用いると、後述す
るようにマスクを用いて露光するため、一括して孔を形
成することができるので配列基板のコストを極めて安く
することができる。この効果は100ピン以上(特に3
00ピン以上)の配列基板の作製で顕著になる。すなわ
ち、放電加工等で1個ずつ開孔を形成する場合は1つで
も失敗すると最初からやり直しとなり、基板作製の歩留
まりが低下してしまう。また、本発明の配列基板にはア
ライメントマークを容易に任意の場所で、しかも任意の
個数で形成することができ、バンプを形成させる電極部
との位置合わせに利用することができる。
Further, when the photosensitive glass is used, since exposure is performed using a mask as described later, holes can be formed at one time, so that the cost of the array substrate can be extremely reduced. This effect is more than 100 pins (especially 3
It becomes remarkable when an array substrate having 100 pins or more) is manufactured. That is, in the case where holes are formed one by one by electric discharge machining or the like, if even one fails, the process is restarted from the beginning, and the yield of substrate fabrication is reduced. In addition, the array substrate of the present invention can easily be formed with an alignment mark at any place and in any number, and can be used for alignment with the electrode portion on which the bump is formed.

【0017】本発明の感光性ガラスは、例えばSiO2
- Al23 - LiO系ガラスをベースにして、感光性
金属してAg,Au,Cu等を含むガラスから成る。ま
た、必要に応じて光増感剤であるCeO2 等を添加して
もよい。この感光性ガラスの両面を研磨し、所望の(半
導体素子等の電極位置に対応した)位置に配列孔開孔パ
ターンを描いたマスクを、研磨したガラス面の一方の面
に載せる。その後マスク上から紫外線を照射し、開孔部
分のガラスを感光させる。そのマスクを除去し、感光し
た部分を結晶化させるために適度な熱処理をする。結晶
化した部分を酸で溶解し、配列孔を形成する。
The photosensitive glass of the present invention is made of, for example, SiO 2
-Al 2 O 3 -LiO-based glass as a base, and a glass containing Ag, Au, Cu, etc. as a photosensitive metal. Further, CeO 2 or the like, which is a photosensitizer, may be added if necessary. Both sides of this photosensitive glass are polished, and a mask having an array hole opening pattern drawn at a desired position (corresponding to an electrode position of a semiconductor element or the like) is placed on one surface of the polished glass surface. After that, ultraviolet rays are radiated from above the mask to expose the glass in the opening portion to light. The mask is removed, and appropriate heat treatment is performed to crystallize the exposed portion. The crystallized portion is dissolved with acid to form arrayed holes.

【0018】開孔位置を±5μm以内(望ましくは±3
μm以内)の精度で加工した本発明の配列基板を使用す
ることにより、配列孔の中心とそれに対応する半導体素
子上のAl電極パッド等の中心から±5μm以内(望ま
しくは±3μm以内)の位置精度でバンプを形成するこ
とが可能である。
The opening position is within ± 5 μm (preferably ± 3
By using the array substrate of the present invention processed with an accuracy of (μm or less), a position within ± 5 μm (preferably within ± 3 μm) from the center of the array hole and the corresponding center of the Al electrode pad or the like on the semiconductor element. It is possible to form bumps with high precision.

【0019】上記方法では、感光した部分が酸によって
エッチングされ易くなることで開口を形成するものであ
るが、感光ガラスの種類を選ぶことによって、感光する
ことにより開孔部以外を酸等によってエッチングされ難
くすることによっても同様の開口部を形成することがで
きる。
In the above method, the exposed portion is easily etched by acid to form the opening. However, by selecting the type of the photosensitive glass, the exposed portion is exposed to acid to etch the portion other than the opening portion with acid or the like. A similar opening can be formed by making it difficult.

【0020】本発明の配列基板は、ボール配列時に圧力
或いは熱を印加し得るヘッドに付設して使用することも
できる。この場合、配列基板には接合時の圧力に耐え得
る強度を持たせるために、ある程度の厚みが必要であ
る。なお、この厚みが厚過ぎると酸等による溶解が困難
になる。本発明者等は種々の厚みの配列基板を用いて検
討した結果、開孔が不均一にならないためには0.1〜
1.0mmの厚さが適当であることを見出した。
The array substrate of the present invention can also be used by being attached to a head to which pressure or heat can be applied when the balls are arrayed. In this case, the array substrate needs to have a certain thickness in order to have a strength capable of withstanding the pressure at the time of joining. If this thickness is too thick, it will be difficult to dissolve with an acid or the like. The present inventors have studied using array substrates of various thicknesses, and as a result, in order not to make the openings nonuniform,
It has been found that a thickness of 1.0 mm is suitable.

【0021】ガラス基板の厚みには前述したように制限
がある。例えばその厚みが0.25mm未満の場合に配
列基板を5kgの力が加圧すると、加圧力に耐えられず
配列基板の割れの現象が加圧回数に対して10%程度の
割合で発生した。厚みを0.3mmに設定すると1万回
の加圧においても、配列基板の破損が見られず生産に使
用することができる。一方、その厚みが1mm以上に場
合は、ガラスをエッチング等で溶解して開口する場合、
エッチング時間が長時間になり、また孔径の精度も時間
がかかると多くの孔数で一様に揃えるのが困難であっ
た。従って、ガラス配列基板の厚みは好ましくは0.3
mm≦配列基板の厚み≦1.0mmであることが必要で
あることが本発明により明らかになった。
The thickness of the glass substrate is limited as described above. For example, when the thickness of the array substrate was less than 0.25 mm and a force of 5 kg was applied to the array substrate, the array substrate could not withstand the applied pressure and a phenomenon of cracking of the array substrate occurred at a rate of about 10% with respect to the number of pressurizations. When the thickness is set to 0.3 mm, the array substrate can be used for production without any damage even when the pressure is applied 10,000 times. On the other hand, when the thickness is 1 mm or more, when glass is melted by etching or the like to open,
If the etching time is long and the accuracy of the hole diameter is also long, it is difficult to make the number of holes uniform. Therefore, the thickness of the glass array substrate is preferably 0.3.
The present invention has revealed that it is necessary that mm ≦ thickness of array substrate ≦ 1.0 mm.

【0022】微細ボールを配列基板に適用する際にその
厚みのみならず、吸引保持に必要な開孔径を種々の実験
を通して最適化する必要があった。配列孔の径は単に微
小導電性ボールの径に比べて小さいだけでは、吸引によ
る配列成功率は確保することができない。配列孔の径と
微小導電性ボールの径の比は、1/3未満であると吸引
効率が低下する。本発明の検討では、例えば80μmφ
の半田ボールを500個吸引保持する場合、配列基板の
孔径が20μm以下では吸引保持成功率が80〜87%
であり、孔径を25μm以上に設定すると95%以上の
吸引保持成功率を確保することができた。
When applying the fine balls to the array substrate, it was necessary to optimize not only the thickness thereof but also the aperture diameter required for suction holding through various experiments. If the diameter of the array holes is simply smaller than the diameter of the minute conductive balls, the success rate of array by suction cannot be secured. If the ratio of the diameter of the arrayed holes to the diameter of the minute conductive balls is less than 1/3, the suction efficiency will decrease. In the study of the present invention, for example, 80 μmφ
When 500 solder balls are suction-held, the success rate of suction-holding is 80 to 87% when the hole diameter of the array substrate is 20 μm or less.
Therefore, when the pore diameter was set to 25 μm or more, the suction holding success rate of 95% or more could be secured.

【0023】また、配列孔の径と微小導電性ボールの径
の比が4/5を越えると、微小ボールを電極に転写する
際にかかる圧力によってボールが孔の中へ食い込んでし
まうことが詳細な実験により判明した。例えば40μm
径の金ボールを孔径34μmの配列基板で保持し、ボー
ル1個あたり20gの力で電極上で加圧すると300個
中52個のボールが配列基板の孔に食い込み、電極への
ボール接合不良が発生した。孔径を32μmに設定する
と食い込みは全く発生しなかった。従って、孔径は1/
3≦(配列孔の径/微小導電性ボールの径)≦4/5な
る条件を満足する必要があることが本発明で始めて明ら
かになった。ステンレス等の金属製の配列基板に放電加
工で孔を形成する場合、開孔のまわりに肉の盛り上がり
が発生するため明確にはこのような傾向は現れない。
Further, if the ratio of the diameter of the arrayed holes to the diameter of the minute conductive balls exceeds 4/5, the balls will bite into the holes due to the pressure applied when the minute balls are transferred to the electrodes. It turned out by various experiments. For example 40 μm
When gold balls with a diameter of 34 μm are held by an array substrate and pressure is applied on the electrodes with a force of 20 g per ball, 52 of the 300 balls dig into the holes of the array substrate, resulting in defective ball bonding to the electrodes. Occurred. When the pore size was set to 32 μm, no bite occurred. Therefore, the hole diameter is 1 /
It was found for the first time in the present invention that the condition of 3 ≦ (diameter of array holes / diameter of minute conductive balls) ≦ 4/5 needs to be satisfied. When holes are formed by electric discharge machining on an array substrate made of metal such as stainless steel, such a tendency does not clearly appear because the meat rises around the openings.

【0024】本発明の配列基板における配列孔形状の幾
つかの例を図2に示す。ボールを配列させる側の面を表
面とする。図2において、配列孔の表、裏面の孔径が等
しいものを(A)、表面の孔径が裏面の孔径に比べて小
さいものが(B)、(B)のものとは逆に表面の孔径が
裏面に比べて大きいものが(C)としている。また、
(A)に示されるタイプのものを加工し、表面の孔径を
大きくし、表面開孔部エッジを落としたものを(D)、
(D)に示されるタイプの表面の加工を同様に裏面にも
加えたものを(E)、(B)のタイプと(C)のタイプ
を混合した形状であって、表、裏面の開孔部の孔径が広
く、配列基板内部に向かって孔径が小さくなっていくも
のを(F)としている。
Some examples of array hole shapes in the array substrate of the present invention are shown in FIG. The surface on which the balls are arranged is the surface. In FIG. 2, the arrangement of holes on the front and back sides is the same (A), the diameter of the front surface is smaller than that of the back surface (B), and the diameter of the front surface is opposite to that of (B). The one that is larger than the back surface is (C). Also,
The type shown in (A) was machined to increase the surface pore size, and the surface opening edge was dropped (D),
A shape obtained by similarly processing the back surface of the type shown in (D) to the back surface has a shape in which the types of (E), (B) and (C) are mixed. (F) indicates that the hole diameter of the portion is wide and the hole diameter becomes smaller toward the inside of the array substrate.

【0025】ここで、(B)のタイプはボール吸着面よ
りも反対側の減圧側の径が大きく、配列基板を保持する
配列ヘッドのボールを吸引するために吸引系統の作製が
容易である(配列ヘッドの配列基板を保持する部分に
は、例えば配列基板の孔に対応して真空を供給するため
の溝パターンを作製する必要があり、孔径や孔のピッチ
が狭いとその形成は困難になってくる)。
Here, the type (B) has a large diameter on the pressure-reducing side opposite to the ball suction surface, and since the balls of the array head holding the array substrate are sucked, the suction system can be easily manufactured ( In the portion of the array head that holds the array substrate, for example, it is necessary to form a groove pattern for supplying a vacuum corresponding to the holes in the array substrate, and if the hole diameter or the hole pitch is narrow, its formation becomes difficult. Come).

【0026】上記図2(D)、(E)及び(F)のタイ
プのものにおいて、配列孔の加工は酸によるエッチッグ
法、機械的研磨のどちらでも良い。その際、直線的なテ
ーパーではなく、なめらかな曲線でもかまわない。ま
た、図2(E)、(F)タイプにおいては配列基板の
表、裏面どちらの孔径が大きくても、等しくても良い
が、裏面のボールを吸引保持させる最小孔径部分の孔径
はボール径の1/3〜4/5が望ましい。
In the type shown in FIGS. 2D, 2E and 2F, the array holes may be processed by either an acid etching method or mechanical polishing. In that case, a smooth curve may be used instead of a linear taper. In the type of FIGS. 2E and 2F, the hole diameters of the front surface and the back surface of the array substrate may be the same or may be the same, but the hole diameter of the minimum hole diameter portion for sucking and holding the balls on the back surface is equal to the ball diameter. 1/3 to 4/5 is desirable.

【0027】なお、本発明による配列基板は以下の実施
例に述べる金ボールのチップへの配列の他に、TAB等
のフィルムキャリアの電極への金や半田ボールの配列、
或いはプリント配線板の電極への金や半田ボールの配列
等にも適用できる。半田ボールでバンプを形成する際
は、予め電極部にフラックスを供給しておいてもよい。
本発明によるガラス基板から成る配列基板と、その配列
基板と微小導電性ボールをそれぞれ保持するための減圧
空間を、ボールを保持する面とは反対側に設けた保持手
段と、を含むヘッドと併用すると極めて高精度でボール
バンプを形成することができる。
In addition to the arrangement of gold balls on the chip described in the following embodiments, the arrangement substrate according to the present invention also has an arrangement of gold or solder balls on the electrodes of a film carrier such as TAB.
Alternatively, it can be applied to the arrangement of gold or solder balls on the electrodes of the printed wiring board. When forming bumps with solder balls, flux may be supplied to the electrode portions in advance.
Used together with a head including an array substrate made of a glass substrate according to the present invention, and a holding means provided with a pressure-reducing space for holding the array substrate and minute conductive balls on the side opposite to the surface holding the balls. Then, the ball bump can be formed with extremely high accuracy.

【0028】[0028]

【実施例】図3は、本発明による配列基板を用いた微小
導電性ボールバンプの製造法を示している。以下に図面
を参照しながら詳細に説明する。図3(A)において、
図2(B)のタイプの配列基板1がステンレス製の配列
基板固定治具9に配列基板吸引用減圧空間8を減圧する
ことにより固定されている。直径60μmのAuを主成
分とする微小なボール3を配列基板固定治具9のボール
吸引用減圧空間7を減圧することにより一括吸引して保
持する。
EXAMPLE FIG. 3 shows a method of manufacturing micro conductive ball bumps using an array substrate according to the present invention. A detailed description will be given below with reference to the drawings. In FIG. 3A,
The array substrate 1 of the type shown in FIG. 2B is fixed to the array substrate fixing jig 9 made of stainless steel by depressurizing the array substrate suction depressurizing space 8. The minute balls 3 having a diameter of 60 μm and containing Au as a main component are collectively sucked and held by depressurizing the ball suction depressurizing space 7 of the array substrate fixing jig 9.

【0029】配列基板1にはボール径の1/2の30μ
m径の配列孔2が開けてある。ボール3は配列基板1の
背面から配列基板固定治具9のボール吸引用減圧空間7
の減圧により吸引することによってこの配列孔2に保持
されている。
The array substrate 1 has 30 μ which is ½ of the ball diameter.
An array hole 2 of m diameter is opened. The balls 3 are from the rear surface of the array substrate 1 to the ball suction decompression space 7 of the array substrate fixing jig 9.
It is held in this array hole 2 by suctioning under reduced pressure.

【0030】図3(B)において、配列基板1を半導体
素子5上に移動し、ボール3と電極パッド4の位置を合
わせる。ここで、配列基板に形成したアライメントマー
クを用いると迅速な位置合わせが可能である。
In FIG. 3B, the array substrate 1 is moved onto the semiconductor element 5, and the balls 3 and the electrode pads 4 are aligned with each other. Here, if an alignment mark formed on the array substrate is used, quick alignment is possible.

【0031】図3(C)において、保持したボール3を
支持台6の上に置かれた半導体素子電極パッド4に向か
って下降させる。そして、ボール1ケ当たり10〜30
gの荷重で加圧する。
In FIG. 3C, the held ball 3 is lowered toward the semiconductor element electrode pad 4 placed on the support 6. And 10 to 30 per ball
Pressurize with a load of g.

【0032】図3(D)において、ボール3を一括接合
し、ボール吸引用減圧空間7を大気圧にし、配列基板1
を上昇させる。
In FIG. 3 (D), the balls 3 are joined together and the reduced pressure space for ball suction 7 is brought to atmospheric pressure, and the array substrate 1
To rise.

【0033】この例では上記のように、この配列基板1
は配列基板吸引用減圧空間8を減圧することによって吸
着されるが、配列基板吸引用減圧空間8を無くした配列
基板固定治具9に配列基板1を固定した一体型のボール
吸引、転写用ヘッドを使用しても良い。また、本発明の
配列基板固定治具9は加熱機構を備えており、ボールの
温度を上げて接合することもできる。
In this example, as described above, this array substrate 1
Is adsorbed by decompressing the array substrate suction decompression space 8, but an integrated ball suction / transfer head in which the array substrate 1 is fixed to the array substrate fixing jig 9 without the array substrate suction decompression space 8. May be used. Further, the array substrate fixing jig 9 of the present invention is provided with a heating mechanism, so that it is possible to raise the temperature of the balls to join them.

【0034】上記実施例において、微小導電性ボール3
を吸引保持する際に、吸引もれ(抜け)、或いは孔形状
不良によるエアーもれ等による余剰ボールの吸着は全く
なかった。半導体素子支持台6に設置した半導体素子5
は、300〜500℃に加熱してある。バンプは電極材
のAlとAl−Au系合金を形成して接合しており欠落
はない。本発明の配列基板の熱影響によるバンプ形成時
の位置ずれは±3μm以内であった。バンプ高さのバラ
ツキは±2μm以内であった。また、このようなバンプ
付き半導体素子を搬送してもバンプの脱落はなかった。
更に、このバンプを用いて半導体素子をフィルムキャリ
アのインナーリードに接合したところ、リードの流れ落
ちが全くないことも確認している。
In the above embodiment, the minute conductive balls 3
When sucking and holding, the excessive balls were not sucked due to the suction leakage (removal) or the air leakage due to the defective hole shape. Semiconductor device 5 installed on semiconductor device support 6
Is heated to 300 to 500 ° C. The bumps are formed by forming Al and an Al-Au-based alloy with the electrode material Al and joining them, and there is no chipping. The positional deviation of the array substrate of the present invention due to the influence of heat when forming bumps was within ± 3 μm. The variation in bump height was within ± 2 μm. Moreover, even if such a semiconductor device with bumps was transported, the bumps did not fall off.
Furthermore, when a semiconductor element was joined to the inner lead of the film carrier using this bump, it was confirmed that there was no drop of lead.

【0035】上述の接合条件と同一条件で、放電加工に
よって配列孔を形成させたステンレスの配列基板を用い
てボールバンプを形成させたところ、±10μm以上の
位置ずれが生じた。また、±7μmのバンプ高さのバラ
ツキが生じた。配列基板固定治具に設けるボール吸引用
減圧空間が大きく、配列孔周辺の配列基板固定治具との
接触面積が著しく小さいと接合時の圧力に配列基板が耐
えられなくなる恐れがある。配列基板の破壊を防ぐため
ボール吸引用減圧空間は配列孔の直径の10〜100倍
の溝状であることが望ましい。
When ball bumps were formed using an array substrate of stainless steel in which array holes were formed by electric discharge machining under the same bonding conditions as described above, a displacement of ± 10 μm or more occurred. Further, there was a variation in bump height of ± 7 μm. If the reduced pressure space for ball suction provided in the array substrate fixing jig is large and the contact area with the array substrate fixing jig around the array holes is extremely small, the array substrate may not be able to withstand the pressure during bonding. In order to prevent the destruction of the array substrate, it is desirable that the reduced pressure space for ball suction has a groove shape 10 to 100 times the diameter of the array holes.

【0036】しかし、格子状にボールを吸引して面配列
させる場合、図4(A),(B)に示すように配列基板
1に格子状に配列孔2を設けるが、その際、図5に示す
ようにボール吸引用減圧空間7aに柱状突起10を設
け、配列基板固定治具9と配列基板1の接触面積を増や
す必要がある。前記接触面積を増やす方法としては、そ
の他に例えばボール吸引用減圧空間7aに多孔質材を使
用しても良いし、配列基板固定治具9自体に多孔質材を
使用しても良い。
However, when the balls are attracted and arranged in a lattice in a plane arrangement, the arrangement holes 1 are formed in a lattice form in the arrangement substrate 1 as shown in FIGS. 4 (A) and 4 (B). It is necessary to increase the contact area between the array substrate fixing jig 9 and the array substrate 1 by providing the columnar projections 10 in the ball suction decompression space 7a as shown in FIG. As another method for increasing the contact area, a porous material may be used for the ball suction decompression space 7a, or a porous material may be used for the array substrate fixing jig 9 itself.

【0037】[0037]

【発明の効果】以上説明したように本発明によれば、微
小導電性ボール配列基板或いはそれを用いた配列用ヘッ
ドにより、配列基板の材質をガラスにし、ボールを吸引
保持する配列孔の開孔位置と孔形状の精度を上げたの
で、ボール配列位置精度が格段に向上し、半導体チッ
プ、フィルムキャリア及びプリント配線板等の電極に高
精度で微小導電性バンプを形成することができる。
As described above, according to the present invention, the array substrate is made of glass and the array holes for sucking and holding the balls are formed by the array substrate of minute conductive balls or the array head using the array substrate. Since the precision of the position and the shape of the holes is improved, the precision of the ball arrangement position is remarkably improved, and the minute conductive bumps can be formed on the electrodes of the semiconductor chip, the film carrier, the printed wiring board and the like with high precision.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明による配列基板の実施形態における外観
斜視図である。
FIG. 1 is an external perspective view of an array substrate according to an embodiment of the present invention.

【図2】本発明の配列基板における配列孔の形状例をそ
れぞれ示す断面図である。
FIG. 2 is a cross-sectional view showing an example of the shape of array holes in the array substrate of the present invention.

【図3】本発明の配列基板を用いた微小導電性ボールバ
ンプ形成法の例を工程順に示す図である。
FIG. 3 is a diagram showing an example of a method of forming a minute conductive ball bump using the array substrate of the present invention in the order of steps.

【図4】本発明における(A)は微小導電性ボールの格
子状配列孔の例を示す配列基板の外観斜視図、(B)は
該配列基板とその配列基板固定治具を示す図である。
FIG. 4A is an external perspective view of an array substrate showing an example of a grid-like array hole of minute conductive balls in the present invention, and FIG. 4B is a diagram showing the array substrate and a jig for fixing the array substrate. .

【図5】本発明における(A)は微小導電性ボールの格
子状配列孔の例を示す配列基板の断面図、(B)は
(A)のP矢視図である。
5A is a cross-sectional view of an array substrate showing an example of a grid-like array hole of micro-conductive balls in the present invention, and FIG. 5B is a P arrow view of FIG.

【符号の説明】[Explanation of symbols]

1 微小導電性ボール配列基板 2 配列孔 3 微小導電性ボール 4 電極パッド 5 半導体素子 6 支持台 7,7a ボール吸引用減圧空間 8 配列基板吸引用減圧空間 9 配列基板固定治具 10 柱状突起 1 Micro Conductive Ball Array Substrate 2 Array Hole 3 Micro Conductive Ball 4 Electrode Pad 5 Semiconductor Element 6 Support 7 and 7a Decompression Space for Ball Suction 8 Decompression Space for Array Substrate Suction 9 Array Board Fixing Jig 10 Columnar Protrusion

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子または基板の電極に対応する
位置に微小導電性ボールを配列するために、前記微小導
電性ボールの径よりも小さい径の配列孔を設けたガラス
より成る配列基板であって、 前記配列孔の前記微小導電性ボールを配列する側の配列
孔の径が前記微小導電性ボールの径に比較して 1/3≦(配列孔の径/微小導電性ボールの径)≦4/
5 なる条件を満足し、かつ前記配列基板の厚みが 0.3mm≦配列基板の厚み≦1.0mm を満足することを特徴とする微小導電性ボールの配列基
板。
1. An array substrate made of glass provided with array holes having a diameter smaller than the diameter of the minute conductive balls in order to arrange the minute conductive balls at positions corresponding to the electrodes of the semiconductor element or the substrate. The diameter of the array hole on the side where the micro-conductive balls of the array holes are arrayed is 1/3 ≦ (diameter of array hole / diameter of micro-conductive ball) ≦ 4 /
5. An array substrate of minute conductive balls, wherein the array substrate satisfies the condition 5 and the array substrate thickness satisfies 0.3 mm ≦ array substrate thickness ≦ 1.0 mm.
【請求項2】 前記ガラス製の配列基板が感光性ガラス
を用いて作製されたことを特徴とする請求項1に記載の
微小導電性ボールの配列基板。
2. The array substrate of micro-conductive balls according to claim 1, wherein the array substrate made of glass is made of photosensitive glass.
【請求項3】 請求項1又は請求項2に記載の配列基板
と、 前記配列基板の下側に前記微小導電性ボールを配列保持
する前記微小導電性ボール配列手段と、 前記配列基板を保持する手段であって、前記配列基板に
おける前記微小導電性ボールを保持する面とは反対側に
減圧空間を設けた配列基板保持手段と、を含むことを特
徴とする微小導電性ボール配列ヘッド。
3. The array substrate according to claim 1 or 2, the micro-conductive ball array means for array-holding the micro-conductive balls under the array substrate, and the array substrate. An array substrate holding means provided with a reduced pressure space on the opposite side of the array substrate from the surface holding the array of minute conductive balls.
JP03127497A 1996-01-30 1997-01-30 Ball array substrate and array head Expired - Fee Related JP3819984B2 (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
JP03127497A JP3819984B2 (en) 1996-01-30 1997-01-30 Ball array substrate and array head
EP97937832A EP0964442B1 (en) 1997-01-30 1997-08-28 Ball arranging substrate for forming bump, ball arranging head, ball arranging apparatus, and ball arranging method
US09/355,517 US6571007B1 (en) 1997-01-30 1997-08-28 Ball-arranging substrate for forming bump, ball-arranging head, ball-arranging device, and ball-arranging method
EP10174137A EP2256793B1 (en) 1997-01-30 1997-08-28 Ball-arranging substrate for placement of bumps, ball-arranging head, ball-arranging apparatus and method for arranging balls
PCT/JP1997/003011 WO1998034273A1 (en) 1997-01-30 1997-08-28 Ball arranging substrate for forming bump, ball arranging head, ball arranging device, and ball arranging method
DE69740081T DE69740081D1 (en) 1997-01-30 1997-08-28 BALL ARRANGEMENT SUBSTRATE FOR THE PRODUCTION OF HEELS, BALL ARRANGEMENT HEAD, BALL ARRANGEMENT DEVICE AND BALL ARRANGEMENT PROCESS
TW086112433A TW365682B (en) 1997-01-30 1997-08-30 Ball arranging substrate for forming bump, ball arranging head, ball arranging device and ball arranging method
MYPI97004781A MY119459A (en) 1997-01-30 1997-10-13 Ball-arranging substrate for forming bump, ball-arranging head, ball-arranging device and ball-arranging method.

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP8-35542 1996-01-30
JP3554296 1996-01-30
JP03127497A JP3819984B2 (en) 1996-01-30 1997-01-30 Ball array substrate and array head

Publications (2)

Publication Number Publication Date
JPH09270429A true JPH09270429A (en) 1997-10-14
JP3819984B2 JP3819984B2 (en) 2006-09-13

Family

ID=26369731

Family Applications (1)

Application Number Title Priority Date Filing Date
JP03127497A Expired - Fee Related JP3819984B2 (en) 1996-01-30 1997-01-30 Ball array substrate and array head

Country Status (1)

Country Link
JP (1) JP3819984B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000015595A (en) * 1998-08-31 2000-03-15 김규현 Solder ball bumping method for fabricating a semiconductor package
US6107181A (en) * 1997-09-08 2000-08-22 Fujitsu Limited Method of forming bumps and template used for forming bumps
US6320158B1 (en) 1998-01-29 2001-11-20 Fujitsu Limited Method and apparatus of fabricating perforated plate
JP2003069207A (en) * 2001-08-28 2003-03-07 Kyushu Hitachi Maxell Ltd Mask for sucking solder ball and its manufacturing method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6107181A (en) * 1997-09-08 2000-08-22 Fujitsu Limited Method of forming bumps and template used for forming bumps
US6432806B1 (en) 1997-09-08 2002-08-13 Fujitsu Limited Method of forming bumps and template used for forming bumps
US6320158B1 (en) 1998-01-29 2001-11-20 Fujitsu Limited Method and apparatus of fabricating perforated plate
KR20000015595A (en) * 1998-08-31 2000-03-15 김규현 Solder ball bumping method for fabricating a semiconductor package
JP2003069207A (en) * 2001-08-28 2003-03-07 Kyushu Hitachi Maxell Ltd Mask for sucking solder ball and its manufacturing method

Also Published As

Publication number Publication date
JP3819984B2 (en) 2006-09-13

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