JPH0926953A - Signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the signal processor of a small scale capable of being used in common for product-sum operations and division. SOLUTION: Plural signal processing elements 105 are cascade-connected and one signal processor provided with three signal paths is constituted. In the respective signal processing elements 105, for shift addition for the multiplication of a variable and a constant to be the base of the product-sum operation, first and second shifters 12 and 13 and an adder-subtractor 14 are used. For subtraction and a shift processing for calculating a partial quotient and a partial remainder in the case of the division, the adder-subtractor 14 and a third shifter 15 for shifting the result are used. The calculated partial quotient is transferred through a flag holding circuit 16 to the signal processing element 105 of a next stage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing device for arithmetic operation processing of video signals and audio signals.

[0002]

2. Description of the Related Art Today, the conventional NTSC (National Telev)
In addition to the ision System Committee) method, EDTV (Ex
tended Definition TV) system, HDTV (High Definit)
Ion TV) and other new broadcasting systems have been put to practical use. Therefore, it is strongly desired to realize a flexible video signal processing device that can be shared by processing algorithms of different broadcasting systems. However, conventional television receivers
Since a plurality of dedicated hardware corresponding to each one broadcasting system is built in and the hardware used is switched according to the received signal, there is a drawback that the cost becomes high.
In addition, it is necessary to newly develop dedicated hardware in order to support the broadcasting system that will be started in the future and to respond to changes in the processing algorithm, which leads to the problem of longer development period and higher development cost. Also had.

In some television receivers, in addition to filtering of pixel signals, that is, product-sum calculation processing, subtraction for obtaining a difference between a pixel signal belonging to a frame and a pixel signal belonging to another frame, that is, an interframe difference. Processing and subtraction processing for obtaining a difference between two pixel signals in one frame, that is, an edge amount are executed. Further, the amount of motion is obtained by a division process in which the difference between frames is divided by the amount of edge. A mixing process of adding the result of the moving image process and the result of the still image process at a ratio according to the amount of motion is also executed.

A conventional product-sum operation circuit for executing filter processing has been composed of a plurality of multiplication circuits and a plurality of adders. Each multiplication circuit has a complicated structure in which a large number of full adders are connected in a tree shape, for example. Since the product-sum calculation circuit includes a multiplication circuit having a complicated structure, it has a problem that the circuit scale is large and the processing speed is slow.

A conventional division circuit for calculating a motion amount is
A ROM (Read Only Memory) was used. A large number of division results are stored in the ROM, and the result of the combination of the dividend (frame difference) and the divisor (edge amount) is 1
One address is given to the ROM and 1 corresponding to the address
The two calculation results are read out from the ROM. Since this division circuit includes the ROM, there is a problem that the circuit scale is large.

The conventional mixing circuit for the mixing process is composed of two multiplication circuits, one adder and one subtractor. Each multiplication circuit has a complicated structure in which a large number of full adders are connected in a tree shape, for example. Assuming that the result of the moving image processing is A, the result of the still image processing is B, and the motion amount is K, the result MX of the mixing processing is, for example, by executing the calculation of MX = K × A + (16−K) × B. Desired. Here, the amount of movement K is an arbitrary integer among integers from 0 to 16. Since this mixing circuit includes a multiplication circuit having a complicated structure, it has the same problem as the product-sum calculation circuit.

[0007]

Each of the plurality of dedicated hardware built into the conventional television receiver is composed of a combination of a plurality of dedicated units. These dedicated units include the product-sum calculation circuit, the division circuit, and the mixing circuit as described above. As long as these dedicated units are used, the flexible video signal processing device as described above cannot be realized. The same applies to the processing of audio signals.

An object of the present invention is to enable one circuit unit for signal processing to be shared by a plurality of processing algorithms.

Another object of the present invention is to reduce the circuit scale of the signal processing device.

[0010]

In order to achieve the above object, the present invention realizes a signal processing device which can be used for both product-sum operation processing and division processing without using a ROM or a multiplication circuit having a complicated structure. It was done. Specifically, the first signal processing device is configured by a plurality of processing elements that are connected in cascade. With these plural processing elements, a first path for transferring an input data signal of the first signal processing device and second and third paths for transferring a data signal indicating a corresponding processing result of each input data signal. And a path is constructed. Each of the plurality of processing elements includes a first input arranged on the first path, a second input arranged on the second path, and a third input.
A third input arranged on the path, and a data holding circuit for holding the data signal supplied via the first input,
Calculation for obtaining a calculation result of addition and subtraction of the data signal supplied from the data holding circuit and another data signal supplied via the second input and supplying a data signal indicating the calculation result to the second path A circuit, an output selection circuit for supplying either the data signal supplied from the data holding circuit or the data signal indicating the operation result to the first path, and the flag signal supplied via the third input. A flag holding circuit for connecting and holding the flag signal indicating the sign of the operation result and supplying the connected flag signal to the third path, the data holding circuit, the operation circuit, the output selection circuit, and the flag holding And a processing control circuit for controlling the operation of each of the circuits. Moreover, the arithmetic circuit adds and subtracts an input shifter for performing a certain amount of shift processing to the data signal supplied from the data holding circuit, and a data signal indicating the result of the shift processing by the input shifter and another data signal. An adder / subtractor for execution, a result shifter for performing a certain amount of shift processing on a data signal indicating the operation result of the adder / subtractor, and a result for holding a data signal indicating the result of the shift processing by the result shifter A register and an input selection circuit for supplying either the data signal supplied via the second input or the data signal supplied from the result register to the adder / subtractor are provided.

According to the first signal processing apparatus, the product-sum calculation process is executed by using the input shifter and the adder / subtractor. If the input data signal is transferred via the first path and the data signal indicating the intermediate result of the product-sum calculation processing is transferred via the second path, the final product-sum calculation processing by a plurality of processing elements will be performed. The result can be obtained. Second
The bypass from the first path to the first path is configured by the output selection circuit, and the first data signal indicating the final result of the product-sum calculation processing is generated.
By transferring to the path, other processing can be executed by the remaining processing elements. Further, according to the first signal processing device, the division processing is executed by using the adder / subtractor, the flag holding circuit and the result shifter. At this time, the divisor signal is applied to the first path and the dividend signal is applied to the second path, and the divisor signal passes through the first path and the partial remainder signal passes through the second path.
The partial quotient signals are respectively transferred via the third path via the path. Then, a signal representing the final result of the division processing, that is, the quotient, is obtained from the flag holding circuit of the processing element at the final stage.

Further, the present invention realizes a signal processing device for executing mixing processing without using a multiplication circuit having a complicated structure. Specifically, the second signal processing device is configured by a plurality of processing elements that are connected in cascade. The plurality of processing elements each provide a first for transferring a corresponding input data signal of the second signal processing device.
And a second path and a third path for transferring a data signal indicating the processing result of the input data signal. Each of the plurality of processing elements includes a first input arranged on the first path, a second input arranged on the second path, a third input arranged on the third path, and a first input. A first latch for holding a data signal supplied through the first path and supplying the held data signal to the first path; and holding the data signal supplied through the second input and the held data A second latch for supplying a signal to the second path, a third latch for holding a data signal supplied via a third input, a data signal supplied from the first latch and a second latch A selection circuit for selecting one of the supplied data signals according to a supplied selection signal, and an addition for obtaining the sum of the selected data signal and the data signal supplied from the third latch Fixed to the data signal indicating the sum of the adder and the adder And subjected to the shift processing in which was decided and a shifter for supplying a data signal indicating the result of the shift processing to the third pass.

According to the second signal processing device described above, two data signals to be mixed are transferred through the first and second paths, and a data signal indicating an intermediate result of the mixing processing is transmitted through the third path. Be transferred through. Then, a signal indicating the final result of the mixing process is obtained from the shifter of the processing element at the final stage.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific examples of the signal processing device according to the present invention will be described below with reference to the drawings.

FIG. 1 shows an example of the configuration of a signal processing device according to the present invention. In FIG. 1, a signal processing device 100
Are four signal processing elements (SP
E) 105. The signal processing elements 105 from the first stage to the fourth stage are respectively connected to SPE1, SPE2,
We will call them SPE3 and SPE4. Each SPE is
First input 101, second input 102, and third input 103
And

FIG. 2 shows the internal structure of the SPE1 shown in FIG. The SPE 1 includes a data holding circuit 1, an arithmetic circuit 2, an output selection circuit 7, a flag holding circuit 16, and a processing control circuit 5. SPE2, SPE3 and S
The internal structure of each PE 4 is the same as that shown in FIG.

The data holding circuit 1 is composed of first, second and third latches 8, 9 and 10 for holding three data signals supplied via the first input 101. These first, second and third latches 8, 9, 10 are
The shift registers are connected in series so as to form one shift register.

The arithmetic circuit 2 has a first register (input register) 3 for holding a data signal supplied via the second input 102, and three data signals held by the data holding circuit 1. A data selection circuit 22 for selecting at least one data signal, first and second shifters (input shifters) 12 and 13 for performing a certain amount of shift processing on each selected data signal, and the first and second shifters 12 and 13. 1st and 2nd
An adder / subtractor 14 for performing addition and subtraction of a data signal indicating the result of the shift processing by the shifters 12 and 13 and another data signal, and a fixed amount of shift processing on the data signal indicating the operation result L of the adder / subtractor 14. It is supplied from a third shifter (result shifter) 15 for applying, a second register (result register) 4 for holding a data signal indicating the result of the shift processing by the third shifter 15, and a first register 3. It has an input selection circuit 6 for supplying either the data signal or the data signal supplied from the second register 4 to the adder / subtractor 14. The adder / subtractor 14 outputs H as a data signal indicating the result of shift processing by the second shifter 13, and I as a data signal indicating the result of shift processing by the first shifter 12.
When the data signal supplied from the input selection circuit 6 is J, addition H + I, addition I + J, subtraction I-J, or subtraction J-I is executed. When executing the subtraction, the adder / subtractor 14 supplies the flag signal K indicating the sign of the subtraction result L together with the data signal indicating the subtraction result L. In the following description, if L <0, then K = 0, and L ≧
If 0, then K = 1. The adder / subtractor 14
Has a function of directly supplying the data signal supplied from the input selection circuit 6 to the third shifter 15.

The output selection circuit 7 selects any one of the three data signals held in the data holding circuit 1 and the data signal supplied from the third shifter 15, and outputs the first output 111. Via the first input 101 of the SPE2
To be supplied to The output data signal of the third shifter 15 is transmitted through the second output 112 to the second input 10 of the SPE2.
2 is also supplied. The flag holding circuit 16 has a third input 1
The flag signal supplied from the adder / subtractor 14 is connected to the flag signal supplied via 03 and held.
The concatenated flag signal is output to S via the third output 113.
It is supplied to the third input 103 of PE2. Processing control circuit 5
Controls the operations of the data holding circuit 1, the arithmetic circuit 2, the output selection circuit 7, and the flag holding circuit 16.

FIG. 3 shows the internal configuration of the processing control circuit 5. The processing control circuit 5 includes four control registers 200 for storing control information and a write control circuit 2 for writing control information in the four control registers 200.
01 and four read control circuits 202 for reading control information from the four control registers 200. In the write control circuit 201, an address for designating the control register 200 to be written has an address bus 20.
4, data indicating control information to be written is transmitted via the data bus 203, and a write control signal is transmitted via the signal line 20.
5 respectively. Each control register 200
Is the operation field OP and the shift field SFT
, Select field SEL, store field STR
It consists of In the operation field OP, information designating the operation rule of the adder / subtractor 14 is stored. The shift field SFT includes first, second and third shifters 12, 1
The shift amounts of 3 and 15 are stored. Information for controlling the input selection circuit 6, the output selection circuit 7, and the data selection circuit 22 is stored in the selection field SEL.
In the store field STR, the data holding circuit 1, the first
Information for controlling the register 3, the second register 4, and the flag holding circuit 16 is stored. Read control circuit 2
A clock signal CLK is applied to 02 via a signal line 206. The read control circuit 202 synchronizes with the four control registers 200 in synchronization with the supplied clock signal CLK.
The control information is read cyclically from. The read contents of each field of the control register 200 are output as control signals 207, 208, 209 and 210, respectively.

The signal processing apparatus 100 having the above configuration
Can execute the sum-of-products calculation process and the division process. First, the operation of the product-sum calculation process will be described. The basis of the product-sum operation is multiplication of the data signal Y1 and the constant coefficient A1.
Here, A1 = 11/16 = 1/2 + 1/8 + 1/1
An example of No. 6 will be described. The data signal Y1 is given from the first input 101 to the first latch 8 of the SPE1. First
In the cycle, the data selection circuit 22 of SPE1 selects the data signal Y1 held in the first latch 8. The processing control circuit 5 instructs the first and second shifters 12 and 13 to shift right by 1 bit and 3 bits, respectively. The adder / subtractor 14 includes the first and second shifters 12, 13
Add each output of. As a result, the addition result L = Y1 ×
(1/2 + 1/8) is obtained. The data signal indicating the addition result passes through the third shifter 15 as it is,
It is stored in the register 4. In the next second cycle, SP
The data signal Y1 of the first latch 8 of E1 is transferred to the second latch 9. The data selection circuit 22 selects the data signal Y1 held in the second latch 9. The processing control circuit 5 instructs the first shifter 12 to shift right by 4 bits. The input selection circuit 6 selects the data signal supplied from the second register 4. The adder / subtractor 14 has a first
Data signal supplied from shifter 12 and input selection circuit 6
And the data signal supplied from. This allows
Multiplication result Y1 × A1 = Y1 × (1/2 + 1/8 + 1/1
6) is obtained.

In the above example, the multiplication Y1 × A1 is processed by the SPE1 in two cycles, but the processing in the second cycle may be performed by the SPE2. In this case, SPE
The first data signal Y1 held in the first latch 8;
The data signal Y1 × (1/2 + 1/8) held in the third shifter 15 of SPE1 is stored in the first latch 8 and the first register 3 of SPE2 in the second cycle, respectively. In SPE2, the data signal Y1 of the first latch 8 is subjected to right 4-bit shift processing via the data selection circuit 22 and the first shifter 12 and then given to the adder / subtractor 14. On the other hand, the data signal Y1 × (1/2 + 1/8) of the first register 3 is given to the adder / subtractor 14 via the input selection circuit 6. The adder / subtractor 14 executes the addition to obtain the multiplication result Y1 × (1/2 + 1/8 + 1/16)
Ask for. Thus, even with two SPEs, multiplication Y1 × A
1 can be processed. Moreover, while the processing of the second cycle is being performed by SPE2, the processing of a new data signal can be performed by SPE1 in parallel. If such pipeline processing is adopted, the signal processing capability can be improved.

According to the signal processing device 100,
The multiplication of the other data signal Y2 and the other constant coefficient A2 is performed in the same manner, and the result of the product-sum operation processing is Y1 × A1 + Y.
2 × A2 is required.

Next, the execution of division X / Y will be described. FIG. 4 shows one algorithm for division X / Y. Here, it is assumed that the dividend X and the divisor Y are both 8-bit integers. First, from the dividend X and the divisor Y, the 1-bit partial quotient Q1 and the partial remainder R1 = X−Y ×
Q1 is required. Here, if X ≧ Y, Q1 = 1 and R1 = X−Y, and if X <Y, Q1 = 0 and R1.
= X. Next, the result of shifting 1 bit to the right of the divisor Y /
2 as a new divisor, from the partial remainder R1 and the divisor Y / 2, the 1-bit partial quotient Q2 and the partial remainder R2 = R1-Y
/ 2 * Q2 is required. Here, if R1 ≧ Y / 2, then Q2 = 1 and R2 = R1-Y / 2, and R1 <Y /
If 2, then Q2 = 0 and R2 = R1. Then the divisor Y
The right 1-bit shift result Y / 4 of / 2 is used as a new divisor, and a 1-bit partial quotient Q3 and a partial remainder R3 = R2-Y / 4 * Q3 are obtained from the partial remainder R2 and the divisor Y / 4. To be Here, if R2 ≧ Y / 4, Q3 = 1 and R3
= R2-Y / 4, and if R2 <Y / 4, then Q3 = 0 and R3 = R2. Next, using the right one-bit shift result Y / 8 of the divisor Y / 4 as a new divisor, the 1-bit partial quotient Q4 and the partial remainder R8 are calculated from the partial remainder R3 and the divisor Y / 8.
4 = R3−Y / 8 × Q4 is obtained. Where R3
If ≧ Y / 8, then Q4 = 1 and R4 = R3-Y / 8, and if R3 <Y / 8, then Q4 = 0 and R4 = R3. The quotient X / Y to be calculated is the 1-bit partial quotient Q1, Q
2, Q3 and Q4 are connected. The 4-bit quotient Q1Q2Q3Q4 thus obtained is the integer part Q
1 and a decimal part Q2Q3Q4. Similarly, a quotient with an arbitrary bit length can be obtained.

FIG. 5 shows another algorithm for division X / Y. First, a 1-bit partial quotient Q1 and a partial remainder r1 = X−Y × Q1 are obtained from the dividend X and the divisor Y. Here, if X ≧ Y, Q1 = 1 and r1 = X−
Y, and if X <Y, then Q1 = 0 and r1 = X.
Next, using the left 1-bit shift result r1 × 2 of the partial remainder r1 as a new dividend, from the dividend r1 × 2 and the divisor Y,
1-bit partial quotient Q2 and partial remainder r2 = r1 × 2-Y
× Q2 is required. If r1 × 2 ≧ Y, then Q
2 = 1 and r2 = r1 × 2-Y, and if r1 × 2 <Y, then Q2 = 0 and r2 = r1 × 2. Next, using the left 1-bit shift result r2 × 2 of the partial remainder r2 as a new dividend, the 1-bit partial quotient Q3 and the partial remainder r3 = r2 × 2-Y × Q3 are calculated from the dividend r2 × 2 and the divisor Y. Is required. If r2 × 2 ≧ Y, then Q3 = 1 and r
3 = r2 × 2-Y, and if r2 × 2 <Y, then Q3 = 0
And r3 = r2 × 2. Next, the left 1-bit shift result r3 × 2 of the dividend r3 is set as a new dividend, and from the dividend r3 × 2 and the divisor Y, a 1-bit partial quotient Q4 and a partial remainder r4 = r3 × 2-Y × Q4 are obtained. Is required. If r3 × 2 ≧ Y, then Q4 = 1 and r4 = r3 × 2-
If Y and r3 × 2 <Y, then Q4 = 0 and r4 = r3
It is × 2. The desired quotient X / Y is a concatenation of 1-bit partial quotients Q1, Q2, Q3, Q4. The 4-bit quotient Q1Q2Q3Q4 thus obtained has an integer part Q1 and a decimal part Q2Q3Q4. Similarly, a quotient with an arbitrary bit length can be obtained.

FIG. 6 shows a concrete example of the division X / Y according to the algorithm of FIG. In this example, the dividend X =
From 01010010 and the divisor Y = 00110010,
A 4-bit quotient X / Y is required. First, the subtraction XY is executed. Since the result of this subtraction is positive, the partial quotient Q
1 = 1 and the partial remainder r1 = XY. Then, r1 × 2 is obtained by shifting the partial remainder r1 to the left by 1 bit, and then the subtraction r1 × 2-Y is executed. Since the result of this subtraction is positive, the partial quotient Q2 = 1 and the partial remainder r2 = r1.
× 2-Y. Next, after r2 × 2 is obtained by shifting the partial remainder r2 to the left by 1 bit, the subtraction r2 × 2-Y is executed. Since the result of this subtraction is negative, the partial quotient Q
3 = 0 and the partial remainder r3 = r2 × 2. At this time, the subtraction result itself, that is, r2 × 2-Y is discarded, and r2 × 2 previously obtained is adopted as the partial remainder r3. Next, the partial remainder r3 is shifted to the left by 1 bit to r.
After 3 * 2 is found, the subtraction r3 * 2-Y is performed. Since the result of this subtraction is positive, the partial quotient Q4 = 1 and the partial remainder r4 = r3 × 2-Y. In this way, the 4-bit quotient Q1Q2Q3Q4 is obtained. That is, the quotient X / Y is 1.101.

The signal processing device 100 employs the division algorithm shown in FIG. here,
It is assumed that the divisor signal Y is held in the first latch 8 of the SPE1 and the dividend signal X is held in the first register 3 of the SPE1. In the first cycle, the data selection circuit 22 of SPE1 selects the divisor signal Y held in the first latch 8. The first shifter 12 supplies the divisor signal Y as it is to the adder / subtractor 14. On the other hand, the input selection circuit 6 supplies the dividend signal X to the adder / subtractor 14. The adder / subtractor 14 is
The subtraction XY is executed, and the data signal indicating the subtraction result L = XY and the flag signal K indicating the sign of the subtraction result are supplied. The flag signal K is a 1-bit partial quotient Q of division X / Y.
This signal is 1 and is held in the flag holding circuit 16. The data signal indicating the subtraction result XY is the third signal as it is.
It is passed through the shifter 15 and stored in the second register 4.
In the next second cycle, the divisor signal Y of the first latch 8 of SPE1 is transferred to the second latch 9. Input selection circuit 6
Selects the data signal X-Y supplied from the second register 4 when the flag signal K obtained in the first cycle is 1, and from the first register 3 when the flag signal K is 0. The supplied data signal X is selected and the selected data signal is supplied to the adder / subtractor 14. The adder / subtractor 14 outputs the data signal (XY or X) supplied from the input selection circuit 6 as it is. Therefore, the output data signal of the adder / subtractor 14 is a signal indicating the partial remainder r1 of the division X / Y. The third shifter 15 shifts the data signal r1 supplied from the adder / subtractor 14 to the left by 1 bit. As a result, the new multiplicand signal r1 × 2 is transferred to the second input 1 of SPE2.
02. Further, the flag holding circuit 16 sends a flag signal indicating the partial quotient Q1 to the third input 103 of SPE2,
The output selection circuit 7 supplies the divisor signal Y supplied from the second latch 9 to the first input 101 of the SPE2. Therefore, the divisor signal Y is applied to the first latch 8 of SPE2 by S
The new dividend signal r1 × 2 is held in the first register 3 of PE2. In the 3rd and 4th cycles, SP
At E2, a 1-bit partial quotient Q2 of the division X / Y is obtained by the same operation as the first and second cycles in SPE1.
And a new multiplicand signal r2 × 2 is obtained. On this occasion,
The flag holding circuit 16 of SPE2 supplies the connected partial quotient Q1Q2 of 2 bits to SPE3. Thereafter, by a similar operation, the flag holding circuit 16 of the SPE4 outputs a signal indicating a 4-bit quotient X / Y = Q1Q2Q3Q4.

As described above, according to the signal processing apparatus 100, the product-sum operation process and the division process can be executed without using the ROM or the multiplication circuit having a complicated structure. Of course, each S in the signal processing device 100 is
The PE can also perform a single addition process or a single subtraction process.

FIG. 7 shows a modification of the SPE of FIG. The SPE 105a of FIG. 7 has a data signal indicating a 1-bit partial quotient Q1 of division X / Y and a new multiplicand signal r1 ×.
2 and 2 are obtained in one cycle. A first register 3 and a second register 4 in the SPE of FIG.
The SPE 105a of FIG. 7 is obtained by removing the third shifter 15 and adding a result selection circuit 17, a result shifter 18, and a result register 19. Result selection circuit 17
Selects the data signal indicating the subtraction result L obtained by the adder / subtractor 14 when the flag signal K obtained by the adder / subtractor 14 is 1, and the input selection circuit 6 when the flag signal K is 0. The data signal supplied from the above is selected, and the selected data signal is supplied to the result shifter 18. Result shifter 18
Performs a certain amount of shift processing on the data signal supplied from the result selection circuit 17. The result register 19 holds a data signal indicating the result of the shift processing by the result shifter 18, and supplies the held data signal to the input selection circuit 6, the output selection circuit 7 and the second output 112. The input selection circuit 6 supplies either the data signal supplied via the second input 102 or the data signal supplied from the result register 19 to the adder / subtractor 14 and the result selection circuit 17.

According to the SPE 105a of FIG. 7, when the adder / subtractor 14 outputs the data signal indicating the subtraction result L = XY and the flag signal K indicating the sign of the subtraction result L, the flag signal K is 1 In the case, the data signal X- which indicates the subtraction result
Y is selected by the result selection circuit 17, and the flag signal K
When is 0, the data signal X supplied from the input selection circuit 6 is selected by the result selection circuit 17. That is,
The data signal supplied from the result selection circuit 17 to the result shifter 18 is a signal indicating the partial remainder r1 of the division X / Y. The result shifter 18 shifts the partial remainder signal r1 supplied from the result selection circuit 17 to the left by 1 bit. As a result, the new multiplicand signal r1 × 2 is held in the result register 19. On the other hand, the flag signal K is a signal indicating the 1-bit partial quotient Q1 of the division X / Y, and the flag holding circuit 16
Is held. As described above, according to the SPE 105a of FIG. 7, the signal indicating the 1-bit partial quotient Q1 of the division X / Y and the new multiplicand signal r1 × 2 are obtained in one cycle. If the signal path from the result register 19 to the input selection circuit 6 is used, the subtraction processing for obtaining the next 1-bit partial quotient Q2 is performed by the same adder / subtractor 14 as that for obtaining the 1-bit partial quotient Q1. I can do it.

FIG. 8 shows another modification of the SPE of FIG. The SPE 105b in FIG. 8 includes a configuration for absolute value conversion processing, and an operation change control circuit 25 is interposed between the processing control circuit 5a and the adder / subtractor 14. The processing control circuit 5a has a value of 2 for the adder / subtractor 14.
Two control signals 207a and 207b are supplied. One of the control signals 207a is assumed to include a command of addition I + J or a command of subtraction I-J. Also, the other control signal 207b
Means an absolute value conversion command. The operation change control circuit 25 receives the addition I + J command and the absolute value conversion command from the process control circuit 5 a, and also supplies the flag signal F having a negative sign via the third input 103. The control signal 207c is given to the adder / subtractor 14 so as to supply the instruction of the subtraction IJ to the adder / subtractor 14. Further, the operation change control circuit 25 is supplied with the instruction of subtraction IJ and the absolute value conversion instruction from the processing control circuit 5 a, and is supplied with the flag signal F indicating a negative sign via the third input 103. In this case, the control signal 207c is given to the adder / subtractor 14 so as to supply the instruction of addition I + J to the adder / subtractor 14. Furthermore, the third
When the flag signal F indicating a positive sign is supplied via the input 103, the operation change control circuit 25 supplies the addition or subtraction command supplied from the processing control circuit 5a to the adder / subtractor 14 as it is.

The first register 3 is, for example, the second input 10
The data signal indicating the difference A-B supplied via 2 is held. The flag signal F supplied via the third input 103 is a signal indicating the sign of the difference AB. here,
If A−B <0, then F = 0, and if A−B ≧ 0, then F =
Assume that it is 1. The data signal indicating the difference AB is
It is given as a J input to the adder / subtractor 14 via the input selection circuit 6. It is also assumed that the data signal C is given to the adder / subtractor 14 as an I input.

When the processing control circuit 5a supplies the instruction of the subtraction IJ and the absolute value conversion instruction when AB <0, that is, F = 0, the adder / subtractor 14 executes the addition I + J. The addition result L is represented by L = I + J = C + (AB) = C- | AB |. When the processing control circuit 5a supplies the subtraction IJ command and the absolute value conversion command when AB ≧ 0, that is, F = 1, the adder / subtractor 14 executes the subtraction IJ. The subtraction result L is represented by L = IJ = C- (AB) = C- | AB |. That is, regardless of the flag signal F, the adder / subtractor 14 executes an operation of subtracting the absolute value of the difference AB from a certain value C.

When the processing control circuit 5a supplies the addition I + J command and the absolute value conversion command when AB <0, that is, F = 0, the adder / subtractor 14 executes the subtraction I-J. The subtraction result L is represented by L = I-J = C- (AB) = C + | AB. When the processing control circuit 5a supplies the command of addition I + J and the absolute value conversion command when AB ≧ 0, that is, F = 1, the adder / subtractor 14 executes addition I + J. The addition result L is expressed by L = I + J = C + (AB) = C + | AB |. That is, regardless of the flag signal F, the adder / subtractor 14 executes the operation of adding the absolute value of the difference AB to a certain value C.

As described above, according to the SPE 105b of FIG. 8, by changing the operation rule in the adder / subtractor 14 according to the flag signal F, the absolute value conversion process of the difference AB can be achieved. It goes without saying that the data signal to be converted into an absolute value is not limited to the difference A-B.

FIG. 9 shows another connection example of the SPE shown in FIG. The signal processing device 100a of FIG. 9 includes a central processing unit (CPU) 104 and twelve SPEs 105, that is, SPE11, arranged in a two-dimensional array of three rows and four columns.
SPE12, SPE13, SPE14, SPE21, S
PE22, SPE23, SPE24, SPE31, SP
E32, SPE33 and SPE34 and 12 connection circuits 106, that is, C11, C12, C13, C14,
C21, C22, C23, C24, C31, C32, C
33 and C34. For example, C22 is SP
It is interposed between E22 and SPE23. And C
Bypasses 107, 108, 109 and 110 are respectively provided between 21 and C22, between C22 and C23, between C12 and C22 and between C22 and C32. Each of the twelve connection circuits 106 has a built-in control register for storing control information indicating where to transfer the data signal from. The CPU 104
It is responsible for writing data to the control registers of all SPEs 105 and all connection circuits 106.
Therefore, the data bus 203 and the address bus 204
And a signal line 205 for transferring a write control signal (see FIG. 3).

According to the signal processing apparatus 100a, each S
The processing to be executed by the PE 105 can be freely set. In addition, the output data signal of the SPE22 is SPE13 and SP.
It can be distributed to E23, the output data signal of SPE22 can be returned to SPE22, the output data signal of SPE22 can be supplied to SPE24 (skipping SPE23), or the output data signal of SPE14 can be supplied to SPE24. it can. As illustrated in FIG. 9, it is also possible to divide the signal processing device 100a into three parts 121, 122, 123 and cause each part to perform different processing. In addition, in the signal processing device 100a, the three types of S
The PEs 105, 105a, 105b may be mixed.

FIG. 10 shows another configuration example of the signal processing device according to the present invention. In FIG. 10, the signal processing device 150 is composed of a mixing circuit 70 and a mixing control circuit 71. The mixing circuit 70 is composed of five signal processing elements (SPE) 74 that are connected in series. The signal processing elements 74 from the first stage to the fifth stage in the mixing circuit 70 are respectively connected to SPE11, SPE12, SPE13,
They will be referred to as SPE14 and SPE15. Each SPE in the mixing circuit 70 has a first input 151 and a second input 1
52 and a third input 153. Mixing control circuit 71
Are five signal processing elements (SP
E) 75. 1 in the mixing control circuit 71
The signal processing elements 75 from the fifth stage to the fifth stage are respectively S
PE21, SPE22, SPE23, SPE24 and S
I will call it PE25. Each SPE in the mix control circuit 71 has a fourth input 171 and a fifth input 172. Each SPE in the mixing circuit 70 and the mixing control circuit 71
To a common clock signal C via a clock input 80.
LK is supplied. The SPE21 sends the 1-bit mixing ratio signal M1 to the SPE11, the SPE22 sends the 1-bit mixing ratio signal M2 to the SPE12, the SPE23 sends the 1-bit mixing ratio signal M3 to the SPE13, and the SPE24 sends the 1-bit mixing ratio signal M4 to the SPE14. The SPE 25 supplies the 1-bit mixing rate signal M5 to the SPE 15, respectively.

FIG. 11 shows the internal structure of the SPE 11 shown in FIG. The SPE 11 has a first latch 5 for holding a data signal supplied through the first input 151.
1, a second latch 52 for holding the data signal supplied via the second input 152, a third latch 56 for holding the data signal supplied via the third input 153, and a selection The circuit 53, the adder 54, and the shifter 55 are provided. The first, second and third latches 51, 52,
A common clock signal CLK is applied to 56. The data signal held in the first latch 51 is the selection circuit 53.
To the SPE via the first output 161
Twelve first inputs 151 are provided. The data signal held in the second latch 52 is supplied to the selection circuit 53 and is also supplied to the second input 152 of the SPE 12 via the second output 162. The selection circuit 53 includes the first latch 51.
The data signal supplied from the second latch 52 or the data signal supplied from the second latch 52 is selected according to the 1-bit mixing ratio signal (selection signal) M1. Specifically, the selection circuit 53 of the SPE 11 sends the data signal supplied from the first latch 51 to M1 = 1, and the data signal supplied from the second latch 52 to M4 if it is M1 = 0. Supply. The adder 54 includes a selection circuit 53.
The data signal supplied from the third latch 56 and the data signal supplied from the third latch 56 are supplied to the shifter 55. The shifter 55 outputs a data signal obtained by subjecting the data signal supplied from the adder 54 to left 1-bit shift processing. The output data signal of the shifter 55 is sent to the SPE12 via the third output 163.
Of the third input 153. The adder 54 is
It also has a function of directly supplying the data signal supplied from the third latch 56 to the shifter 55. Also, the shifter 55
Has a function of directly outputting the data signal supplied from the adder 54. SPE12, SPE
13, the internal configuration of each of SPE14 and SPE15,
It is similar to FIG.

FIG. 12 shows the internal structure of the SPE 21 shown in FIG. The SPE 21 has a fourth latch 6 for holding the data signal supplied via the fourth input 171.
0 and the fifth latch 61 for holding the data signal supplied via the fifth input 172, a control shifter 62, a subtractor 66, a result selection circuit 67, and a flag holding circuit 69. Is equipped with. Fourth and fifth latches 60,
A common clock signal CLK is applied to 61 and the flag holding circuit 69. The data signal held in the fourth latch 60 is supplied to the control shifter 62 and also to the fourth input 171 of the SPE 22 via the fourth output 181. The control shifter 62 supplies to the subtractor 66 a data signal obtained by subjecting the data signal supplied from the fourth latch 60 to a certain amount of shift processing. Fifth
The data signal held in the latch 61 is supplied to the subtractor 66 and the result selection circuit 67. The subtractor 66 uses the data signal supplied from the fifth latch 61 to control the shifter 62.
Subtract the data signal showing the result of the shift processing by
A flag signal S indicating the sign of the subtraction result T is supplied together with the data signal indicating the subtraction result T. If T <0, then S = 0, and if T ≧ 0, then S = 1. The result selection circuit 67 outputs the data signal indicating the subtraction result T of the subtractor 66 if S = 1, and the data signal supplied from the fifth latch 61 if S = 0.
To the fifth input 172 of the SPE 22 via 82.
The flag holding circuit 69 holds the flag signal S supplied from the subtractor 66, and supplies the held flag signal S to the SPE 11 as a 1-bit mixing ratio signal M1. S
The internal configuration of each of PE22, SPE23, SPE24, and SPE25 is similar to that of FIG.

The operation of the mixing circuit 70 will be described. SP
E11 first, second and third inputs 151, 152, 15
A data signal A, a data signal B, and a data signal O are given to 3, respectively. Data signal A is the result of moving image processing, data signal B is the result of still image processing, and data signal O
Are signals indicating the constant 0, respectively. SPE11, SP
It is assumed that the shifter 55 of each of E12 and SPE13 executes the left 1-bit shift processing, and each shifter 55 of SPE14 and SPE15 does not execute the shift processing. S
The output MX of the shifter 55 of the PE 15 and the movement amount K are represented by MX = K × A + (16−K) × B K = M1 × 8 + M2 × 4 + M3 × 2 + M4 × 1 + M5. That is, the 5-bit mixing ratio M1M2M3
According to M4M5, the two data signals A and B can be mixed in 17 steps.

Further, SPE11, SPE12, SPE1
3, each shifter 55 of SPE14 and SPE15 does not perform shift processing, and the adder 54 of SPE15
If the output of the third latch 56 is directly supplied to the shifter 55, the output MX of the shifter 55 of the SPE 15 is
And the amount of movement K are represented by MX = K × A + (4-K) × B K = M1 + M2 + M3 + M4. That is, the 4-bit mixing ratio M1M2M3
Depending on M4, the two data signals A and B can be mixed in five stages.

As described above, according to the mixing circuit 70, various mixing processes can be executed without using a multiplication circuit having a complicated structure. Moreover, the pipeline operation of each SPE is possible, and the mixing processing result can be obtained every cycle. The third latch 56 and the adder 54 in the SPE 11 can be omitted.

Next, the operation of the mixing control circuit 71 will be described. The data signal D and the data signal C are applied to the fourth and fifth inputs 171 and 172 of the SPE 21, respectively. The data signal C is a signal indicating the interframe difference, and the data signal D is a signal indicating the edge amount. The control shifter 62 of SPE21 performs right 1-bit shift processing, the control shifter 62 of SPE22 performs right 2-bit shift processing, the control shifter 62 of SPE23 performs right 3-bit shift processing, and SPE24.
The control shifter 62 of SPE2
The control shifter 62 of No. 5 executes the right 4-bit shift processing. As a result, the mixing control circuit 71
Will perform division C / D according to the algorithm of FIG. That is, the 5-bit mixing ratio M1M2M3
M4M5 represents the quotient C / D. Where C / D
If ≧ 1, then M1 = M2 = M3 = M4 = M5 = 1,
If C / D <1, then M1M2M3M4 = 16 × C / D and M5 = 0.

If the data signal C is shifted to the left by 4 bits in advance, the control shifter 62 of the SPE 21 shifts left 3 bits and the control shifter 62 of the SPE 22 shifts left 2 bits.
As the bit shift processing, the control shifter 62 of the SPE 23 performs the left 1-bit shift processing, and the control shifter 62 of each of the SPE 24 and SPE 25 does not perform the shift processing. .

As described above, according to the mixing control circuit 71, the division process can be executed without using the ROM or the multiplication circuit having a complicated structure. Moreover, each SP
E pipeline operation is possible.

FIG. 13 shows still another configuration example of the signal processing device according to the present invention. In FIG. 13, the signal processing device 150a includes a mixing circuit 70a and a mixing control circuit 71a.
It is composed of The mixing circuit 70a is composed of four signal processing elements (SPE) 74, that is, SPE11, SPE12, SPE13, and SPE14, which are connected in cascade. The internal configuration of each SPE in the mixing circuit 70a is as shown in FIG. Mixing control circuit 71a
Are four signal processing elements (SP
E) 75a, that is, SPE21, SPE22, SPE
23 and SPE24. Mixing control circuit 7
Each SPE in 1a has a fourth input 173. A common clock signal CL is supplied to each SPE in the mixing circuit 70a and the mixing control circuit 71a via a clock input 80.
K is supplied. SPE21 is a 1-bit mixed rate signal M
1 to SPE11, SPE22 supplies 1-bit mixing ratio signal M2 to SPE12, SPE23 supplies 1-bit mixing ratio signal M3 to SPE13, and SPE24 supplies 1-bit mixing ratio signal M4 to SPE14.

FIG. 14 shows the internal structure of the SPE 21 shown in FIG. The SPE 21 includes a fourth latch 81 for holding the data signal Z supplied via the fourth input 173, a constant holding circuit 82 for holding the constant data signal Z1, and a comparator 83, Flag holding circuit 8
4 is provided. The common clock signal CLK is applied to the fourth latch 81 and the flag holding circuit 84. The data signal Z held in the fourth latch 81 is supplied to the comparator 83.
To the SPE via the fourth output 183
22 to the fourth input 173. Constant holding circuit 82
Supplies the constant data signal Z1 to the comparator 83. The comparator 83 subtracts the data signal Z1 of the constant holding circuit 82 from the data signal Z of the fourth latch 81 and supplies a flag signal S indicating the sign of the subtraction result. If the subtraction result is negative, S = 0, and if the subtraction result is positive or 0, S = 1. The flag holding circuit 84 holds the flag signal S supplied from the comparator 83, and sets the held flag signal S as a 1-bit mixing ratio signal M1 in the SPE11.
Supply to That is, if Z <Z1, then M1 = 0,
If Z ≧ Z1, then M1 = 1. SPE22, SPE2
The internal configuration of each of the SPE 3 and the SPE 24 is similar to that of FIG. However, SPE22, SPE23 and SPE24
The constant holding circuit 82 of each of the
3 and Z4 shall be held respectively. Where Z
1>Z2>Z3> Z4.

FIG. 15 shows the operation of the mixing control circuit 71a. If Z1 ≦ Z ≦ Zmax (Zmax is the maximum value of Z, for example, 1111), M1M2M3M4
= 1111, and if Z2 ≦ Z <Z1, then M1M2M3
If M4 = 0111 and Z3 ≦ Z <Z2, then M1M2
M3 M4 = 0011, and if Z4 ≦ Z <Z3, then M1
If M2M3M4 = 0001 and 0 ≦ Z <Z4, then M
1M2M3M4 = 0000. Therefore, according to the signal processing device 150a, the 4-bit mixing ratio M1M
According to 2M3M4, the two data signals A and B can be mixed in five stages, and the pipeline operation of each SPE is possible. The operation of the mixing circuit 70a is as shown in FIG.
The description is omitted because it is similar to the mixing circuit 70 in 0.

[0050]

As described above, according to the present invention, a signal processing device that can be used for both product-sum calculation processing and division processing is realized by an input shifter, an adder / subtractor, a flag holding circuit, and a result shifter. Therefore, the circuit scale is reduced. Further, since the signal processing device for executing the mixing process is realized by the selection circuit, the adder, and the shifter, the circuit scale can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a signal processing device according to the present invention.

FIG. 2 is a block diagram showing an internal configuration of one signal processing element in FIG.

FIG. 3 is a block diagram showing an internal configuration of a processing control circuit in FIG.

FIG. 4 is a diagram showing one algorithm for division.

FIG. 5 is a diagram showing another algorithm for division.

FIG. 6 is a diagram showing a specific example of division.

FIG. 7 is a block diagram showing a modification of the signal processing element of FIG.

FIG. 8 is a block diagram showing another modification of the signal processing element of FIG.

9 is a block diagram showing another connection example of the signal processing element in FIG. 1. FIG.

FIG. 10 is a block diagram showing another configuration example of the signal processing device according to the present invention.

11 is a block diagram showing an internal configuration of one signal processing element in the upper row of elements in FIG.

12 is a block diagram showing the internal configuration of one signal processing element in the lower element sequence in FIG.

FIG. 13 is a block diagram showing still another configuration example of the signal processing device according to the present invention.

14 is a block diagram showing the internal configuration of one signal processing element in the lower element sequence in FIG.

FIG. 15 is a diagram showing an operation of a lower element row in FIG.

[Explanation of symbols]

 1 Data Holding Circuit 2 Arithmetic Circuit 3 First Register (Input Register) 4 Second Register (Result Register) 5, 5a Processing Control Circuit 6 Input Selection Circuit 7 Output Selection Circuit 8, 9, 10 First to Third Latch 12, 13 first and second shifter (input shifter) 14 adder / subtractor 15 third shifter (result shifter) 16 flag holding circuit 17 result selection circuit 18 shifter (result shifter) 19 register (result register) 22 data selection circuit 25 operation change control Circuits 51, 52 First and second latches 53 Selection circuit 54 Adder 55 Shifter 56 Third latch 60, 61 Fourth, fifth latch 62 Control shifter 66 Subtractor 67 Result selection circuit 69 Flag holding circuit 70, 70a Mixing circuit 71, 71a Mixing control circuit 74 Signal processing element 75, 75a Signal processing element (control processing element) 8 Fourth latch 82 Constant holding circuit 83 Comparator 84 Flag holding circuit 100, 100a Signal processing device 101-103 First to third input 104 Central processing unit (CPU) 105, 105a, 105b Signal processing element 150, 150a Signal processing device 151 to 153 1st to 3rd inputs 171, 172 4th, 5th inputs 173 4th inputs 200 Control register M1 to M5 Mixing ratio signals (selection signals)

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Shintaro Tsubata, 1006 Kadoma, Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor, Nishiyama, 1006, Kadoma, Kadoma, Osaka

Claims (9)

[Claims] 1. A signal processing apparatus comprising a plurality of processing elements, wherein the plurality of processing elements include a first path for transferring an input data signal of the signal processing apparatus, and each of the input data signals. The plurality of processing elements are connected in series so as to form second and third paths for transferring a data signal indicating a corresponding processing result, and each of the plurality of processing elements is arranged on the first path. 1 input, a second input arranged on the second path, a third input arranged on the third path, and data for holding a data signal supplied via the first input A holding circuit, and a calculation result of addition and subtraction of the data signal supplied from the data holding circuit and another data signal supplied via the second input, and a data signal indicating the calculation result is output to the second signal. Operation to feed the path A path, an output selection circuit for supplying either the data signal supplied from the data holding circuit or the data signal indicating the calculation result to the first path, and the output selection circuit supplied via the third input. A flag holding circuit for connecting and holding a flag signal indicating the sign of the operation result to the flag signal and supplying the connected flag signal to the third path; the data holding circuit; the operation circuit; A processing control circuit for controlling the operation of each of the output selection circuit and the flag holding circuit, wherein the arithmetic circuit performs a certain amount of shift processing on the data signal supplied from the data holding circuit. An input shifter, an adder / subtractor for executing addition / subtraction of a data signal indicating the result of the shift processing by the input shifter and another data signal, and an operation result of the adder / subtractor. A result shifter for performing a certain amount of shift processing on the data signal, a result register for holding a data signal indicating a result of the shift processing by the result shifter, and a data signal supplied via the second input And an input selection circuit for supplying one of the data signal supplied from the result register to the adder / subtractor. 2. The signal processing device according to claim 1, wherein the data holding circuit includes a plurality of latches for holding a plurality of data signals supplied via the first input, and the output selection circuit. Has a function of supplying a data signal held in any one of the plurality of latches to the first path, and the arithmetic circuit selects from among the plurality of data signals held in the plurality of latches. The input shifter further comprises a data selection circuit for selecting at least one data signal, wherein each of the input shifters performs a certain amount of shift processing on the selected data signal and outputs a data signal indicating a result of the shift processing. A signal processing device comprising at least one shifter for supplying to the adder / subtractor. 3. The signal processing device according to claim 1, wherein the arithmetic circuit holds a data signal supplied via the second input, and supplies the held data signal to the input selection circuit. A signal processing apparatus, further comprising an input register for. 4. The signal processing device according to claim 1, wherein the arithmetic circuit is one of a data signal supplied from the input selection circuit and a data signal supplied from the adder / subtractor indicating the operation result. And a result selection circuit for supplying the result to the result shifter. 5. The signal processing device according to claim 1, wherein the processing control circuit holds control information that specifies an operation of each of the data holding circuit, the arithmetic circuit, the output selection circuit, and the flag holding circuit. At least one for
A signal processing device comprising a plurality of control registers. 6. The signal processing apparatus according to claim 1, wherein when the flag signal supplied via the third input has a negative sign, subtraction is performed when an addition command is issued from the processing control circuit. Is further provided with an arithmetic change control circuit for causing the adder / subtractor to execute addition when a subtraction command is issued from the processing control circuit. 7. A signal processing device comprising a plurality of processing elements, said plurality of processing elements each comprising first and second paths for transferring a corresponding input data signal of said signal processing device, And a third path for transferring a data signal indicating a processing result of the input data signal, the plurality of processing elements being connected in cascade, each of the plurality of processing elements being arranged on the first path. 1 input, a second input arranged on the second path, a third input arranged on the third path, and a data signal supplied via the first input,
And a first latch for supplying the held data signal to the first path, and a data signal supplied via the second input,
And a second latch for supplying the held data signal to the second path, a third latch for holding the data signal supplied via the third input, and A selection circuit for selecting one of the data signal supplied from the first latch and the data signal supplied from the second latch; and the selected data signal and the third data supplied from the third latch. An adder for obtaining the sum of the data signal and a data signal indicating the sum of the adder, and a data signal indicating the result of the shift processing is supplied to the third path. And a shifter for the signal processing device. 8. The signal processing device according to claim 7, wherein a fourth path for transferring a control data signal of the signal processing device, and a fourth path for transferring a data signal indicating a processing result of the control data signal. And a plurality of control processing elements that are connected in cascade so as to form five paths, wherein each of the plurality of control processing elements includes a fourth input arranged on the fourth path, and a fifth input on the fifth path. Holding a fifth input located at, and a data signal provided through the fourth input,
And a fourth latch for supplying the held data signal to the fourth path, a fifth latch for holding the data signal supplied via the fifth input, and a fourth latch. A control shifter for performing a certain amount of shift processing on the data signal, and a subtractor for subtracting a data signal indicating the result of the shift processing by the control shifter from the data signal supplied from the fifth latch, One of the data signal supplied from the fifth latch and the data signal indicating the subtraction result of the subtractor is added to the fifth signal.
A result selection circuit for supplying to a path, and a flag holding circuit for holding a flag signal indicating the sign of the subtraction result of the subtractor, and held in each flag holding circuit of the plurality of control processing elements. The signal processing device is characterized in that the flag signal is applied as a selection signal to a selection circuit of a corresponding signal processing element among the plurality of signal processing elements. 9. The signal processing device according to claim 7, further comprising a plurality of control processing elements cascade-connected to form a fourth path for transferring a control data signal of the signal processing device, Each of the plurality of control processing elements holds a fourth input arranged on the fourth path, and a data signal supplied via the fourth input,
And a fourth latch for supplying the held data signal to the fourth path, a constant holding circuit for holding a constant data signal, a data signal supplied from the fourth latch, and the constant holding circuit A comparator for performing a magnitude comparison with a constant data signal supplied from, and a flag holding circuit for holding a flag signal indicating the result of the magnitude comparison, each of the plurality of control processing elements The signal processing device, wherein the flag signal held in the flag holding circuit is supplied as a selection signal to a selection circuit of a corresponding signal processing element among the plurality of signal processing elements.