JPH09266452A - Reception device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the reception device for mobile communication equipment by reducing high-power consuming factors and operation unstable factors in a high frequency circuit by reducing high-frequency circuit parts. SOLUTION: A reception signal 1 obtained from an antenna is amplified to a high frequency and the output makes a 1st band-pass filter 3 extract only all channel signals of a corresponding communication system from other radio signals. This outputs is converted in frequency with a local oscillation frequency fL0 and a 2nd band-pass filter 6 passes only a desired wave. This output is supplied to a sample holding circuit 8, and sampled and held. For the sampling of the sample holding circuit 8, a band-limiting sampling theory is used. The discrete signal of the reception signal which is thus obtained is supplied to an I-axis component separating circuit 10 and Q-axis component separating circus 11 respectively. The sampling output is Hilbert-transformed into two orthogonal components on a phase plane by inverting the polarity of the sampling output alternately as to an I and a Q axis. Those two signals are supplied to a complex coefficient filter 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiver in mobile communication equipment, and more particularly to a receiver capable of reducing high power consumption factors and unstable operation factors inherent in the high frequency circuit by reducing the high frequency circuit portion.

[0002]

2. Description of the Related Art One of the points of a receiving device in a mobile communication device is how to reduce the number of high frequency circuit parts and reduce the high power consumption elements, unstable operation elements, manufacturing cost and occupied space in the high frequency circuit. It is in. Here, one of the reasons why the high-frequency part of the receiving device is complicated is that it is very difficult to realize a sharp channel filter for extracting a desired channel band by separating it from an adjacent channel, and it is gradually divided into several stages. This is because the characteristics must be established in.

First, FIG. 38 shows an example of the configuration of a receiving system used in the current mobile communication equipment. Also, as a conventional example, as described in Japanese Patent Laid-Open No. 6-164243, in order to reduce a high frequency circuit portion, a direct demodulation method in which a carrier frequency is a local oscillation frequency, that is, a direct conversion to a baseband band is performed. FIG. 39 shows a direct conversion receiving system which is a system.

[0004]

In FIG. 38, a radio signal having a frequency fc enters from an antenna ANT, is amplified by a low noise amplifier LNA, and then passes through a band pass filter BPF1 to be a target of a communication system. The entire existing frequency channel is extracted from another communication signal group. The output is converted into the first intermediate frequency by the frequency converter MIX1, and the signal components other than the desired frequency channel are removed as much as possible by the first intermediate frequency filters IF1-FLT. The output is reinforced by the first intermediate frequency amplifier IF1-AMP and supplied to the frequency converter MIX2.

The received signal having the second intermediate frequency is further filtered by the second intermediate frequency filter IF2-FLT to remove signal components other than the desired frequency channel. The output is the second
It is reinforced by the intermediate frequency amplifier IF2-AMP and enters the quadrature detector Q-DET.

[0006] Here, the second intermediate frequency fLO also receives a frequency conversion action, and is reduced to the baseband. A low-pass filter LPF is passed to remove signal components other than frequency channels including image signal removal in frequency conversion. In this way, the signal of the desired channel is taken out, amplified by the baseband amplifier BF-AMP to a predetermined signal strength, and the reception output is provided.

Therefore, first, there will be described a problem concerning a receiving apparatus of a communication device used in the vicinity of the microwave band shown in FIG. 38 which is a conventional example.

As a first problem, as seen in the conventional example of FIG. 38, frequency conversion is performed in three stages including quadrature detection, four stages of filtering and four stages of amplification are performed. Three types of local oscillators, LO1, LO2, and fLO, must be prepared. Therefore, many parts are required for the receiving device.

The second problem is that many of these components generate large power consumption.

Next, let us consider an example of FIG. 39 for a direct conversion receiving device in which the receiving device is simplified. In FIG. 39, the received AM high frequency signals are input to the pair of mixers 18 and 19, and high frequency signals having carrier frequencies different in phase by 90 degrees from each other are mixed.

The outputs of the mixers 18 and 19 are passed through low-pass filters 23 and 24 and A / D converters 25 and 26, respectively, and the phase shifters 2 are
Enter 7, 28. The signals whose phases have been delayed by the phase shifters 27 and 28 so that they are different from each other by 90 degrees are input to the matrix circuit 29, and the sum and difference signals of the respective signals are derived.

The signal from the matrix circuit 29 is converted into an analog signal by the D / A converters 30 and 31, the modulated signals of the sidebands of the AM high frequency signal are separated, and the signal with less noise is speaker 35. It is said that a direct conversion receiving device that is selectively output to and has less noise and interference is realized.

Now, let us consider the power consumption of the circuit and the performance required for the parts in this conventional example. In the conventional example of FIG. 39, the channel filter for separating and extracting the received signal from the adjacent interference signal is secured by the low-pass filters 23 and 24 and the digital filter provided in the digital circuit after A / D conversion. .

When the signal processing in the demodulation circuit 42 is performed by a digital circuit, the filters 23 and 24 in the radio system can be simplified, but in order to obtain sufficient amplitude resolution and frequency resolution, the operation of the digital system 42 is performed. Since the clock speed must be sufficiently higher than the highest frequency component of the analog system, the operating part becomes faster, while the digital system 42 has a constant operating amplitude and a few volts, so the analog system processes it. However, there is a problem that the power consumption is increased several times as much as the case of

Further, in the logic circuit system, many processing systems operate in parallel. That is, even if the operation clock speed is close to the baseband frequency, the total power consumption of the circuit is (square of voltage amplitude) × (processing speed) × (circuit system load capacitance) × (parallel number). It is big. That is, processing signals with digital circuits has the negative factor of increasing power consumption.

A third problem is that, when the signal processing is digitized, the power consumption is increased several times as compared with the case where the processing is performed by the radio system.

A fourth problem is that the conventional digital filter has complicated calculations, requires addition, subtraction, multiplication and division even with a simple structure, and power consumption cannot be ignored.

A / D for digitizing the signal
Considering the converters 25 and 26, the voltage amplitude required for the input signal is generally as large as 1 to 2 volts. Therefore, the ability to supply that amplitude is shown in FIG.
In the conventional example shown in FIG. 9, the mixer 18 at the preceding stage,
19 will be required. This cannot be said to be possible in the frequency of the AM radio band, that is, the medium-wave broadcasting band targeted by the conventional example of FIG.
In the frequency band of V broadcasting and mobile phones, there is no mixer that can obtain such a large output. Therefore, in general, it is necessary to insert an amplifier in front of the A / D converter to amplify the voltage amplitude. Therefore, the fifth problem is that the adoption of the method using the A / D converter has a negative factor that the electric power of the wireless system or the analog system greatly increases.

In the conventional system shown in FIG. 39, the frequency generated by the local oscillator is equal to the carrier frequency of the received signal. For this reason, the sixth problem is that a failure occurs in many communication systems. That is, as shown in FIG. 40 (a), the local oscillation signal of the conventional system leaks to the receiving circuit system because the oscillation frequency is the same as the tuning frequency of the receiving circuit system, and interferes with the adjacent station from the antenna. , From the reception signal input side of the mixers 18, 19. In the mixer, the local oscillation signals are mixed with each other, that is, multiplication occurs, and a DC component is generated as shown in FIG. 40 (b), which becomes a DC offset component and gives an error to the demodulated signal. Therefore, the direct conversion receiving system in which the carrier frequency is selected as the local oscillation frequency is mainly used for the communication in the frequency modulation system relatively strong against the single frequency interference.

To summarize the above-mentioned problems, the first problem is that the receiving device requires many parts in order to secure good reception channel selectivity.

The second problem is that many parts, which are the first problem, cause large power consumption.

The third problem is that the digitization of signal processing consumes power several times that of analog processing.

The fourth problem is that the conventional digital filter requires complicated calculations and consumes a large amount of power.

The fifth problem is A / D for signal digitization.
That is, the converter requires a large input signal amplitude.

The sixth problem is that in the direct conversion reception system in which the local oscillation signal is equal to the carrier frequency of the received signal, the local oscillation signal interferes with the adjacent station from the antenna, or a DC offset occurs and an error occurs in the demodulated signal. give.

In order to solve the above six problems found in the conventional receiving apparatus, the present invention reduces the high frequency circuit portion, and occupies a high power consumption element, an unstable operation element, a manufacturing cost, and an internal high frequency circuit. It is an object of the present invention to provide a receiving device in which the space to be used is reduced.

[0027]

In order to solve the above-mentioned problems, the invention of claim 1 is such that the carrier frequencies are arranged in channels at equal frequency intervals or in a frequency arrangement close thereto.
A receiver for a wireless system using quadrature modulation or a similar modulation method, which receives a reception signal including a reception desired channel signal, and receives the received signal at the upper or lower end of the band of the desired reception channel or a boundary with a corresponding adjacent channel. Means for selectively frequency-converting a frequency range of up to approximately three channels above and below the boundary frequency into an intermediate frequency, and a bandwidth of a desired reception channel or a half of a channel interval frequency of a corresponding wireless system. A means for sampling at a frequency 16 times the frequency, a means for extracting a quadrature component in phase from the sampling output, and a signal for a desired reception channel are extracted from the positive phase axis signal component and the quadrature phase axis signal component. And means.

Further, the invention according to claim 2 is a receiving apparatus for a radio system using orthogonal modulation or a modulation system similar to this, in which carrier frequencies are arranged in channels at equal frequency intervals or in frequencies close thereto. In addition, the reception signal including the reception desired channel signal is received, and the frequency at the upper end or the lower end of the band of the desired reception channel or the boundary with the corresponding adjacent channel is centered around the boundary frequency, and the frequency range up to about three channels is provided. Means for selectively frequency converting to the DC region and 1/2 of the bandwidth of the desired reception channel or the channel interval frequency of the corresponding wireless system
Means for sampling at 16 times the frequency of
It is characterized by comprising means for extracting a quadrature component in phase from the sampling output and means for extracting a signal of a desired reception channel from the positive phase axis signal component and the quadrature phase axis signal component.

According to a third aspect of the present invention, in the first aspect of the present invention, the received signal including the desired reception channel signal is received and the frequency at the upper or lower end of the band of the desired reception channel or at the boundary with the corresponding adjacent channel is set. A frequency converter having an intermediate frequency, an intermediate frequency stage which receives a frequency conversion output from the frequency converter and which has a pass band in a frequency range up to about three channels around the intermediate frequency, and an output of the intermediate frequency stage. Bandwidth of receiving and receiving desired channel 1
6 times or 8 of the channel spacing frequency of the corresponding wireless system
A sample-and-hold circuit that samples at twice the frequency, a Hilbert converter that extracts the quadrature component on the phase from the sampling output and generates the positive phase axis signal component and the quadrature phase axis signal component, and the received signal positive A complex coefficient filter having a function of receiving a phase axis signal component and a quadrature phase axis signal component to remove adjacent upper and lower three channels adjacent to a desired channel signal, and two phase equalizers individually receiving the outputs thereof It is characterized in that the signal of the desired reception channel is extracted from the receiver and two low-pass filters that receive their respective outputs.

According to a fourth aspect of the present invention, in the second aspect of the present invention, the received signal including the desired reception channel signal is received and the frequency at the upper or lower end of the band of the desired reception channel or at the boundary with the corresponding adjacent channel is set. A frequency converter having a direct current, that is, a zero frequency, a low frequency stage that receives a frequency conversion output from this frequency converter, and has a pass band in a frequency range of up to about three positive and negative channels centering on the direct current, that is, a zero frequency, and a low frequency stage. A sample and hold circuit that receives the output of the wave stage and samples at a frequency 16 times the bandwidth of the desired reception channel or 8 times the channel interval frequency of the corresponding wireless system, and extracts the quadrature component in phase from the sampling output Hilbert transformer that generates a positive-phase axis signal component and a quadrature-phase axis signal component, and its received signal positive-phase axis signal And a quadrature phase axis signal component, the complex coefficient filter having a function of removing adjacent upper and lower three channels adjacent to the desired channel signal, and two phase equalizers individually receiving the outputs thereof, It is characterized in that a signal of a desired reception channel is extracted from two low-pass filters that receive their respective outputs.

Further, in the invention described in claim 5, in the invention described in any one of claims 1 to 4, thinning processing is performed on the orthogonal signals of the desired reception channels extracted from the two low-pass filters. And an image suppression type frequency conversion circuit for removing the offset frequency by receiving the two outputs thereof.

According to a sixth aspect of the present invention, in the invention according to any one of the first to fourth aspects, an orthogonal signal including a desired reception channel extracted from the two equalizers is used. It is characterized by including an averaging circuit for performing averaging processing and an image suppression type frequency conversion circuit for removing the offset frequency by receiving the two outputs thereof.

The invention according to claim 7 of the present invention is intended for a radio system using a quadrature modulation or a modulation system similar to this, in which carrier frequencies are arranged in channels at equal frequency intervals or in frequencies close thereto. A receiving device for receiving a reception signal including a reception desired channel signal, and a frequency of a boundary between an upper end or a lower end of a band of the reception desired channel or a corresponding adjacent channel is about 12 channels above and below the boundary frequency. Means for selectively frequency converting the frequency range to the intermediate frequency or DC region,
Means for sampling at a frequency that is 64 times the frequency of the bandwidth of the desired reception channel or 1/2 the channel interval frequency of the corresponding wireless system, means for extracting the quadrature component on the phase from the sampling output, and its positive phase A means for extracting a signal of 4 channels including a desired reception channel from the axis signal component and the quadrature phase axis signal component by removing other adjacent channels, and 4 channels including the extracted desired reception channel A means for extracting only the desired channel for reception by removing adjacent channels other than the desired channel for reception by using a bandwidth or a frequency 16 times the frequency of 1/2 of the channel interval frequency of the corresponding wireless system as a sampling frequency. Is characterized by.

According to the invention described in claim 8, in the invention described in claim 7, the carrier frequencies are arranged in channels at equal frequency intervals or in a frequency arrangement close to that.
A receiver for a wireless system using quadrature modulation or a similar modulation method, which receives a reception signal including a reception desired channel signal, and receives the received signal at the upper or lower end of the band of the desired reception channel or a boundary with a corresponding adjacent channel. Means for selectively frequency-converting the frequency of up to approximately 12 channels above and below the boundary frequency into an intermediate frequency or a DC region, and 1 of the bandwidth of the desired reception channel or the channel interval frequency of the corresponding wireless system. / 2
And a Hilbert converter that extracts a quadrature component on the phase from the sampling output and generates a positive-phase axis signal component and a quadrature-phase axis signal component from the sampling output. A second complex coefficient filter having a function of receiving the reception signal positive phase axis signal component and the quadrature phase axis signal component and removing all but the upper or lower three adjacent channels adjacent to the desired channel signal; Two second phase equalizers for individually receiving the outputs, two second low-pass filters for receiving the respective outputs, and a second decimation circuit for thinning the outputs by 1/4, Receiving the received signal positive-phase axis signal component and quadrature-phase axis signal component, the upper and lower two adjacent channels adjacent to the desired channel signal are removed and the baseband signal band is reached. A first complex coefficient filter having a conversion function, two first phase equalizers individually receiving their outputs, two first low pass filters receiving their respective outputs, and their outputs It is characterized in that it is provided with a first thinning circuit for thinning out to 1/4 and an image suppression type frequency conversion circuit for removing an offset frequency.

The invention according to claim 9 is the invention according to claim 7, wherein orthogonal modulation or a modulation method similar to this is used, in which the carrier frequencies are arranged in channels at equal frequency intervals or a frequency arrangement close to that. A receiver for a wireless system which receives a received signal including a desired channel signal, and raises or lowers a frequency of a boundary between an upper end or a lower end of a band of the desired reception channel or a corresponding adjacent channel around the boundary frequency. A means for selectively frequency-converting the frequency range of up to about 12 channels into an intermediate frequency or a DC region, and a frequency 64 times the bandwidth of the desired reception channel or 1/2 the channel interval frequency of the corresponding wireless system. A sample and hold circuit for sampling and the quadrature component on the phase are extracted from the sampling output. A Hilbert transformer that generates a positive-phase axis signal component and a quadrature-phase axis signal component, and a reception signal that receives the positive-phase axis signal component and the quadrature-phase axis signal component. A second complex coefficient filter having a function of removing channels other than adjacent channels, two second phase equalizers individually receiving the outputs thereof, and two second phase equalizers receiving the outputs thereof and averaging them over 8 samples. The second averaging circuit and the received signal positive phase axis signal component and quadrature phase axis signal component are received to remove the upper or lower three adjacent channels adjacent to the desired channel signal, and to remove the baseband signal band. A first complex coefficient filter having the function of transforming the output into two, a first phase equalizer receiving the outputs individually, and two first phase equalizers receiving the outputs and averaging the outputs over eight samples. 1 of an averaging circuit, characterized by comprising an image suppression type frequency conversion circuit for eliminating an offset frequency, the.

According to a tenth aspect of the present invention, in the invention according to any one of the third, fourth, eighth and ninth aspects, the Hilbert converter is a buffer amplifier and an inverting amplifier each including a switched capacitor circuit. It is characterized by being configured with a switch.

The invention of claim 11 is the invention according to claim 3, claim 4, claim 8 or claim 9, wherein the absolute value of the coefficient in the complex coefficient filter is composed of only two types. It is characterized by having done.

The invention of claim 12 is the invention according to claim 3, 4, or 8, wherein each of the operational amplifiers necessary for the two equalizers is connected to the low-pass filter in the subsequent stage. -Characterized by sharing with each operational amplifier of the filter.

The thirteenth aspect of the present invention is characterized in that, in the twelfth aspect of the present invention, the low-pass filter is constituted by using a CCD to reduce the number of operational amplifiers.

[0040]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is a radio using orthogonal modulation or a similar modulation method in which carrier frequencies are arranged in channels at equal frequency intervals or in frequencies close thereto. A receiving device for a system, which receives a received signal including a desired channel signal, and determines a frequency at a boundary between an upper end or a lower end of a band of the desired channel or a boundary with a corresponding adjacent channel above and below the boundary frequency. Means for selectively frequency converting the frequency range of up to 3 channels to an intermediate frequency; means for sampling at a frequency 16 times the bandwidth of the desired reception channel or 1/2 the channel spacing frequency of the wireless system in question; Means for extracting the quadrature component on the phase from the sampling output, and the positive phase axis signal component and the quadrature phase axis signal component Obtained by a receiving apparatus characterized by comprising a means for extracting a signal et desired reception channel has the effect of removing the arithmetic of the once for adjacent channels of the upper and lower 3 channels.

The invention according to claim 2 of the present invention is intended for a radio system using orthogonal modulation or a similar modulation method, in which carrier frequencies are channel-allocated at equal frequency intervals or frequency allocations approximate thereto. A receiving device for receiving a reception signal including a reception desired channel signal, and setting a frequency at a boundary between an upper end or a lower end of a band of the desired reception channel or a boundary with a corresponding adjacent channel up to about 3 channels above and below the boundary frequency. Means for selectively converting the frequency range into the direct current region, means for sampling at a frequency 16 times the bandwidth of the desired reception channel or half the channel interval frequency of the corresponding wireless system, and the sampling output A means for extracting a quadrature component on the phase and a rare signal received from the positive phase axis signal component and the quadrature phase axis signal component. Obtained by a receiving apparatus characterized by comprising a means for extracting a channel signal has the effect of removing the arithmetic of the once for adjacent channels of the upper and lower 3 channels.

According to a third aspect of the present invention, in the first aspect of the invention, the received signal including the desired reception channel signal is received, and the upper or lower end of the band of the desired reception channel or the boundary with the corresponding adjacent channel. Of the intermediate frequency, the intermediate frequency stage which receives the frequency conversion output from this frequency converter, and which has the pass band in the frequency range of up to about three channels up and down about the intermediate frequency, and this intermediate frequency stage And a sampling and holding circuit that samples the output at a frequency 16 times the bandwidth of the desired reception channel or 8 times the channel interval frequency of the corresponding wireless system, and extracts the quadrature component in phase from the sampling output. Hilbert transformer that generates a phase axis signal component and a quadrature phase axis signal component, and a received signal positive phase axis signal component and a quadrature phase A complex coefficient filter having a function of receiving the signal component and removing adjacent channels of upper and lower three channels adjacent to the desired channel signal, two phase equalizers individually receiving the outputs thereof, and the respective outputs thereof. A receiving device characterized by extracting a signal of a desired reception channel from two low-pass filters to be received,
It has an effect of realizing an orthogonal filter function by a complex coefficient filter.

The invention according to claim 4 of the present invention is
In a second aspect of the present invention, a frequency converter that receives a reception signal including a reception desired channel signal and sets the frequency at the upper or lower end of the band of the desired reception channel or the boundary with the corresponding adjacent channel to direct current, that is, zero frequency, A low-frequency stage that receives the frequency-converted output from the frequency converter and that has a pass band in the frequency range of positive or negative about 3 channels centering on a direct current, that is, zero frequency, and the output of this low-frequency stage, A sample and hold circuit that samples at a frequency 16 times or 8 times the channel interval frequency of the corresponding wireless system, and a quadrature component on the phase is extracted from the sampling output, and a positive phase axis signal component and a quadrature phase axis signal component are extracted. A Hilbert transformer that generates a signal and its received signal A complex coefficient filter having a function of removing adjacent upper and lower three channels adjacent to a channel signal, two phase equalizers individually receiving their outputs, and two low pass filters receiving their respective outputs. The receiving device is characterized by extracting a signal of a desired reception channel from and, and removing the adjacent channel of each of the upper and lower three channels by one calculation and realizing a quadrature filter function by a complex coefficient filter. Has the effect of

According to a fifth aspect of the present invention, in the invention according to any one of the first to fourth aspects, the orthogonal signals of the desired reception channels extracted from the two low-pass filters are respectively received. A thinning circuit for performing a thinning process and an image suppression type frequency conversion circuit for removing an offset frequency by receiving two outputs of the thinning circuit are provided. The thinning process and the offset frequency are removed. By performing the above, there is an effect that the desired reception channel can be accurately extracted.

According to a sixth aspect of the present invention, in the invention according to any one of the first to fourth aspects, an orthogonal signal including a desired reception channel extracted from the two equalizers is used. An averaging circuit for performing averaging processing, and an image suppression type frequency conversion circuit for removing offset frequencies by receiving the two outputs of the averaging circuit. By removing the offset frequency, the desired channel can be accurately extracted.

The invention according to claim 7 of the present invention is intended for a radio system using orthogonal modulation or a modulation system similar to this, in which carrier frequencies are arranged in channels at equal frequency intervals or in frequencies close to the channels. A receiving device for receiving a reception signal including a reception desired channel signal, and a frequency of a boundary between an upper end or a lower end of a band of the reception desired channel or a corresponding adjacent channel is about 12 channels above and below the boundary frequency. Means for selectively frequency converting the frequency range to the intermediate frequency or DC region,
Means for sampling at a frequency that is 64 times the frequency of the bandwidth of the desired reception channel or 1/2 the channel interval frequency of the corresponding wireless system, means for extracting the quadrature component on the phase from the sampling output, and its positive phase A means for extracting a signal of 4 channels including a desired reception channel from the axis signal component and the quadrature phase axis signal component by removing other adjacent channels, and 4 channels including the extracted desired reception channel A means for extracting only the desired channel for reception by removing adjacent channels other than the desired channel for reception by using a bandwidth or a frequency 16 times the frequency of 1/2 of the channel interval frequency of the corresponding wireless system as a sampling frequency. This is a receiver characterized by the fact that even if the band of adjacent channels including the desired channel is widened, It has an effect of capable of extracting the channel.

The invention according to claim 8 of the present invention is intended for a radio system using quadrature modulation or a similar modulation method, in which carrier frequencies are arranged in channels at equal frequency intervals or in frequencies close thereto. A receiving device for receiving a reception signal including a reception desired channel signal, and a frequency of a boundary between an upper end or a lower end of a band of the reception desired channel or a corresponding adjacent channel is about 12 channels above and below the boundary frequency. Means for selectively frequency converting the frequency range to the intermediate frequency or DC region,
A sample-and-hold circuit that samples at a frequency 64 times the bandwidth of the desired reception channel or half the channel interval frequency of the corresponding radio system, and the quadrature component on the phase is extracted from the sampling output and its positive phase is extracted. A Hilbert transformer that generates an axis signal component and a quadrature phase axis signal component, and a reception signal that receives the positive phase axis signal component and the quadrature phase axis signal component, and is adjacent to a desired channel signal, except for adjacent two channels above and below Second complex coefficient filter having the function of removing the
Second phase equalizer, two second low-pass filters receiving their respective outputs, and 1/4 receiving their outputs
A second thinning circuit for thinning out the received signal, the reception signal of the positive phase axis signal component and the quadrature phase axis signal component are received to remove adjacent channels of upper and lower two channels adjacent to the desired channel signal and convert to a baseband signal band. A first complex coefficient filter having the function of
First phase equalizer, two first low-pass filters receiving their respective outputs, and a quarter of the outputs
A receiving device characterized by comprising a first thinning circuit for thinning out a signal and an image suppression type frequency conversion circuit for removing an offset frequency, which is desired by cascading basic signal processing blocks. It has an effect of removing the upper or lower three adjacent channels adjacent to the channel signal and converting into the baseband signal band.

The invention according to claim 9 of the present invention is
In a seventh aspect of the present invention, there is provided a receiver for a radio system using orthogonal modulation or a similar modulation method, in which carrier frequencies are channel-allocated at equal frequency intervals or frequency allocations close thereto. , A reception signal including a reception desired channel signal is received, and a frequency at the upper or lower end of the band of the desired reception channel or a boundary with the corresponding adjacent channel is selectively selected within a frequency range of approximately 12 channels up and down about the boundary frequency. A means for frequency conversion into an intermediate frequency or a DC region, a sample and hold circuit for sampling at a frequency of 64 times a bandwidth of a desired reception channel or a half of a channel interval frequency of a corresponding wireless system, and a sampling output thereof. Extracts the quadrature component on the phase and extracts its positive phase axis signal component and quadrature phase axis signal component A Hilbert transformer for generating a signal, and a function of receiving the received signal positive-phase axis signal component and quadrature-phase axis signal component and removing all but the upper or lower three adjacent channels adjacent to the desired channel signal. Two
Complex coefficient filters, two second phase equalizers for individually receiving the outputs, two second averaging circuits for averaging the outputs over 8 samples, and the received signal positive phase A first complex coefficient filter having a function of receiving an axis signal component and a quadrature phase axis signal component, removing adjacent channels of upper or lower three channels adjacent to a desired channel signal, and converting into a baseband signal band; , Two first phase equalizers receiving their outputs individually, and two first phase equalizers receiving their outputs and averaging over 8 samples
The averaging circuit and the image suppression type frequency conversion circuit for removing the offset frequency are provided in the receiving device, and the desired channel signal is converted into the desired channel signal by cascading the basic signal processing blocks. It has an effect of removing the adjacent three adjacent channels on the upper side or the lower side and converting into the baseband signal band.

According to a tenth aspect of the present invention, in the invention according to any one of the third, fourth, eighth and ninth aspects, the Hilbert converter is a buffer composed of a switched capacitor circuit. The receiving device is characterized by being composed of an amplifier, an inverting amplifier, and a switch, and has an operation of realizing simple synchronization control and low power consumption.

The invention according to claim 11 of the present invention is the invention according to claim 3, claim 4, claim 8 or claim 9, wherein there are two types of absolute values of the coefficients in the complex coefficient filter. It is a receiver characterized by being configured only with the function of improving the easiness of design and the production quality of the circuit device and stabilizing the operation by configuring the circuit with limited fixed value circuit elements. Have.

According to a twelfth aspect of the present invention, in the invention according to any one of the third, fourth and eighth aspects, each operational amplifier required for the two equalizers is provided in a subsequent stage. The receiver is characterized by being shared with each of the operational amplifiers of the low-pass filter described above, and the circuit is configured with limited circuit elements to reduce the power consumption and improve the production quality of the circuit device and stabilize the operation. It has the action of causing.

According to a thirteenth aspect of the present invention, the receiving device is characterized in that, in the eleventh aspect of the present invention, the low-pass filter is constituted by using a CCD and the number of operational amplifiers is reduced. Thus, it has the effects of promoting lower power consumption, improving the ease of design and the production quality of circuit devices, and stabilizing the operation.

(First Embodiment) FIG. 1 shows a configuration example of a first embodiment of the present invention. The received signal 1 obtained from the antenna is supplied to the high frequency amplifier 2 and amplified. The output of the first band-pass filter 3 extracts only all channel signals of the corresponding communication system from other wireless signals. This output is supplied to the frequency converter 4 and frequency-converted at the local oscillation frequency f _LO from the local oscillator 5.

The output of the frequency converter 4 is blocked by the second band-pass filter 6 to prevent the image signal generated in the frequency converter 4 and at the same time obtain a channel filter effect of passing only the desired wave. This output is supplied to the AGC amplifier 7 and is output with a predetermined signal strength. This output is supplied to the sample and hold circuit 8 and controlled by the sampling clock 9 to perform sample and hold. The sampling frequency of the sample and hold is the second
It is set to an integral fraction of the frequency equal to the pass band width defined by the band filter 6 of FIG. In other words, the sampling in the sample and hold circuit uses the band limiting sampling theorem. The discretized signal of the received signal thus obtained is supplied to the I-axis component separation circuit 10 and the Q-axis component separation circuit 11, respectively.

This sample output is 1 in the I-axis component separation circuit 10.
By taking the clock every other clock, the Q-axis component separation circuit 11 takes the sample output at the time not taken by the I-axis component separation circuit 10, and inverts the polarity of the sample output every other I-axis and Q-axis. The transformation is performed to form the two orthogonal components on the phase plane. These two signals are supplied to the complex coefficient filter 12. The complex coefficient filter 12 removes unnecessary adjacent channel signal groups, and supplies the quadrature outputs 13 and 14 to the I-axis equalizer 15 and the Q-axis equalizer 16, respectively. Here, the phase delay is equalized, and the outputs 17 and 18 thereof are provided to the I-axis low-pass filter 19 and the Q-axis low-pass filter 20, respectively, and the high frequency unnecessary residual components are removed.

Further, if necessary, level conversion is performed and digital signal level outputs 21 and 22 are supplied to the digital system. The operation control after the sample hold is performed by various clock signals supplied from the clock signal generation and control circuit 23.

The processing relationship from the frequency axis up to the frequency conversion circuit in the first embodiment of FIG. 1 will be described with reference to FIG.

FIG. 2A shows an example of a frequency band used by the target communication system, an arrangement of communication channels within the communication band, and one of them as a desired wave channel. The frequency regions above and below the communication band show the situation in which they are occupied by other communication signal groups.

FIG. 2B shows a situation in which the target communication band is extracted from another communication signal group by the first bandpass filter 3 of FIG.

In FIG. 2C, the communication band of interest is subjected to frequency conversion by the frequency converter 4 of FIG. 1 and moved to a lower frequency band, and the communication of interest is further processed by the second band pass filter 6. The band for use is band-limited within the intermediate frequency bandwidth f _FB centered at the lower end of the band of the desired wave channel.

FIG. 2D shows the above-mentioned intermediate frequency bandwidth f _FB.
It shows a state in which a signal having a band-limited state is subjected to a frequency conversion action at the same time as sampling by the sample and hold circuit 8 and moved to the vicinity of the baseband frequency. Here, fs represents the frequency of the sampling clock 9, and in the present invention, the intermediate frequency bandwidth f _FB is within 6 times the channel interval width. At this time, the sampling frequency is either the baseband bandwidth frequency fb or the channel interval frequency fw.
Set the frequency to 16 times 1/2 or an even multiple of 16 times.

In conventional sampling, usually 1
By the second sampling theorem, the center frequency f _IF of 2
It is set to double or more. In the present invention, the lowest sampling frequency fs can be made twice the bandwidth f _FB of the intermediate frequency band by using the sampling theorem for the signal with band limitation.

In FIG. 2D, as a result of down-conversion by sampling, the desired wave channel moves to a position where the lower end of the desired wave channel is placed near the DC point of the baseband region, and the frequency axis positive / negative is separated from the DC axis. A spectrum with the same number of channels arranged symmetrically is obtained.

The processing relationship from the frequency conversion circuit in the first embodiment of FIG. 1 to the sampling and thereafter as seen from the frequency axis will be described with reference to FIG.

FIG. 3 (a) is the same as that shown in FIG. 2 (c), and the target communication band is subjected to frequency conversion by the frequency converter 4 of FIG. 1 and moved to a lower frequency band. In addition, the second bandpass filter 6 indicates that the target communication band is band-limited within the intermediate frequency bandwidth f _FB centered on the lower end of the band of the desired wave channel.

FIG. 3B shows the relationship between the sampling frequency fs of the sample and hold circuit and the intermediate frequency center frequency (fc-f _LO ). The sampling frequency fs is the intermediate frequency center frequency (fc-f _LO ). It is necessary to have a relationship of integer division frequencies of 2 or more.

FIG. 3C shows an intermediate frequency bandwidth f on the multiple wave of the sampling frequency including the frequency zero of FIG. 3B.
It is shown that the spectrum in which the channel group of _FB is superimposed is obtained. As is apparent from FIG. 3C, the intermediate frequency center frequency (fc-f _LO ) is set to a frequency higher than the value of the intermediate frequency bandwidth f _FB so that aliasing does not occur in sampling.

FIG. 3 (d) shows the characteristics of the adjacent channel elimination filter composed of the complex coefficient filter, the phase equalizer and the delay type low pass filter according to the present invention on the channel arrangement. It shows that the zeros of the filter are located on each center frequency of the adjacent channel.

FIG. 3E schematically shows the adjacent channel removal effect by the channel characteristic of FIG. 3D.

(Second Embodiment) FIG. 4 shows a configuration example of a second embodiment of the present invention. The received signal 1 obtained from the antenna is supplied to the high frequency amplifier 2 and amplified. The output extracts all the channel signals of the corresponding communication system from other radio signals by the band pass filter 3. This output is supplied to the frequency converter 4 and frequency-converts the local oscillation frequency f _LO from the local oscillator 5 at the frequency of the boundary between the desired wave and the adjacent low channel.

The output of the frequency converter 4 is the low pass of the first stage.
The filter 6'blocks the image signal generated in the frequency converter 4, and at the same time obtains a channel filter effect of passing only the desired wave. This output is supplied to the AGC amplifier 7 and is output with a predetermined signal strength. This output is supplied to the sample and hold circuit 8 for sampling and
Controlled by clock 9, sampling and holding is performed.

The sampling frequency of the sample and hold is set to an integral fraction of the frequency equal to twice the pass band width defined by the low pass filter 6'of the first stage. That is, the sampling in the sample and hold circuit uses the primary sampling theorem. The discretized signal of the received signal thus obtained is supplied to the I-axis component separation circuit 10 and the Q-axis component separation circuit 11, respectively.

This sample output is 1 in the I-axis component separation circuit 10.
By taking the clock every other clock, the Q-axis component separation circuit 11 takes the sample output at the time not taken by the I-axis component separation circuit 10, and inverts the polarity of the sample output every other I-axis and Q-axis. The transformation is performed to form the two orthogonal components on the phase plane.

The two signals are supplied to the complex coefficient filter 12. The complex coefficient filter 12 removes unnecessary adjacent channel signal groups, and outputs their quadrature outputs 13 and 14 respectively to the I-axis equalizer.
15 and Q-axis equalizer 16 are provided. Here, the phase delay is equalized, and the outputs 17 and 18 are respectively set to the I-axis low-pass filter.
19 and Q-axis low-pass filter 20 to remove high frequency unnecessary residual components.

Further, if necessary, level conversion is performed and the digital signal level outputs 21 and 22 are supplied to the digital system. The operation control after the sample and hold is all performed by various clock signals supplied from the clock signal generation and control circuit 23 '.

The processing relationship from the frequency axis up to the frequency conversion circuit in the second embodiment of FIG. 4 will be described with reference to FIG.

FIG. 5A shows an example of a frequency band used by the target communication system, an arrangement of communication channels within the communication band, and one of them as a desired wave channel. The frequency regions above and below the communication band show the situation in which they are occupied by other communication signal groups.

FIG. 5B shows a situation in which the target communication band is extracted from another communication signal group by the bandpass filter 3 of FIG.

FIG. 5 (c) shows that the target communication band is subjected to frequency conversion by the frequency converter 4 of FIG. 4 and moved to a lower frequency band, and the target communication band is further processed by the low pass filter 6'of the first stage. The band for use is band-limited within the intermediate frequency bandwidth f _FB centered at the lower end of the band of the desired wave channel.

FIG. 5D shows the above-mentioned intermediate frequency bandwidth f _FB.
It shows a state in which a signal having a band-limited state is subjected to a frequency conversion action at the same time as sampling by the sample and hold circuit 8 and moved to the vicinity of the baseband frequency. Here, fs indicates the frequency of the sampling clock 9, and in the present invention, the intermediate frequency bandwidth f _{FB is set} to 6 of the channel interval width.
Within 2 times. At this time, the sampling frequency is 1 of the baseband bandwidth frequency fb or the channel interval frequency fw.
Set to a frequency that is 16 times 1/2 or an even multiple of 16 times. In the conventional sampling, it is usually set to twice or more the intermediate frequency center frequency f _{IF according to} the primary sampling theorem.

In the present invention, the lowest sampling frequency fs can be made twice the bandwidth f _FB of the intermediate frequency band by using the sampling theorem for the band-limited signal.

In FIG. 5D, as a result of down-conversion by sampling, the desired wave channel moves to the position where the lower end of the desired wave channel is placed near the DC point in the baseband region, and the frequency axis is separated by the DC axis. A spectrum with the same number of positive and negative channels arranged symmetrically is obtained.

The processing relationship from the frequency conversion circuit according to the second embodiment shown in FIG. 4 to the sampling and thereafter as viewed from the frequency axis will be described with reference to FIG.

FIG. 6 (a) is the same as that shown in FIG. 5 (b), and FIG. 6 (c) is the same as that shown in FIG. 5 (c). The target communication band undergoes frequency conversion by the frequency converter 4 and moves to a lower frequency band,
Further, the target communication band is band-limited by the first-stage low-pass filter 6 ′ within the baseband frequency region f _BB in which the lower end of the band of the desired wave channel is near DC.

FIG. 6B shows the local oscillation frequency f _LO, that is,
It shows the relationship between the value of (desired channel frequency fc-channel width / 2) and the sampling frequency fs of the sample and hold circuit. The sampling frequency fs is the baseband frequency region in order to prevent aliasing during sampling. It must be more than twice f _BB .

FIG. 6C shows that a spectrum in which the channel group of the baseband frequency region f _BB is superposed on the multiple wave of the sampling frequency including the frequency zero of FIG. 6B is obtained. Note that there is generally no restriction between the local oscillation frequency f _LO and the sampling frequency fs.

FIG. 6 (d) shows, on the channel arrangement, the characteristics of the adjacent channel elimination filter composed of the complex coefficient filter, the phase equalizer and the delay type low pass filter according to the present invention. It shows that the zeros of the filter are located on each center frequency of the adjacent channel.

FIG. 6E schematically shows the effect of removing the adjacent channel due to the channel characteristic of FIG. 6D.

(Third Embodiment) FIG. 7 shows a configuration example of a third embodiment of the present invention. FIG. 7 shows the first configuration example of the second embodiment of the present invention. In FIG. 4, the I-axis thinning circuit 24, the Q-axis thinning circuit 25, and the image suppression type frequency conversion circuit 26 are mainly I-axis thinning circuits. Low-pass filter 19 and digital system 21 'or Q-axis low-pass filter 2
It is inserted between 0 and the digital system 22 '. Relatedly, the control system of the clock signal generation and control circuit 23 'is increased.

The received signal 1 obtained from the antenna is supplied to the high frequency amplifier 2 and amplified. The output extracts all the channel signals of the corresponding communication system from other radio signals by the band pass filter 3. This output is supplied to the frequency converter 4 and the local oscillation frequency from the local oscillator 5 is supplied.
The frequency of f _LO is converted at the frequency of the boundary between the desired wave and the low adjacent channel.

The output of the frequency converter 4 is the low pass of the first stage.
The filter 6'blocks the image signal generated in the frequency converter 4, and at the same time obtains a channel filter effect of passing only the desired wave. This output is supplied to the AGC amplifier 7 and is output with a predetermined signal strength. This output is supplied to the sample and hold circuit 8 for sampling and
Controlled by clock 9, sampling and holding is performed.

The sampling frequency of the sample and hold is set to an integral fraction of the frequency equal to twice the pass band width defined by the low pass filter 6'of the first stage. That is, the sampling in the sample and hold circuit uses the primary sampling theorem. The discretized signal of the received signal thus obtained is supplied to the I-axis component separation circuit 10 and the Q-axis component separation circuit 11, respectively.

This sample output is 1 in the I-axis component separation circuit 10.
By taking the clock every other clock, the Q-axis component separation circuit 11 takes the sample output at the time not taken by the I-axis component separation circuit 10, and inverts the polarity of the sample output every other I-axis and Q-axis. The transformation is performed to form the two orthogonal components on the phase plane.

These two signals are supplied to the complex coefficient filter 12. The complex coefficient filter 12 removes unnecessary adjacent channel signal groups, and outputs their quadrature outputs 13 and 14 respectively to the I-axis equalizer.
15 and Q-axis equalizer 16 are provided. Here, the phase delay is equalized, and the outputs 17 and 18 are respectively set to the I-axis low-pass filter.
19 and Q-axis low-pass filter 20 to remove high frequency unnecessary residual components.

The outputs of the I-axis low-pass filter 19 and the Q-axis low-pass filter 20 are the I-axis thinning circuit 24 and Q, respectively.
It is input to the axis thinning circuit 25. And the I-axis thinning circuit
The outputs of 24 and the Q-axis thinning circuit 25 are input to the image suppression type frequency conversion circuit 26, and the output thereof is the digital output 2
1'and 22 'are provided to the digital system.

The processing relationship seen from the frequency axis up to the frequency conversion circuit and the processing relationship seen from the frequency axis from the frequency conversion circuit to the sampling and thereafter in the third embodiment of FIG. 7 are the same as those of the second embodiment of FIG. The description is omitted because it is the same as FIG. 5 that illustrates the processing relationship viewed from the frequency axis up to the frequency conversion circuit and FIG. 6 that illustrates the processing relationship viewed from the frequency axis from the frequency conversion circuit to the sampling and subsequent steps in this mode.

The operation of the thinning circuit will be described with reference to FIG. FIG. 8A is the same as the diagram showing the filtering position in FIG. 6D and shows the functions of the I-axis thinning circuit 24 and the Q-axis thinning circuit 25 shown in FIG.

FIG. 8B shows a complex coefficient filter 12, an I-axis equalizer 15, a Q-axis equalizer 16, an I-axis low-pass filter 19 and a Q-axis.
It is shown that the desired wave can be generally extracted by the characteristics of the adjacent channel elimination filter including the axial low-pass filter 20. However, for each harmonic of the sampling frequency fs, the same spectrum as the residual spectrum of the desired wave moved to the DC region and the adjacent channel signal group is repeated.

Here, in FIG. 8C, the data is thinned to 1/2, but the sampling frequency fs', which is 1/2 of the original sampling frequency fs, has a harmonic interval of 1 /. 2 and the spectrum is doubled. Ie 16
In the double oversampling, 8 channels existed between the harmonics of the sampling frequency, but the number of channels was reduced to 1/2 to 4 channels, and the signal residuals of different channels overlap at each channel position.

In FIG. 8D, the data is further reduced to 1/2.
8 (e), the data is further thinned to 1/2, and from FIG. 8 (b), 1/8 is thinned. As a result, the desired wave spectrum repeatedly appears at the channel intervals. At this time, the sampling frequency fs '''is oversampled by a factor of 2 with respect to the desired wave, which means that the sampling frequency fs''' is lowered to a state where the minimum standard of the sampling theorem is satisfied.

In FIG. 8E, the signals of the adjacent channel groups are folded and folded in the desired wave spectrum, but basically, the complex coefficient filter 12 and the I-axis equalizer 15 are used.
The adjacent channel signal is greatly attenuated due to the characteristics of the adjacent channel elimination filter including the Q axis equalizer 16, the I axis low pass filter 19 and the Q axis low pass filter 20.

Therefore, in FIG. 8E, it may be considered that the desired wave is sampled and extracted at a frequency twice the desired wave. However, the frequency offset from DC is still present, and the output is input to the image suppression type frequency conversion circuit 26 in order to remove this offset frequency.
The thinning circuit is a sample and hold circuit or a transfer circuit that performs sampling only once every eight clocks, and its specific circuit is well known, so the description thereof is omitted here.

Thus, as is clear from the description of the third embodiment, the complex coefficient filter 12, the I-axis equalizer 15 and the Q
A desired wave can be extracted by the characteristics of the adjacent channel elimination filter including the axial equalizer 16, the I-axis low-pass filter 19 and the Q-axis low-pass filter 20.

(Fourth Embodiment) FIG. 9 shows an example of the configuration of the fourth embodiment of the present invention. FIG. 9 shows the first configuration example of the second embodiment of the present invention. In FIG. 4, the I-axis averaging circuit 27, the Q-axis averaging circuit 28, and the image suppression type frequency conversion circuit 26 are mainly used. It is inserted between the I-axis equalizer 15 and the digital system 21 'or between the Q-axis equalizer 16 and the digital system 22'. Relatedly, the control system of the clock signal generation and control circuit 23 'is increased.

The received signal 1 obtained from the antenna is supplied to the high frequency amplifier 2 and amplified. The output extracts all the channel signals of the corresponding communication system from other radio signals by the band pass filter 3. This output is supplied to the frequency converter 4 and the local oscillation frequency f from the local oscillator 5 is output.
_{The LO} is frequency converted at the frequency of the boundary between the desired wave and the low adjacent channel.

The output of the frequency converter 4 is the low pass of the first stage.
The filter 6'blocks the image signal generated in the frequency converter 4, and at the same time obtains a channel filter effect of passing only the desired wave. This output is supplied to the AGC amplifier 7 and is output with a predetermined signal strength. This output is supplied to the sample and hold circuit 8 for sampling and
Controlled by clock 9, sampling and holding is performed.

The sampling frequency of the sample and hold is set to an integral fraction of the frequency equal to twice the pass band width defined by the low pass filter 6'in the first stage. That is, the sampling in the sample and hold circuit uses the primary sampling theorem. The discretized signal of the received signal thus obtained is supplied to the I-axis component separation circuit 10 and the Q-axis component separation circuit 11, respectively.

This sample output is set to 1 by the I-axis component separation circuit 10.
By taking the clock every other clock, the Q-axis component separation circuit 11 takes the sample output at the time not taken by the I-axis component separation circuit 10, and inverts the polarity of the sample output every other I-axis and Q-axis. The transformation is performed to form the two orthogonal components on the phase plane.

These two signals are supplied to the complex coefficient filter 12. The complex coefficient filter 12 removes unnecessary adjacent channel signal groups, and supplies the quadrature outputs 13 and 14 to the I-axis equalizer 15 and the Q-axis equalizer 16, respectively. Here, the phase delays are equalized and their outputs 17 and 18 are input to the I-axis averaging circuit 27 and the Q-axis averaging circuit 28, respectively. The outputs of the I-axis averaging circuit 27 and the Q-axis averaging circuit 28 are input to the image suppression type frequency conversion circuit 26, and the output is a digital output.
21 'and 22' are provided to the digital system.

The processing relationship viewed from the frequency axis up to the frequency conversion circuit and the processing relationship viewed from the frequency axis from the frequency conversion circuit to the sampling and thereafter in the fourth embodiment of FIG. 9 are the same as those in the second embodiment of FIG. The description is omitted because it is the same as FIG. 5 that illustrates the processing relationship viewed from the frequency axis up to the frequency conversion circuit and FIG. 6 that illustrates the processing relationship viewed from the frequency axis from the frequency conversion circuit to the sampling and subsequent steps in this mode.

The operation of the averaging circuit will be described with reference to FIG. FIG. 10A is the same as the diagram showing the filtering position of FIG. 6D, and shows the functions of the I-axis averaging circuit 27 and the Q-axis averaging circuit 28 shown in FIG.

FIG. 10 (b) shows the characteristics of the adjacent channel elimination filter including the complex coefficient filter 12, the I-axis equalizer 15, the Q-axis equalizer 16, the I-axis averaging circuit 27, and the Q-axis averaging circuit 28. Shows that the desired wave is almost extracted. However,
For each harmonic of the sampling frequency fs, the same spectrum as the residual spectrum of the desired wave and the adjacent channel signal group that have moved to the DC region is repeated.

Here, FIG. 10 (c) shows the data averaged over two sampling periods, but the sampling frequency f which is ½ of the original sampling frequency fs is obtained.
In s', the interval between harmonics becomes 1/2, and the spectrum repetition is doubled. That is, in 16-times oversampling, there were 8 channels between the harmonics of the sampling frequency, but there were 4 channels due to the averaging of 2 sections, and the signal residuals of different channels overlap at each channel position. .

In FIG. 10 (d), the data is further averaged, and from FIG. 10 (b), four periods are averaged. In FIG. 10E, the data is further averaged, and from FIG. 10B, the averaging is performed for 8 periods. As a result, the desired wave spectrum repeatedly appears at the channel intervals. At this time, the sampling frequency fs '''is oversampled by a factor of 2 with respect to the desired wave, which means that the sampling frequency fs''' is lowered to a state where the minimum standard of the sampling theorem is satisfied.

In FIG. 10 (e), it can be imagined that the signals of the adjacent channel groups are folded and convolved in the spectrum of the desired wave, but the folded adjacent channel component is attenuated by the low-pass filter effect by averaging. Has been done.

Therefore, in FIG. 10E, it can be considered that the desired wave is sampled and extracted at a frequency twice the desired wave. However, the frequency offset from DC is still present, and this output is input to the image suppression type frequency conversion circuit 26 in order to remove this offset frequency.

FIG. 11 shows a configuration example of a circuit for averaging 8 samples. Using 7 stages of delay means for both I axis and Q axis,
Averaged by connecting to the cascade and synthesizing all the inputs and outputs. Strictly speaking, it should be divided into 1/8, but we think that it is not necessary to actually divide it by allocating it to the constituent elements in the necessary amplification degree of the entire system.

Thus, as is clear from the description of the fourth embodiment, the complex coefficient filter 12, the I-axis equalizer 15 and the Q
A desired wave can be extracted by the characteristics of the adjacent channel elimination filter including the axis equalizer 16, the I-axis averaging circuit 27, and the Q-axis averaging circuit 28.

(Fifth Embodiment) FIGS. 12 and 13
Shows a configuration example of the fifth embodiment of the present invention. FIG. 12 mainly shows an I-axis component separation circuit of the configuration examples shown in the second and fourth embodiments of the present invention.
Between the 10 and the first complex coefficient filter 12, and between the Q axis component separation circuit 11 and the first complex coefficient filter 12, the second
Quadrant complex coefficient filter 112 which is a complex coefficient filter of
And an I-axis quadruple band equalizer 115 which is a second I-axis quadruple equalizer 115 and a Q-axis quadruple band equalizer 116 which is a second Q-axis equalizer and a second
The I-axis quadruple-range averaging circuit 127 which is the I-axis averaging circuit and the Q-axis quadruple-region averaging circuit 128 which is the second Q-axis averaging circuit are inserted, and FIG. Of the configuration examples shown in the first and third embodiments of the invention,
The second complex coefficient filter, which is 4 times, is mainly provided between the I-axis component separation circuit 10 and the first complex coefficient filter 12 and between the Q-axis component separation circuit 11 and the first complex coefficient filter 12. Band complex coefficient filter 112 and I-axis 4 which is a second I-axis equalizer
Double-pass equalizer 115, second Q-axis equalizer Q-axis quadruple-pass equalizer 116, and second I-axis low-pass filter I
Axis quadruple-range low-pass filter 119, second Q-axis low-pass filter Q-axis quadruple-range low-pass filter 120 and second I-axis thinning circuit I-axis quadruple-range thinning circuit
124 and a Q-axis quadruple-range thinning circuit 125, which is a second Q-axis thinning circuit, are inserted.

Then, by inserting the circuit means consisting of these complex coefficient filters, equalizers, averaging circuits or decimation circuits, the adjacent wave removing action by the 16 times oversampling as seen from the baseband frequency is reduced. Used heavily,
This is to remove 9 to 16 adjacent channel waves on each side by 16 × 4 or 64 times oversampling.

In FIG. 12, a sample from the antenna
The description of the structure and connection of the hold circuit 8 is the same as that described above, and will not be repeated. sample·
The hold circuit 8 is a clock signal generation and control circuit 23 '.
To 64 times oversampling required for oversampling
Upon receiving the clock 9, the received signal is sampled and held. The band-limited sampling theorem is used for sampling.

The discretized signal of the received signal thus obtained is supplied to the I-axis component separation circuit 10 and the Q-axis component separation circuit 11, respectively. Each output is a quadruple band complex coefficient filter 11
2 are supplied to 2 to remove upper and lower eight adjacent channel signals. The respective outputs 113 and 114 are respectively the I-axis quadruple band equalizer 115.
And the Q axis quadruple equalizer 116. Furthermore, an I-axis quadruple-area averaging circuit 127 and a Q-axis quadruple-area averaging circuit 128, respectively.
And is restored to the baseband output of the quadruple band including the desired wave.

The two outputs of the quadruple band baseband output thus obtained are supplied to the circuit means for extracting the original baseband signal described in the third to fourth embodiments. . That is, according to the fourth embodiment, the first complex coefficient filter 12 corresponding to 16 times oversampling, the first equalizers 15 and 16, the first averaging circuits 27 and 28, Image suppression type frequency conversion circuit 26
And the original baseband signal is extracted. According to the third embodiment, the first complex coefficient filter 12 corresponding to 16 times oversampling, the first equalizers 15 and 16, the first low-pass filters 19 and 20, The original baseband signal is extracted by being supplied to the first decimation circuits 24 and 25 and the image suppression type frequency conversion circuit 26.

FIG. 14 shows a concrete example of the configuration of the thinning circuit. The thinning circuit of FIG. 14 is a switch SW1 that receives an input.
A capacitor C1 for charging the input voltage, an inverting amplifier U6, a feedback capacitor C3, a switch SW2 for selectively connecting the input and output of the inverting amplifier U6, a capacitor C2 connected between the ground by the switch SW2, a sampling capacitor A first D-type flip-flop U1 receiving a clock signal a at a clock input CLK, a second D-type flip-flop U2 receiving a Q output thereof at a clock input, and a third D-type flip-flop receiving a Q output thereof at a clock input. U3 It is composed of an AND circuit U4 for inputting all the Q outputs and the sampling clock signal a.

The operation will be described with reference to FIG. 8 when the sampling clock signal a is received at the clock input
A sampling / hold circuit or a transfer circuit that samples only once at a clock, and is divided by 8 by a first D-type flip-flop U1, a second D-type flip-flop U2, and a third D-type flip-flop U3, AND circuit
The output of U4 becomes the high potential "H" only once every eight clocks when all the outputs and the sampling clock signal a have the high potential "H".

This output controls the switch SW1 to connect the input to the capacitor C2, and at the same time to switch SW2.
Connects capacitor C2 to the input of inverting amplifier U6. At this moment, the output of the inverting amplifier U6 continues its output state by the capacitor C2 storing the output state up to that point. The output of the AND circuit U4 returns to the low potential "L" when the time corresponding to one pulse width of the sampling clock signal elapses, so the switches SW1 and SW2 are connected to the previous state, but at this time, the capacitor C1 The input instantaneous voltage is charged, and the voltage of the inverting amplifier U6 is maintained at the instantaneous voltage of the input signal for the period of 15 sampling pulses thereafter. From the above, according to the circuit, the input signal is 1
It is clear that it is thinned out to / 8.

FIG. 15 shows the processing relationship seen from the frequency axis from the frequency conversion circuit in the fifth embodiment to sampling and thereafter. In FIG. 15A, the received signal group sampled and held by 64 times oversampling is
It is shown that four channels are treated as a virtual channel. FIG. 15 (b) shows FIG. 3 (d) or FIG.
This is the same as that shown in (d), and shows how it is connected to the subsequent processing.

Thus, as is clear from the description of the fifth embodiment, the desired wave is extracted by using the adjacent wave removing action by 16 times oversampling as seen from the baseband frequency in a double manner. be able to.

(Specific Example of Sample and Hold Circuit) FIG.
In order to reduce the load on the high-frequency circuit, the present invention performs wideband sampling as it is with one stage of down-conversion, and the subsequent signal processing is performed by the digitizing means. As a concrete example of the components, the sample and hold circuit is composed of an input buffer stage, a sampling gate and an output buffer. The received signal sampled and held is discretized and can be said to be an analog signal converted into data.

As for the sampling frequency, the band width of the intermediate frequency stage is widened in order to bear a part of the function of the adjacent channel removal filter so that the performance required for the filter of the intermediate frequency stage can be reduced. The bandwidth of the intermediate frequency stage corresponds to 6 channels including the desired channel when the adjacent channels are targeted for 5 channels in total.
Therefore, from the viewpoint of the bandwidth of the baseband signal, 16 times oversampling is performed.

Therefore, in order to enable the sample-and-hold circuit of FIG. 16 to over-sample the signal of the intermediate frequency stage more than twice, it is desirable to use a sampling gate made of a compound semiconductor such as GaAs. is there.

Further, if a low noise device such as a compound semiconductor such as GaAs is used, the sampling input / output does not have to be a large-amplitude signal required by the conventional A / D converter. Can be lowered to

The sampling clock signal CLK shown in FIG. 16 is assumed to be track-and-hold operated with a duty ratio of about 50% in order to reduce the switching idling current of the sampling gate. This method makes the settling time slightly demanding, but it is an unreasonable method as a whole.

(Specific Example of Quadrature Component Separation Circuit) I-axis component separation circuit 10 and Q-axis component separation circuit 11 in FIG. 1 or 4.
17 and a description of the operation thereof are shown in FIG.

In FIG. 17, the sample and hold output provided from the sample and hold circuit 8 is a switch SW.
21 and switch SW31. The inverting amplifier U1 is a shunt feedback type amplifier due to the negative feedback by the capacitor C3. When SW21 and SW22 are in the state shown in FIG. 17, the output is regulated by the terminal voltage due to the charge accumulated in the capacitor C1.

When SW21 and SW22 are inverted at time to, SW22 connects the capacitor C2, which was connected to the output end of the inverting amplifier U1 and was charged by the output voltage, to the input of the inverting amplifier U1. Therefore, when the capacitances of C2 and C3 are equal, the output potential of the inverting amplifier U1 is still kept at the same potential. During this time, SW21 connects the output of the sample and hold circuit to the capacitor C1, and the capacitor C1 is charged with a new sample value.

When SW21 and SW22 return to the state shown in FIG. 17 again at time t1, the output voltage of the sample and hold circuit 8 charged in the capacitor C1 is connected to the inverting amplifier U1.
If C1 and C3 have the same capacitance, a voltage equal to the new sample value is generated at the output of the inverting amplifier U1. That is, U1 acts as a buffer amplifier of the same polarity for the sample and hold circuit output.

The inverting amplifier U2 is a shunt feedback type amplifier due to the negative feedback by the capacitor C6. When SW32 and SW33 are in the state of FIG. 17, the output is regulated by the terminal voltage due to the electric charge accumulated in the capacitor C5. At this time, the capacitor C4 receives the output of the sample and hold circuit and is charged.

When SW31, SW32, and SW33 are inverted at time to, the capacitor C5, which has been connected to the input terminal of the inverting amplifier U2 and governs the output voltage up to that point, is switched by SW33 to the inverting amplifier U2.
Connect to the output of. At the same time, SW31 of the capacitor C4 is on the ground side and SW32 is connected to the input of the inverting amplifier U2. Therefore, when the capacitances of the capacitors C4 and C6 are equal, the output of the inverting amplifier U2 outputs the sample value voltage of the sample-hold circuit 8. Is generated. At the same time, the capacitor C5 is connected to the output of the inverting amplifier U2 by SW33, and is charged with the output voltage.

Therefore, at time t1, SW32 and SW33 are restored again.
17 returns to the state shown in FIG. 17, the voltage charged in the capacitor C5 is connected to the input terminal of the inverting amplifier U2, and the output potential is further maintained. That is, U2 acts as an amplifier that inverts the polarity of the sample and hold circuit output.

Next, the D-type flip-flop U3 receives the sampling clock signal as an input and outputs the output Q-bar to the D input to form a frequency divider. Similarly, the flip-flop U5 also constitutes a frequency divider, and the two-stage flip-flops are cascaded to perform frequency division by four.

The operation of this circuit will be described with reference to the signal operation example shown in the operation timing of FIG. sampling·
The clock signal arrives at times t1, t2, t3, t4, t5, t6, t7, t8, ... At equal time intervals. Its waveform is approximately
It is a square wave with a duty ratio of 50%. In response to this signal, the flip-flop U3 has an output Q of "1" at odd times of times t1, t3, t5, t7, .... Flip in response to this
The flop U4 sets its output Q to "1" at times t1, t5, t9, ....

On the other hand, the quadrature-modulated signal is converted into 2 in the phase space.
In order to separate them into two, it is sufficient to perform phase discrimination at the same frequency. Quadrature detection for this is equivalent to sampling shifted by π / 2. In order to generate this from a sequence of sample values that are sampled continuously and uniformly, cosine on the I-axis component side
The function and the sine function on the Q-axis component side may be multiplied for discrimination.

If this is handled at the sampling limit, it is considered that the sampling value corresponds to the sampling clock signal shown in FIG. 18A at a π / 2 interval. That is, FIG.
The highest frequency component is sampled by four pulses of the sampling clock signal shown in (a).

At this time, the cosine function for extracting the I-axis component for extracting the quadrature component and the sine function for extracting the Q-axis component may be set to a frequency corresponding to the highest frequency and simultaneously sampled. That is, in the sampling clock signal, the repetition frequency of this sampling clock
When a 1/4 sine wave is sampled, the cosine function is
+1 and +1 are sampled at the position shown in 8 (d), and the sine function is π / corresponding to one sample as shown in FIG. 18 (e).
+1 and -1 are sampled at positions delayed from the cosine function by 2 phases. Therefore, the I-axis side is shown in FIG.
It is obtained without reversing the polarity of the sample output at the position shown in (4), and the Q axis side is obtained by alternately reversing the polarity of the sample output at the position shown in FIG.

As described above, from the sample values obtained by one series of sampling, it is possible to obtain the same sampling output when sampling is performed as an orthogonal signal. To handle this as a circuit, see FIG.
When the I-axis multiplication coefficient of (d) and the Q-axis multiplication coefficient of FIG. 18 (e) are grouped in the same polarity section, a pair of 3 samples and 1 sample is obtained as shown in FIG. 18 (h). .

The OR gate U5, which receives the Q output of the flip-flop U3 and the Q output of the flip-flop U4, becomes the "H" state at the times t1, t2, t3 and t5, t6, t7 in FIG. Therefore, the output of the AND gate U6 which receives this output and the sampling clock signal a is as shown in FIG.
Produces the waveform of. On the other hand, the negative logic output of the OR gate U5 and the output of the AND gate U7 which receives the sampling clock signal a produce the waveform of FIG. 18 (i).

On the other hand, since the I-axis and the Q-axis are alternately output, this state is shown in FIG. 18 (j). From the above, the circuit of FIG.
The output of can be transformed into a quadrature signal output. In order to manage such a state change on the circuit, three types of gate circuits U5, U6, U7 of FIG. 17 using the outputs of the above-mentioned flip-flops are provided.

(Specific Example of Complex Coefficient Filter) FIG. 19 shows a specific example of the complex coefficient filter 12 of FIG. The complex coefficient filter 12 includes three filters having the same structure, that is, a complex coefficient filter I, a complex coefficient filter II, and a complex coefficient filter I.
Configure II in cascade. These three filters are respectively adjusted to the center frequencies of the three kinds of adjacent channel signals which are moved to the base band region and placed in the negative frequency region in FIG. 2 (d).

This state will be described with reference to FIG. 19 (a diagram showing the setting of the characteristic of the complex coefficient filter). FIG. 20 (A) is shown in FIG.
The same applies to each channel group in the communication band shown in (b). FIG. 20 (B) shows each signal transferred to the vicinity of the base band.
Equal to (d).

Here, the zeros of the complex coefficient filters I, II and III are respectively set to the center frequencies -fb and -3f of the adjacent channel signals.
Adjust to b and -5fb. FIG. 20 (B-1) schematically shows the case of only the complex coefficient filter I that removes the adjacent channel of the center frequency -fb. Similarly, FIG. 20 (B-2) is a diagram in which characteristics of complex coefficient filters I, II, and III that remove three types of adjacent channels having center frequencies −fb, −3fb, and −5fb are superimposed and schematically illustrated. FIG. 20C shows a case where the characteristics are combined, and actually shows that the adjacent channel signal in the positive region is also attenuated.

FIG. 21 is a diagram for explaining the operation of the complex coefficient filter. 21A shows the structure of the basic block of the complex coefficient filter, FIG. 21B shows the operation in the phase plane, and FIG. 21C shows the operation in the phase / frequency plane. It shows the action of.

FIG. 21 (b) shows the case of the complex coefficient filter I with respect to the center frequency -fb, which is the target of the adjacent channel wave that rotates in the phase opposite to the desired wave channel. Sampling is 16 times oversampling from the desired wave channel, and there is a phase difference of π / 8 in one sample interval.

The adjacent wave having the center frequency of −fb has a phase difference of −π / 8 in one sample section. Therefore, the present invention has devised a method of canceling an adjacent wave having a center frequency -fb by adding a signal obtained by rotating the signal vector obtained one sample earlier by a phase of 7π / 8 to a signal obtained one sample later.

As is apparent from FIG. 21 (b), the two samples have a phase difference of π and disappear as diametrically opposite vectors. At this time, the desired wave has a phase difference of 6π / 8,
Survive as a vector of in (π / 8).

In the same manner as the phase rotation angle for removing the adjacent channel shown in FIG. 21 (b), the phase rotation angle for removing the next adjacent channel and the next adjacent channel is
22 (a) and 22 (b). As a result, it can be seen that the removal of the next adjacent channel is 5π / 8 and the removal of the next adjacent channel is 3π / 8.

Assuming that the sample values at time to are Io and Qo on the I axis and Q axis, the rotation vector at time t1 is I axis rotation vector = Io × cos (rotation angle) −Qo × sin (rotation angle) = Io × cos7π / 8−Qo × sin7π / 8 = −Io × cosπ / 8−Qo × sinπ / 8 Q-axis rotation vector = Io × sin (rotation angle) + Qo × cos (rotation angle) = Io × sin7π / 8 + Qo × cos7π / 8 = Io × sinπ / 8−Qo × cosπ / 8. Here, the I axis is the cosine component when viewed from the phase and the Q axis is the sine component, but the rotation vector is created by multiplying both components by the rotation angle. Therefore, a filter called such a complex coefficient filter is born.

The complex coefficient filters I, II, and III of FIG. 19 show components intersecting from the I axis and the Q axis to the other side, respectively. From the above, the combined value at time t1 is combined with the vector obtained by rotating the information obtained by delaying the sample one sample before, and the outputs of the I-axis and Q-axis of the complex coefficient filter I are I
1 and Q1, I1 = Io (t = to + ts) −Io (t = to) × cosπ / 8−Qo (t = to) × sinπ / 8 ----- (Equation 1) Q1 = Qo (t = to + ts) + Io (t = to) × sinπ / 8−Qo (t = to) × cosπ / 8 ----- (Equation 2) However, t and to represent the time, and ts represents the interval time of one sample.

Similarly, in the complex coefficient filter II for removing the next adjacent channel, the rotation amount of the rotation vector is 5π.
/ 8, and in the complex coefficient filter III for removing the next adjacent channel, the rotation amount of the rotation vector is 3π / 8. When the outputs of the I axis and Q axis of the complex coefficient filter II are expressed by I2 and Q2, I2 = I1 (t = to + ts) + I1 (t = to) × cos5π / 8−Q1 (t = to) × sin5π / 8 --- (Equation 3) Q2 = Q1 (t = to + ts) + I1 (t = to) × sin5π / 8 + Q1 (t = to) × cos5π / 8 --- (Equation 4) I of complex coefficient filter III When the output of the axis and Q axis is expressed by I3 and Q3, I3 = I2 (t = to + ts) + I2 (t = to) × cos3π / 8−Q2 (t = to) × sin3π / 8 --- (Equation 5) Q3 ＝ Q2 (t = to + ts) ＋ I2 (t = to) × sin3π / 8 ＋ Q2 (t = to) × cos3π / 8 --- (Equation 6) Between time to and sample of to + ts There is a delay relationship. In FIG. 19, delay means is provided on the to side. It should be noted that there is no theoretical difference in the order in which the complex coefficient filters are cascaded. However, in reality, there is a desirable order from the frequency characteristics of the means for realizing the circuit.

In FIG. 21 (c), the desired wave center angular frequency is
Assuming that + ωo and the central angular frequencies of the three waves on the lower adjacent channel are -ωo, -3ωo, and -5ωo, respectively, the complex coefficient filters I and I that try to remove these adjacent channel waves, respectively.
The phase characteristics P of I and III are complex coefficient filters I:-
ωo removal P = -πω / 16ωo + 3π / 16 complex coefficient filter II: -3ωo
Removal P = -πω / 16ωo + 5π / 16 complex coefficient filter III: -5ωo
Removal P = -πω / 16ωo + 7π / 16 It becomes like the parallel downward three lines in the figure. When these three filter phase characteristics are combined, the line A in FIG. 21 (c) represented by P = −3πω / 16ωo + 15π / 16 is obtained, and the intercept at ω = 0 is represented by point B and is 15π / 16.

This effect is shown in FIG. 23 as a theoretical calculation result. FIG. 23A shows the individual characteristics of the three types of filters of the complex coefficient filters I, II, and III.
(b) is an overall characteristic. From FIG. 23 (a), it can be understood that the frequency zero appears at four times the channel interval in the first stage of the complex coefficient filter, but it occurs every channel interval when combined. Further, it is clear from FIG. 23 (b) that as a result, the desired wave shown in the gray part is protected while the upper and lower adjacent wave groups are largely attenuated.

As described above, as shown in FIGS. 2 (a) and 2 (b), the frequency offset is applied between the center frequency of the desired wave after frequency conversion and the sampling frequency by 1/2 of the channel interval frequency. It is obtained by doing.

Another effect of the frequency offset is an effect of avoiding the influence of the DC offset and the drift after demodulation.

By the way, as shown in FIG. 21 (c), it is shown that the complex coefficient filter is given a constant phase lead / lag which does not depend on frequency. However, a plurality of stages of complex coefficient filters are connected in cascade. Figure 21 (c)
As shown in B of No. 3, frequency-dependent phase distortion occurs.

Therefore, in order to remove this phase distortion,
It is connected to the equalizer shown in FIG. In this case, since the signal is not removed, the delay means is unnecessary and the phase can be simply returned. As shown in FIG. 25, the phase equalization of the equalizer is represented by I4 and Q4 representing the outputs of the I-axis and Q-axis of the equalizer, and when the rotation phase is -15π / 16, I4 = I3 × cos (-15π / 16) −Q3 × sin (-15π / 16) -------- (Equation 7) Q4 ＝ I3 × sin (-15π / 16) + Q3 × cos (-15π / 16)- ------ (Equation 8) With the configuration of FIG. 24, the phase can be corrected by rotating the signal information from the I axis and Q axis on the orthogonal axis.

Here, if the above equations 1 to 6 are reviewed, the calculation coefficient required to generate the rotation vector is 2
It can be seen that it can be configured only by type. That is, π
Paying attention to / 8, and letting the sine and cosine be α and β respectively, sinπ / 8 = cos3π / 8 = -cos5π / 8 = sin7π / 8 = 0.3826
8 = α cos π / 8 = sin3π / 8 = sin5π / 8 = cos7π / 8 = 0.92388
= Β. Therefore, the absolute values of the coefficients of Expressions 1 to 6 can be composed of only the above two values. That is, the fact that all the filter coefficients can be configured by the above-mentioned two values is because the difference in the angular velocity of each channel is set to a multiple of π / 8, which is also the desired wave center frequency after frequency conversion. It is obtained by applying a frequency offset to the sampling frequency by 1/2 of the channel spacing frequency.

As a result of the above, the upper and lower sides are each centered around the desired wave.
Adjacent channels of the wave can be attenuated. However, a passband as shown in FIG. 26 is formed in the frequency folding region peculiar to the image suppression filter at the frequency away from the desired wave.

(Specific Example of Low-Pass Filter) Therefore, in the present invention, finally, a low-pass filter is formed by using delay means, and these high-frequency unnecessary signals are removed with a simple structure.
FIG. 26 shows the positions on the frequency to be removed, and FIG. 27 shows the configuration of the low-pass filter.

According to the configuration of FIG. 27, each delay element has an integral action determined by the delay time, so that it has a blocking action on the fundamental frequency whose fundamental period is the delay time and its second and fourth harmonics. To have. This theoretical characteristic is shown in FIG.

(Specific Example of Image Suppression Type Frequency Conversion Circuit) FIG. 29 is a specific example of the image suppression type frequency conversion circuit used in FIGS. 7, 9 and 12. Further, FIG.
1 shows the operation timing.

The frequency conversion can be expressed as follows using a complex number. Considering the case of synthesizing the angular frequency ωo to be added with the angular modulation φcosωo having the angular center frequency ωc, cos ((ωc + ωo) t + φcosωot) + jsin (((ωc + ωo) t + φcosωot) = Cos (ωct + φcosωot) × cosωot-sin (ωct + φcosωot) × sinωot + j {sin (ωct + φcosωot) × cosωot + cos (ωct + φcosωot) × sinωot}-(Equation 9) In the case of waves, it is necessary to reduce the center frequency to the DC region, so if ωc → (-ωo), then Equation 9 above is cos ((ωot + φcosωot) -ωot) + jsin ((ωot + φcosωot)-
ωot) = cos (ωot + φcosωot) × cosωot + sin (ωot + φcos
ωot) × sinωot ＋ j {sin (ωot + φcosωot) × cosωot-cos
(ωot + φcosωot) × sinωot} where φcosωot << π / 2, cos ((ωot + φcosωot) -ωot) + jsin ((ωot + φcosωot)-
ωot) ＝ cos (ωot + φ) × cosωot + sin (ωot + φ) × sinωot
+ J {sin (ωot + φ) × cosωot-cos (ωot + φ) × sinωot}, and each cosine and sine satisfy the sampling theorem if the sampling frequency is 2ωo. Therefore, the sampling time may be set to 4 sampling times in one cycle in which the phase value of the angular frequency ωo is an integral multiple of π / 2.

31 (d) and 31 (e), cosωo
This is a state in which t and sinωot are sampled by 4 samplings per cycle. At time nπ, sinωot becomes 0, and at the time when the phase is delayed by π / 2, cosωot becomes zero. Therefore, there are only two non-zero sampled values in one cycle as shown in FIGS. 31 (d) and 31 (e).

As described above, since the frequency conversion is obtained by multiplication, the zero phase can be ignored. As a result, co
The multiplication with sωot or sinωot is simply the product of +1 and -1, that is, the multiplication is done if only the polarity is managed. In FIGS. 31 (j), (l), and (m), cosωot is +
At the same time that the time becomes 1 or -1, the sampled signal I
i (nT) and Qi (nT) signals multiplied by +1 and -1, that is, positive polarity Ii (nT) and Qi (nT) and opposite polarity -Ii (nT) and -Qi (nT) Is a gate signal for selecting.

Note that all of these control signal groups shown in FIG. 31 are dominated by clock signals, and it is possible to generate these control signals by a circuit very similar to the control circuit shown in FIG. In addition, since it is almost obvious that it can be generated by a standard logic circuit, it is omitted to present it with a concrete example.

In the circuit diagram of FIG. 29 (b), the amplifier U10
Shows the configuration of switch SW11 and capacitor C10.
A buffer amplifier having the same function as the inverting amplifier U1 of No. 7 and the same polarity as the input signal is formed. In exactly the same way, the amplifier U20 likewise forms a buffer amplifier of the same polarity as the input signal. The amplifier U11 is an inverting amplifier which has the same function as the inverting amplifier U2 in FIG. 17 and which generates an input signal and an output whose polarity is inverted. The same applies to the amplifier U21.

Amplifiers U12 and U22 are composed of a plurality of capacitors.
A polarity inversion multiplication / addition circuit is supplied with signals from C17, C28 or C18, C27. The multiplication gain is the feedback capacitor C31.
Or input side capacitors C17, C2, C1 with C32 as the denominator
8, determined by the value of the ratio with C27 as the numerator. Switch SW11
~ SW15, switches SW21 ~ SW25 are the amplifiers U11, U12, U2.
1, U22 receives the input signal Ii (nT) or Qi (nT) and generates positive polarity Ii (nT) and Qi (nT) and opposite polarity -Ii (nT) and -Qi (nT). Therefore, it operates under the control of the above-mentioned FIGS. 31 (a), 31 (b) and 31 (c) generated in synchronization with the clock signal a or its inverted signal. The switches SW16 to SW19 have positive polarity Ii (n
T) and Qi (nT) and -Ii (nT) and -Qi (nT) having opposite polarities are selected and transmitted to the adder circuit by the amplifier U12 to control its output Io (nT). Signals for controlling the switches SW16 to SW19 are shown in FIG.
(j), (k), (l), (m) or its inverted signal.

Now, at time t1, as shown in the timing control j shown in FIG. 31 (j), only cosine becomes +1 and the switch SW17 supplies -Ii (nT) to the polarity inversion multiplication / addition circuit U12. Therefore, Ii (nT) is generated at the output Io (nT).

At time t2, only sine becomes +1 as shown in the timing control 1 shown in FIG. 31 (l), and the switch SW18
Is supplied to the polarity inversion multiplication / addition circuit U12 through -Qi (nT), so Qi (nT) is generated at the output Io (nT).

At time t3, only cosine becomes -1 as shown in the timing control k shown in FIG. 31 (k), and the switch SW
Since 16 supplies it to the polarity inversion multiplication / addition circuit U12 through + Ii (nT), -Ii (nT) is generated at its output Io (nT).

At time t4, only sine becomes -1 as shown in the timing control m shown in FIG. 31 (m), and the switch SW19
Is supplied to the polarity inversion multiplication / addition circuit U12 through + Qi (nT), and -Qi (nT) is generated at the output Io (nT).

Similarly, on the Qo (nT) terminal side, at time t1, cosine as shown in the timing control j shown in FIG.
Only becomes +1 and the switch SW27 supplies it to the polarity inversion multiplication and addition circuit U22 through -Qi (nT), so its output Qo (nT) has Q
i (nT) occurs.

At time t2, only sine becomes +1 as shown in the timing control 1 shown in FIG. 31 (l), and the switch SW28
Is supplied to the polarity inversion multiplication / addition circuit U22 through -Ii (nT), so that Ii (nT) is generated at the output Qo (nT).

At time t3, only cosine becomes -1 as shown in the timing control k shown in FIG. 31 (k), and the switch SW
Since 26 supplies + Qi (nT) to the polarity inversion multiplication / addition circuit U22, -Qi (nT) is generated at its output Qo (nT).

At time t4, only sine becomes -1 as shown in the timing control m shown in FIG. 31 (m), and the switch SW29
Is supplied to the polarity inversion multiplication / addition circuit U22 through + Ii (nT), and -Ii (nT) is generated at the output Qo (nT).

Thereafter, the circuit switching control from time t1 to t4 is performed every four clocks, and the operation of the equation 7 is executed according to the principle shown in FIG.

In this way, the image suppression type frequency conversion circuit can be realized by using the switched capacitor circuit.

FIG. 30 is a circuit example for controlling the image suppression type frequency conversion circuit shown in FIG. A first D-type flip-flop U1 that receives the sampling clock signal a at its clock input terminal CLK and a second D-type flip-flop and a Q output of the first D-type flip-flop U1 that receive its Q output at its clock input terminal CLK. And sampling
A first logical product circuit U3 which receives the clock signal a, a logical sum circuit U4 which receives the Q-bar output of the first D-type flip-flop U1 and the Q-bar output of the second D-type flip-flop U1 A second OR circuit U6 receiving the Q output of the first D-type flip-flop U1 and the Q-bar output of the second D-type flip-flop U2 at its inputs and the Q-bar output of the first D-type flip-flop U1 A third OR circuit U8 receiving the Q output of the second D-type flip-flop U2 at its input, the Q output of the first D-type flip-flop U1, and the second D-type flip-flop U2.
And a second AND circuit U5 which receives the negative logical output of the first OR circuit U4 and the sampling clock signal a A third logical product circuit U7, which receives the negative logic output of the logical sum circuit U4 and the sampling clock signal a, and a negative logical output of the third logical sum circuit U4, which receives the sampling clock signal a 4 AND circuit U9 and 4th AND circuit U4
And a fifth AND circuit U11 which receives the sampling clock signal a and its negative logic output.

The operation will be described with reference to FIG. The sampling clock signal a is supplied to the clock input CLK of the first D-type flip-flop U1 to obtain the divided output Q and the negative logic output Q bar. The Q output is supplied to the clock input CLK of the second D-type flip-flop U2 to obtain the divided output Q and the negative logic output Q bar. As a result,
A signal obtained by dividing the sampling clock signal a by 4 is obtained at the output Q and the negative logic output Q of the second D-type flip-flop U2. As a result, the first AND circuit U3 is supplied with the sampling clock signal a and the Q output of the first D-type flip-flop U2, and the Q output is set to 2 clocks only during the period of the high potential "H". At the same time, the output becomes high potential "H". The second AND circuit U5 divides the sampling clock signal a from the Q-bar output of the first D-type flip-flop U1 by 1/2 and outputs the sampling signal from the Q-bar output of the second D-type flip-flop. The sampling clock signal a is supplied with the negative logic output of the first OR circuit U4 which receives the 1/4 frequency division of the clock signal a and the first clock period of the four sampling clock periods is at the high potential " H ”. Similarly, the third AND circuit U7
Is a 1/2 frequency-divided signal of the sampling clock signal a from the Q output of the first D-type flip-flop U1 and a 1/4 minute of the sampling clock signal a from the Q-bar output of the second D-type flip-flop. The negative logic output of the second logical sum circuit U6 having the frequency and the sampling clock signal a are supplied, and the second clock period of the four sampling clock periods becomes the high potential "H". Fourth AND circuit U9
Is a 1/2 frequency-divided signal of the sampling clock signal a from the Q-bar output of the first D-type flip-flop U1 and a 1 / 4-minute divided signal of the sampling clock signal a from the Q-output of the second D-type flip-flop U1. The negative logic output of the third logical sum circuit U8 having the frequency and the sampling clock signal a are supplied, and the third clock period of the four sampling clock periods becomes the high potential "H". Fifth AND circuit U11
Is a 1/2 frequency-divided signal of the sampling clock signal a from the Q output of the first D-type flip-flop U1 and a 1/4 frequency-divided signal of the sampling clock signal a from the Q-output of the second D-type flip-flop U1. Fourth OR circuit with inputs and
The negative logic output of U10 and the sampling clock signal a are supplied, and the fourth clock period of the four sampling clock periods becomes the high potential "H".

From the above, each timing waveform at the operation timing of the specific example of the image suppression type frequency conversion circuit shown in FIG. 31 is the + 1 / -1 discrimination signal (h) by the above control circuit. 1 corresponds to the output signal of the AND circuit U3, and similarly the I / Q discrimination signal (i) shown in FIG.
Corresponds to the Q output signal of the first D-type flip-flop U1 of the control circuit, and the +1 timing waveform (j) of cos θ corresponds to the output signal of the second AND circuit U5 of the control circuit. The output signal of the third AND circuit U7 of the control circuit corresponds to the -1 timing waveform (k) of cos θ, and +1 of sin θ
The timing waveform (l) of is the fourth AND circuit of the above control circuit.
It is clear that the output signal of U9 corresponds and the output signal of the fifth AND circuit U11 of the control circuit corresponds to the -1 timing waveform (m) of cos θ. Therefore, FIG.
It becomes clear that the image suppression type frequency conversion can be achieved by the configuration example of the image suppression type frequency converter shown in FIG. 4 and the control circuit shown in FIG.

(Specific Example of Some Functional Elements by Switched Capacitor Circuit) FIG. 32 shows a specific example of the complex coefficient filter. FIG. 32 shows a delay coefficient, an inverter, and a multiplication adder, which are the basic elements constituting the complex coefficient filter, embodied in a switched capacitor circuit.

As for the operating principle of the switched capacitor circuit, the explanation of the operation performed in the orthogonal component separation circuit of FIG. 17 can be applied, so that it is omitted here. Circuit elements of a switched capacitor circuit for forming a complex coefficient filter are shown in FIGS. 32 (b), 32 (c) and 32 (d). To realize a complex coefficient filter as shown in FIG. 32 (a), a delay device, a positive number multiplier, a negative number multiplier and an adder are required.

FIG. 32 (b) shows a delay device using a switched capacitor circuit. Capacitance can have a multiplying effect. The multiplication formula is shown in the figure.

A negative multiplier is shown in FIG. 32 (c). The adder is shown in FIG. When performing multiplication with a positive number, the negative number multipliers are cascaded in two stages.

FIG. 33 shows a concrete example of one stage of the complex coefficient filter using the switched capacitor circuit configured by using the above basic elements. Similarly, FIG. 34 shows an implementation example of a phase equalizer using a switched capacitor circuit.

FIG. 35 shows an implementation example of a low-pass filter using a switched capacitor circuit. In FIG. 35, the same I-axis and Q-axis are used. All operations are clock controlled.

That is, the power consumption in the switched capacitor circuit is proportional to the transfer clock speed, proportional to the capacitance held, and proportional to the square of the signal amplitude handled. If the switched-capacitor circuit is composed of a low-noise device such as a compound semiconductor such as GaAs, a sufficient S / N can be obtained even if the signal amplitude is small. Even when the frequency becomes high, the power consumption is much lower than that of the processing by the conventional digital circuit.

FIG. 36 shows a specific example in which an equalizer using a switched capacitor circuit and a low-pass filter are integrated. The switched capacitor has an operational amplifier in each stage in principle, but the operational amplifier is also a major cause of increasing power consumption in the switched capacitor circuit. FIG. 36 shows an example in which the number of operational amplifiers is reduced by sharing the operational amplifier on the equalizer side and the operational amplifier on the low-pass filter side. The equalizer 1 in the figure may be connected to the low-pass filter 2 independently of the quadrature component, but the operational amplifier near the output of the equalizer 1 that should be originally placed in the gray thick line frame is omitted and shared. Is connected to the operational amplifier 4 and the operational amplifier 5 near the input end of the low-pass filter 2 so as to supply both quadrature components. Although FIG. 36 shows only the Q-axis side, the I-axis side can be shared in the same manner.

In order to further reduce the power consumption of the receiving device, the filter using the switched capacitor circuit shown in FIGS. 33, 34, 35 and 36 may not be sufficient. This is because, as is apparent from FIGS. 33, 34, 35 and 36, too many active devices, especially amplifiers, consume a lot of power.

(Example of Embodying Functional Elements by CCD Circuit)
FIG. 37 shows an embodied example of the present invention in which sampling output is made to a filter constituted by a CCD circuit. FIG. 37 (a) shows the structure of the CCD. The CCD is capable of forming a charge potential well between the n-type substrate and the SiO ₂ layer, and can transfer the charge stored in the potential well by the potential of the gate electrode provided outside the SiO ₂ layer. is there.

As is clear from FIG. 37 (a), in principle, there is no active element in the charge transfer direction. Further, since the processing is performed by transferring the charges, it is not necessary to supply new charges to the same information. Therefore, power consumption is fundamentally low. Also, all operations are controlled by a clock applied to the gate electrode. However, since it does not need to pass through the switching element, noise due to switching is small.

Therefore, if the low noise device is used, a sufficient S / N can be obtained even if the signal amplitude is small, so that it is not necessary to secure a large amplitude, and the power consumption is much lower than that of the switched capacitor circuit. Becomes CCDs are commonly used to transfer images. Therefore, as shown in FIG. 37 (a), only the input charges are sent to the final output.

In order to achieve the object of the present invention, it is necessary to distribute a signal to the delay circuit section, generate a delay difference, and combine a non-delayed signal and a delayed signal. It is not preferable to complete the treatment only with electric charges.

In FIG. 37 (b), a circuit for the above function is devised for this purpose. The contents of one stage of the low-pass filter will be described. In FIG. 37 (b), the gray thick line frame represents one delay type low-pass filter consisting of an input buffer stage 1, a delay side CCD line 2, a non-delay side CCD line 3, an adding CCD 4, and an output buffer / input buffer stage 5. FIG. 27 shows a specific example of the basic configuration of the delay element low-pass filter shown in FIG. 27 for the first stage. This is shown in FIG.
In FIG. 6B, the reference numeral 6 corresponds. Similarly, reference numeral 7 indicates a low-pass filter stage with a delay difference of 2 stages, and reference numeral 8 indicates a low-pass filter stage with a delay difference of 4 stages.
A filter stage is shown.

In the first stage, the input buffer stage 1 is a buffer provided to supply an equal amount of electric charge to the input electric charge to the subsequent delay side CCD line 2 and non-delay side CCD line 3, and the input charge Charge about twice the amount from the power supply CC
Supply to column D. The delay-side CCD row 2 and the non-delay-side CCD row 3 can be composed of exactly the same unit cell if the transmission loss can be ignored.

In the first stage, the length of the CCD array is C on the delay side.
The CD column 2 is increased by one cell. Since the summing CCD 4 receives charges from two systems, the potential well is widened so that the cell is not saturated. This also applies to the output buffer / input buffer stage 5. The FET buffer of the buffer stage 5 basically has the same function as the input buffer stage 1. From the above, the low-pass filter is CC
It can be realized by developing D device technology.

[0206]

With the above-described structure, the present invention is achieved by digitizing the output of the intermediate frequency stage at a single stage and at the same time sampling and holding the output thereof so that the subsequent signal processing can be easily integrated into an integrated circuit. The first problem is to solve the problem that the receiving device requires many parts in order to secure good reception channel selectivity.

Further, the present invention reduces the signal amplitude by adopting a switched capacitor circuit in the digitized signal processing without using a digital logic circuit, and facilitates the integration into a small number of circuit elements to realize an integrated circuit. Many parts of the first problem, which is a problem, are trying to solve a problem that large power consumption is caused.

Further, according to the present invention, the sampling performed at the time of digitization is sampled by adopting a band-limited sampling method from ordinary primary sampling.
By drastically reducing the clock frequency, the third problem is dealt with the digitization of signal processing which causes power consumption several times that of analog processing.

Further, the present invention (1) uses a complex filter employing the switched capacitor circuit to process addition, subtraction, multiplication, and division with substantially the same low power, and (2) channel conversion in down conversion to an intermediate frequency. A fourth type of conventional digital filter, in which the number of calculations is reduced by applying a frequency offset corresponding to the interval frequency and by using the complex coefficient filter, is complicated and the power consumption is large. I am trying to resolve.

Further, according to the present invention, although the received signal is discretized by the sample and hold circuit, the digital signal processing is performed by using the switched capacitor circuit without conversion to the logical level, and the input signal is input. The solution to the A / D converter that requires a large input signal amplitude, which is the fifth problem, is eliminated by eliminating the need to increase the signal amplitude.

Further, the present invention deals with the sixth problem by making the local oscillation signal not equal to the carrier frequency of the received signal and applying the frequency offset corresponding to the channel interval frequency as described above. The conversion receiving method is a solution to radiate a local oscillation signal from the antenna to interfere with an adjacent station or to generate an error in a demodulation signal due to a DC offset.

As described above, the present invention can provide a receiving apparatus that solves all the conventional problems.

In the inventions of claims 2 to 6 and 8 to 9, the connection order of three stages in the complex coefficient filter of the constituent elements or the connection order of the complex coefficient complex and the equalizer is mathematically different from each other. It is a basic property of a general linear circuit that it is possible to obtain substantially the same effect even if the configurations are connected in reverse order because of the multiplication action, and this is within the scope of the present invention.

Similarly, in the inventions of claims 8 to 9, in the connection order of the thinning circuit of the components and the frequency converter for removing the offset frequency, or the averaging circuit and the frequency converter for removing the offset frequency. However, since each is mathematically a multiplication action, even a configuration in which they are connected in reverse order is included in the scope of the present invention.

Furthermore, in the inventions of claims 1 to 9, the basic sampling frequency is set to 16 times the base bandwidth of the desired wave.
The fact that the doubling point is set to 32 times and the adjacent wave number is set to about twice is basically only to extend the idea of the present invention, and is included in the scope of the present invention. Needless to say.

Further, in the method of using the adjacent wave removing circuit means system using the complex coefficient filter in a dual manner as set forth in the inventions of claims 7 to 9, the total sampling frequency is set to 64 times the base bandwidth of the desired wave. It means that it can be used in a double or multiple manner, and 64 times oversampling is considered to include the case of multiplying by an integer power of 2.

Further, the present invention is variously devised for the purpose of performing signal processing by hardware. For example, the sampling frequency, that is, the sampling frequency is set to 16 times the desired wave base band and the digital signal processing is performed. It is also possible to configure a complex coefficient filter and capture the next adjacent wave and the next adjacent wave at the position for each phase angle difference π / 4 to remove them.
It is considered to fall within the scope of the present invention.

In the inventions of claims 1 to 4, the removal of the remaining amount of frequency offset shown in the inventions of claims 5 to 6 is left to the signal processing in the digital system. Basically, this removal is performed. It goes without saying that is essential.

It is considered that the combined use of the thinning-out process and the averaging process by the eclectic combination of the invention of claim 8 and the invention of claim 9 is basically included in the invention of claim 7.

Similarly, in the frequency conversion by local oscillation in the invention of claim 8 and the invention of claim 9, selection of a method of setting the frequency range after frequency conversion as an intermediate frequency and a method of setting it as a direct current range, thinning-out processing and averaging A plurality of combinations can be selected in selecting the chemical conversion processing, and it is considered that all of them are basically included in the invention of claim 7.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration example of a first embodiment of the present invention,

FIG. 2 is a first explanatory diagram of the first embodiment of the present invention,

FIG. 3 is a second explanatory diagram of the first embodiment of the present invention,

FIG. 4 is a diagram showing a configuration example of a second embodiment of the present invention,

FIG. 5 is a first explanatory diagram of the second embodiment of the present invention,

FIG. 6 is a second explanatory view of the second embodiment of the present invention,

FIG. 7 is a diagram showing a configuration example of a third embodiment of the present invention,

FIG. 8 is an explanatory diagram of a third embodiment of the present invention,

FIG. 9 is a diagram showing a configuration example of a fourth embodiment of the present invention,

FIG. 10 is an explanatory diagram of a fourth embodiment of the present invention,

FIG. 11 is a diagram showing a configuration example of an averaging circuit used in the fourth embodiment of the present invention;

FIG. 12 is a diagram showing a configuration example of a fifth embodiment of the present invention,

FIG. 13 is a diagram showing a configuration example of a fifth embodiment of the present invention,

FIG. 14 is a diagram showing a configuration example of a thinning circuit of the present invention,

FIG. 15 is an explanatory diagram of a fifth embodiment of the present invention,

FIG. 16 is a diagram showing an example of a high speed sample hold circuit;

FIG. 17 is a diagram showing a specific example of an orthogonal component separation circuit,

FIG. 18 is a diagram showing operation timing of a specific example of the orthogonal component separation circuit;

FIG. 19 is a diagram showing an example of a complex coefficient filter;

FIG. 20 is a diagram showing setting of characteristics of a complex coefficient filter;

FIG. 21 is a diagram showing an operation explanation of a complex coefficient filter;

FIG. 22 shows the next adjacent channel and the phase rotation angle for removal for the next adjacent channel;

FIG. 23 is a diagram showing theoretical characteristics of a complex coefficient filter;

FIG. 24 is a diagram showing a configuration example of an equalizer,

FIG. 25 is a diagram showing the operation of the equalizer;

FIG. 26 is a diagram showing how the filter function deteriorates at high frequencies seen in the output of the complex coefficient filter group and a region removed by a low-pass filter;

FIG. 27 is a diagram showing a configuration example of a delay element type low-pass filter,

FIG. 28 is a diagram showing a positional relationship between characteristics of a delay element low-pass filter and each channel wave;

FIG. 29 is a diagram showing a configuration example of an image suppression type frequency conversion circuit;

FIG. 30 is a diagram showing an example of a circuit that controls an image suppression type frequency conversion circuit;

FIG. 31 is a diagram showing the operation timing of the image suppression type frequency conversion circuit;

FIG. 32 is an explanatory diagram of implementation of a filter using a switched capacitor circuit;

FIG. 33 is a diagram showing an implementation example of one stage of a complex coefficient filter using a switched capacitor circuit;

FIG. 34 is a diagram showing an implementation example of a phase equalizer using a switched capacitor circuit;

FIG. 35 is a low-pass capacitor using a switched capacitor circuit.
A diagram showing an example of implementation of a filter,

FIG. 36 is a diagram showing a circuit example of an equalizer and a low-pass filter in which power consumption is reduced by sharing an operational amplifier;

FIG. 37 is a diagram showing a CCD equalizer and a low-pass filter;

FIG. 38 is a diagram showing the configuration of a conventional receiving device;

FIG. 39 is a diagram showing a conventional example of a direct conversion receiving device,

FIG. 40 is a diagram showing a problem of direct conversion reception.

[Explanation of symbols]

 1 Received Signal Input 2 High Frequency Amplifier 3 First Band Pass Filter 4 Frequency Converter 5 Local Oscillator 6 Second Band Pass Filter 6'First Stage Low Pass Filter 7 AGC Amplifier 8 Sample Hold Circuit 9 Sampling Clock 10 I-axis Component separation circuit 11 Q-axis component separation circuit 12 Complex coefficient filter 13 Complex coefficient filter I-axis output 14 Complex coefficient filter Q-axis output 15 I-axis equalizer 16 Q-axis equalizer 17 I-axis baseband signal output 18 Q-axis base Band signal output 19 I-axis low-pass filter 20 Q-axis low-pass filter 21, 21 'I-axis output to image suppression type signal processing system 22, 22' Q-axis output to image suppression type signal processing system 23, 23 'Clock Signal generation and control circuit 24 I-axis thinning circuit 25 Q-axis thinning circuit 26 Image suppression type frequency conversion circuit 27 I-axis averaging circuit 28 Q-axis averaging circuit 1 12 4-fold complex coefficient filter 115 I-axis 4-fold equalizer 116 Q-axis 4-fold equalizer 119 I-axis 4-fold low-pass filter 120 Q-axis 4-fold low-pass filter 124 I-axis 4-fold thinning Circuit 125 Q-axis quadruple region thinning circuit 127 I-axis quadruple region averaging circuit 128 Q-axis quadruple region averaging circuit

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Fujio Sasaki 4-3-1 Tsunashima Higashi, Kohoku-ku, Yokohama-shi, Kanagawa Prefecture Matsushita Communication Industrial Co., Ltd.

Claims (13)

[Claims] 1. A receiver for a radio system using orthogonal modulation or a similar modulation method, in which carrier frequencies are arranged at channels at equal frequency intervals or at frequencies close to the channels, the desired channel being received. Receiving a received signal including a signal, the frequency of the upper or lower end of the band of the desired channel to receive or the boundary with the corresponding adjacent channel is centered around the boundary frequency, and a frequency range up to about three channels is selectively changed to an intermediate frequency. A means for converting, a means for sampling at a frequency 16 times a bandwidth of a desired reception channel or a frequency ½ of a channel interval frequency of the corresponding wireless system, and means for extracting a quadrature component in phase from the sampling output. And means for extracting a signal of a desired channel for reception from the positive phase axis signal component and the quadrature phase axis signal component A receiving device comprising: 2. A receiver for a radio system using orthogonal modulation or a similar modulation method, in which carrier frequencies are arranged in channels at equal frequency intervals or in frequencies close to the channels, the desired channel being received. Receiving a received signal including a signal, the frequency at the upper or lower end of the band of the desired channel to receive or at the boundary with the corresponding adjacent channel is selectively tuned to a frequency range up to about 3 channels above and below the boundary frequency to the DC region. A means for converting, a means for sampling at a frequency 16 times a bandwidth of a desired reception channel or a frequency ½ of a channel interval frequency of the corresponding wireless system, and means for extracting a quadrature component in phase from the sampling output. And means for extracting the signal of the desired channel for reception from the positive phase axis signal component and the quadrature phase axis signal component. A receiving device comprising: 3. A frequency converter which receives a reception signal including a reception desired channel signal and which has an intermediate frequency at the upper or lower end of the band of the desired reception channel or at the boundary with the corresponding adjacent channel, and a frequency from this frequency converter. An intermediate frequency stage that receives the converted output and has a pass band in a frequency range of up to about three channels around the intermediate frequency, and an output of this intermediate frequency stage is 16 times the bandwidth of the desired reception channel.
Or a sample-and-hold circuit that samples at a frequency that is eight times the channel interval frequency of the corresponding wireless system, and a quadrature component on the phase is extracted from the sampling output and the positive-phase axis signal component and the quadrature-phase axis signal component are extracted. A Hilbert transformer to be generated, a complex coefficient filter having a function of receiving the reception signal positive phase axis signal component and the quadrature phase axis signal component and removing adjacent channels of upper and lower three channels adjacent to a desired channel signal, 2. The receiving apparatus according to claim 1, wherein the signal of the desired channel is extracted from two phase equalizers that individually receive the outputs and two low-pass filters that individually receive the outputs. 4. A frequency converter which receives a reception signal including a reception desired channel signal and sets the frequency at the upper or lower end of the band of the desired reception channel or at the boundary with the corresponding adjacent channel to direct current, that is, zero frequency, and this frequency converter. A low-frequency stage which receives a frequency conversion output from DC, that is, a pass band in the frequency range of positive and negative about 3 channels centering on zero frequency, and 16 times the bandwidth of the desired channel to receive the output of this low-frequency stage or A sample and hold circuit that samples at a frequency eight times the channel interval frequency of the corresponding wireless system, and a quadrature component on the phase is extracted from the sampling output to generate a positive phase axis signal component and a quadrature phase axis signal component. It receives the Hilbert transformer and its received signal, the positive phase axis signal component and the quadrature phase axis signal component, A complex coefficient filter having a function of removing adjacent upper and lower three adjacent channels, two phase equalizers individually receiving the outputs thereof, and two low-pass filters receiving the respective outputs are desired to be received. The receiving device according to claim 2, wherein a channel signal is extracted. 5. A decimating circuit for decimating the orthogonal signals of the desired channels to be received extracted from the two low-pass filters, and an image suppression type for removing the offset frequency by receiving the two outputs. The frequency conversion circuit is provided, The receiver in any one of Claim 1 thru | or 4 characterized by the above-mentioned. 6. An averaging circuit for respectively averaging orthogonal signals including a desired reception channel extracted from the two equalizers, and an offset averaging circuit for receiving the two outputs of the averaging circuit. An image suppression type frequency conversion circuit is provided.
The receiving device according to any one of the above. 7. A receiver for a radio system using orthogonal modulation or a similar modulation method, in which carrier frequencies are arranged in channels at equal frequency intervals or in a frequency arrangement close to the channels, the desired channel being received. It receives a received signal including a signal, and selectively selects an intermediate frequency or a direct current at the upper or lower end of the band of the desired channel or the frequency of the boundary with the corresponding adjacent channel up to about 12 channels above and below the boundary frequency. A means for frequency-converting into a region, a means for sampling at a frequency 64 times the frequency of the bandwidth of the desired reception channel or 1/2 the channel interval frequency of the corresponding wireless system, and the quadrature component in phase from the sampling output. The desired receiving channel is included from the means for extracting and the positive phase axis signal component and the quadrature phase axis signal component. Means for extracting the signals of the four channels by removing the other adjacent channels, and four channels including the extracted desired reception channel, the bandwidth of the desired reception channel or the channel interval frequency of the corresponding wireless system being 1
And a means for extracting only the desired reception channel by removing adjacent channels other than the desired reception channel with a frequency 16 times the frequency of / 2 as the sampling frequency. 8. A receiver for a radio system using orthogonal modulation or a similar modulation method, in which carrier frequencies are arranged in channels at equal frequency intervals or in frequencies close to the channels, the desired channel being received. It receives a received signal including a signal, and selectively selects an intermediate frequency or a direct current at the upper or lower end of the band of the desired channel or the frequency of the boundary with the corresponding adjacent channel up to about 12 channels above and below the boundary frequency. A means for frequency-converting into a region, a sample and hold circuit for sampling at a frequency of 64 times a bandwidth of a desired reception channel or a frequency of 1/2 of a channel interval frequency of a corresponding wireless system, and a phase output from the sampling output. Hilbe that extracts the quadrature component and generates its positive phase axis signal component and quadrature phase axis signal component Second complex having a function of receiving the received signal, the positive-phase axis signal component and the quadrature-phase axis signal component, and removing all but the upper or lower three adjacent channels adjacent to the desired channel signal. A coefficient filter, two second phase equalizers individually receiving the outputs thereof, two second low-pass filters receiving the respective outputs, and a second decimating the outputs thereof by 1/4 The decimation circuit and the received signal, the positive phase axis signal component and the quadrature phase axis signal component, are received to remove the upper or lower three adjacent channels adjacent to the desired channel signal and convert them into a baseband signal band. A first complex coefficient filter having a function, two first phase equalizers individually receiving their outputs, two first low-pass filters receiving their respective outputs, and their outputs / 4 and the first decimating circuit for decimating the receiving apparatus according to claim 7, comprising: the image suppression type frequency conversion circuit for eliminating an offset frequency, the. 9. A receiver for a wireless system using orthogonal modulation or a similar modulation method, in which carrier frequencies are arranged at channels at equal frequency intervals or at frequencies close to the channels, the desired channel being received. It receives a reception signal including a signal, and selects the intermediate frequency or direct current from the upper or lower end of the band of the desired reception channel or the frequency at the boundary with the corresponding adjacent channel up to about 12 channels above and below the boundary frequency. A means for frequency-converting into a region, a sample and hold circuit for sampling at a frequency of 64 times a bandwidth of a desired reception channel or a frequency of 1/2 of a channel interval frequency of a corresponding wireless system, and a phase output from the sampling output. Hilbe that extracts the quadrature component and generates its positive phase axis signal component and quadrature phase axis signal component Second complex having a function of receiving the received signal, the positive-phase axis signal component and the quadrature-phase axis signal component, and removing all but the upper or lower three adjacent channels adjacent to the desired channel signal. A coefficient filter, two second phase equalizers that individually receive their outputs, and an average of the outputs over 8 samples 2
The second averaging circuit of the base and the received signal positive phase axis signal component and quadrature phase axis signal component are received to remove the upper or lower three adjacent channels adjacent to the desired channel signal, and the baseband. A first complex coefficient filter having a function of converting to a signal band, two first phase equalizers individually receiving the outputs thereof, and two first phase equalizers averaging the outputs thereof over 8 samples. An averaging circuit,
An image suppression type frequency conversion circuit for removing an offset frequency, and the receiving device according to claim 7. 10. The method according to claim 3, wherein the Hilbert transformer comprises a buffer amplifier composed of a switched capacitor circuit, an inverting amplifier and a switch.
The receiving device according to claim 8. 11. The receiving apparatus according to claim 3, wherein the absolute value of the coefficient in the complex coefficient filter is constituted by only two kinds. 12. The method according to claim 3, wherein each of the operational amplifiers required for the two equalizers is shared with each of the operational amplifiers of the low-pass filter in the subsequent stage. The receiver described. 13. The receiver according to claim 12, wherein the low-pass filter is composed of a CCD to reduce the number of operational amplifiers.