JPH09266423A - Power amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the power amplifier which is simple in constitution, easily made small-sized, and inexpensive and small in power loss. SOLUTION: A voltage error signal EVA is generated by comparing the voltage at a terminal 22R of an error amplification part 22 based upon the voltage at the power supply terminal 50A of an amplifier 50 with the voltage at a terminal 22S based upon the output signal Sout of the amplification part 50. The oscillation signal FS from a reference oscillation circuit 52 is supplied to a pulse control circuit 23. When the voltage at the terminal 22S rises above that at the terminal 22RR, a control circuit 23 generates a driving signal SWA by varying a duty ratio equally to the signal FS and on the basis of the signal EVA, thereby driving an FET 12. A source voltage +VIN is raised corresponding to the signal SOUT and supplied to the terminal 50A. Similarly, a source voltage -VIN is boosted corresponding to the signal Sout and supplied to a power supply terminal 50B. It is not necessary to generates a high and a low source voltage and switch them according to the signal SOOUT, the constitution is simple and small-sized, and also inexpensive, and the power loss is reducible.

Description

Detailed Description of the Invention

[0001]

[0001] The present invention relates to a power amplifier. Specifically, when it is determined that the voltage of the output signal of the amplification unit exceeds the predetermined level with respect to the output voltage of the voltage variable unit based on the voltage error signal from the error amplification unit, the control unit outputs the drive signal. The voltage is generated to drive the switching element, and the power supply voltage of the amplification unit is boosted by the voltage variable unit.

[0002]

2. Description of the Related Art In recent years, audio devices such as mini-components and CD radio-cassettes have been reduced in size and tended to have higher outputs. A power transformer having a large capacity, a power IC, a radiator, or the like may be used. However, using a large-capacity transformer causes an increase in cost and also increases power loss because a high power supply voltage is applied to the power amplifier and the power supply transformer.

Therefore, it is conceivable to switch and use the low power supply voltage when the voltage level of the output signal of the power amplifier is low and to use the high power supply voltage when the voltage level is high. For example, as shown in FIG. 11, when the voltage level of the output signal VO is low (section TL), the low power supply voltage ± VL is selected as the operating power supply, and when it is high (section TH), the high power supply voltage ± VH is used for the operation. Select as power source.

If the power supply voltage can be changed according to the voltage level of the output signal as described above, it is possible to suppress the increase in the capacity of the transformer, reduce the cost, and suppress the power loss.

[0005]

By the way, when the power supply voltage is switched and used according to the signal level of the output signal as described above, a power supply unit for generating a high power supply voltage ± VH and a low power supply voltage ± VL are used. A power supply for generating the power must be provided, which complicates the configuration and makes it difficult to reduce the size.

Therefore, the present invention provides a power amplifier which has a simple structure, can be easily miniaturized, is inexpensive, and has a small power loss.

[0007]

A power amplifier according to the present invention amplifies an input signal by using a voltage variable section for boosting and outputting an input voltage by using a switching element and an output voltage of the voltage variable section as a power source. And the output signal of the voltage variable section and the output signal output from the amplification section are compared to generate a voltage error signal, and the drive signal for driving the switching element is generated. When the control unit has a voltage error signal from the error amplification unit and the control unit determines that the voltage of the output signal of the amplification unit exceeds the predetermined level with respect to the output voltage of the voltage variable unit, A drive signal is generated to drive the switching element.

According to the present invention, when it is determined that the voltage of the output signal of the amplifier exceeds the predetermined level with respect to the output voltage of the voltage variable unit based on the voltage error signal from the error amplifier, the control is performed. A drive signal is generated in the unit and the switching element is driven, so that the power supply voltage of the amplifier is boosted by the voltage variable unit. In addition, since the drive signal is generated in the control unit according to the voltage error signal from the error amplification unit,
The output voltage of the voltage varying unit is boosted according to the voltage level of the output signal of the amplifying unit.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration of an embodiment of a power amplifier.

In FIG. 1, the power supply voltage + VIN is supplied to one end of the choke coil 11. The other end of the choke coil 11 is connected to the drain of a field effect transistor (hereinafter referred to as “FET”) 12 which is a switching element and the anode of a diode 13. FET1
The source of 2 is grounded, and the gate is connected to a pulse width control circuit 23 described later. One terminal of the capacitor 14 is connected to the cathode of the diode 13, and the other terminal of the capacitor 14 is grounded. A voltage variable portion is formed by the choke coil 11, the FET 12, the diode 13 and the capacitor 14, and when the FET 12 is driven, the cathode of the diode 13 and the capacitor 14 are formed.
The voltage at the connection point P is set higher than the power supply voltage + VIN.

The connection point P is connected to the power input terminal 50A on the positive side of the amplifier 50 and one terminal of the resistors 15 and 20. The other terminal of the resistor 15 is a Zener diode 1
6 cathode. The anode of the Zener diode 16 is connected to the signal output terminal 50D of the amplifier 50, and the capacitor 17 is connected in parallel to the Zener diode 16. Further, one terminal of the resistor 18 is connected to the cathode of the Zener diode 16, and
The other terminal of the resistor 18 is connected to the terminal 22S of the error amplifying section 22 configured by using, for example, an operational amplifier.
Further, the other terminal of the resistor 18 is grounded via the resistor 19. The other terminal of the resistor 20 is connected to the terminal 22R of the error amplification unit 22 and is grounded via the resistor 21.

Similarly, the power supply voltage -VIN is supplied to one end of the choke coil 31. This choke coil 3
The other end of 1 is connected to the drain of the FET 32 and the cathode of the diode 33. The source of the FET 32 is grounded and the gate thereof is a pulse width control circuit 43 described later.
Connected to. One terminal of the capacitor 34 is connected to the anode of the diode 33, and the capacitor 3
The other terminal of 4 is grounded. This choke coil 3
1, the FET 32, the diode 33, and the capacitor 34 form a voltage variable portion, and when the FET 32 is driven, the voltage at the connection point Q between the anode of the diode 33 and the capacitor 34 is made higher than the power supply voltage −VIN.

To the connection point Q, the power supply input terminal 50B on the negative side of the amplifier 50 and one terminal of the resistors 35 and 40 are connected. The other terminal of the resistor 35 is the Zener diode 3
6 is connected to the anode. The cathode of the zener diode 36 is connected to the signal output terminal 50D of the amplifier 50, and the capacitor 37 is connected in parallel to the zener diode 36. Further, one terminal of the resistor 38 is connected to the anode of the Zener diode 36, and
The other terminal of the resistor 38 is connected to the terminal 42S of the error amplifying section 42 configured by using, for example, an operational amplifier.
Further, the other terminal of the resistor 38 is grounded via the resistor 39. The other terminal of the resistor 40 is connected to the terminal 42R of the error amplification section 42 and is also grounded via the resistor 41.

An oscillator 53 such as a crystal oscillator is connected to the reference oscillation circuit 52, and an oscillation signal FS generated based on the oscillator 53 is applied to pulse width control circuits 23 and 43 which are control units. Supplied.

The audio input signal SIN is supplied to the signal input terminal 50C of the amplifier 50. The amplifier 50 amplifies the audio input signal SIN to generate an audio output signal SOUT. This audio output signal SOUT is supplied to the speaker 51 from the signal output terminal 50D of the amplification section 50, and the speaker 5
The reproduced sound is output from 1.

In the error amplifying section 22, the voltage levels of the terminals 22R and 22S are compared and a voltage error signal EVA indicating the level difference is generated. The voltage error signal EVA is supplied to the pulse width control circuit 23.

In the pulse width control circuit 23, when the voltage level of the audio output signal SOUT of the amplifying section 50 exceeds a predetermined level with respect to the voltage level of the connection point P based on the voltage error signal EVA, for example, at the terminal 22S. Voltage level is terminal 2
When the voltage level is made higher than the voltage level of 2R, a pulse signal is generated based on the oscillation signal FS, and the duty ratio of this pulse signal is changed based on the voltage error signal EVA, and is supplied to the gate of the FET 12 as the drive signal SWA. To be done. Therefore, the FET 12 is switching-driven by the drive signal SWA, so that the voltage level of the connection point P is increased in accordance with the voltage level of the audio output signal SOUT.

Similarly, in the error amplification section 42, the terminal 42
A voltage error signal EVB indicating the level difference between R and 42S is generated and supplied to the pulse width control circuit 43. In the pulse width control circuit 43, when the voltage level of the terminal 42S is made higher than the voltage level of the terminal 42R in the negative direction, the oscillation signal FS
A pulse signal is generated based on the pulse signal, the duty ratio of the pulse signal is changed, and the pulse signal is supplied to the gate of the FET 32 as the drive signal SWB. Therefore, FET
32 is driven by the drive signal SWB,
The voltage level of the connection point Q is increased in the negative direction according to the voltage level of the audio output signal SOUT.

Next, the operation will be described with reference to FIGS. 1 and 2. FIG. 2A shows the audio output signal SOUT and the voltage VK on the cathode side of the Zener diode 16 shown in FIG. 2B shows the voltage VS at the terminal 22S and the voltage VR at the terminal 22R of the error amplification section 22. The voltage VS shown by the broken line in FIG. 2B is a voltage obtained by dividing the above-mentioned voltage VK by the resistors 18 and 19, and the voltage VR shown by the solid line in FIG. 2B is the voltage VP at the connection point P shown in FIG. It is the voltage divided by the devices 20, 21.

Here, until the time t1 when the voltage VS is lower than the voltage VR, the drive signal SWA output from the pulse width control circuit 23 based on the voltage error signal EVA from the error amplifying unit 22 is as shown in FIG. 2C. As shown in, it is kept constant at the low level "L". Therefore, the FET 12 is turned off, and the voltage VP at the connection point P becomes as shown in FIG. 2D.
It is equal to the supplied power supply voltage + VIN.

Next, at time t1, the voltage VS is changed to the voltage VR.
If the voltage error signal EVA is generated by the error amplifier 22 based on the voltages VS and VR,
The drive signal SWA output from the pulse width control circuit 23 is a pulse signal. The frequency of the drive signal SWA is equal to the frequency of the oscillation signal FS, and the duty ratio is variable based on the voltage error signal EVA from the error amplifier 22. Therefore, the FET 12 is switching-driven,
The voltage VP at the connection point P is set to a voltage higher than the power supply voltage + VIN by the voltage variable unit so that the voltage VS at the terminal 22S of the error amplification unit 22 and the voltage VR at the terminal 22R become equal.
Since the voltage VS at the terminal 22S is variable according to the voltage level of the audio output signal SOUT, the voltage VP at the connection point P is also variable according to the voltage level of the audio output signal SOUT.

After that, when the voltage VS becomes lower than the voltage VR at the time t2, the drive signal SWA is set to the low level "L", and the FET 12 is turned off, so that the operation of the voltage variable portion is stopped. The voltage VP at the connection point P is made equal to the power supply voltage + VIN.

Similarly, the voltage obtained by dividing the anode side voltage of the Zener diode 36 by the resistors 38 and 39,
That is, the voltage obtained by dividing the voltage of the terminal 42S of the error amplification section 42 and the voltage of the connection point Q by the resistors 40 and 41,
That is, the voltage error signal EVB is generated in the error amplifier 42 based on the voltage of the terminal 42R of the error amplifier 42, and the drive signal SWB is further generated in the pulse width control circuit 43 based on the voltage error signal EVB.

Here, if the voltage of the terminal 42S is about to exceed the voltage of the terminal 42R and becomes low, the drive signal SWB from the pulse width control circuit 43 is made a pulse signal by the voltage error signal EVB from the error amplifier 42. It The frequency of the drive signal SWB is equal to the oscillation signal FS, and the duty ratio is changed based on the voltage error signal EVB from the error amplification section 42. Therefore, the FET 32 is switched and driven, and the voltage at the connection point Q is set to a voltage higher than the power supply voltage −VIN by the voltage variable unit so that the voltage at the terminal 42S of the error amplification unit 42 becomes equal to the voltage at the terminal 42R. To be done. The voltage of this terminal 42S is the audio output signal SO.
Since it is variable according to the voltage level of UT, the voltage VQ at the connection point Q is also variable according to the voltage level of the audio output signal SOUT.

Therefore, as shown in FIG. 3, a period T in which the signal level of the audio output signal SOUT exceeds a predetermined level LU.
In U, the voltage VP supplied to the power input terminal 50A of the amplifier 50 is increased by the voltage variable unit according to the level of the audio output signal SOUT. Further, during the period TL in which the signal level of the audio output signal SOUT exceeds the predetermined level LL, the voltage VQ supplied to the power input terminal 50B of the amplifier 50 is increased by the voltage variable unit according to the level of the audio output signal SOUT. It

As described above, according to this power amplifier, the voltage error signals EVA and EVB from the error amplifiers 22 and 42 are used.
When it is determined that the voltage of the audio output signal SOUT of the amplifying unit exceeds the predetermined level with respect to the output voltages VP and VQ of the voltage varying unit, the pulse width control units 23 and 43 are determined.
Drive signals SWA and SWB are generated by the FETs 12 and 3
When 2 is driven, the output voltages VP and VQ are increased. Therefore, it is not necessary to separately provide a power supply unit that generates a high power supply voltage and a power supply unit that generates a low power supply voltage, and it is possible to provide a power amplifier that is simple in configuration, can be downsized, and is inexpensive and has low power loss. it can.

Further, the power input terminal 50A of the amplifier 50,
Depending on the output level of the audio output signal SOUT, by setting the Zener voltage of the Zener diodes 16 and 36 higher than the voltage difference between the voltage supplied to 50B and the maximum output level of the audio output signal SOUT at this voltage. The voltage of the power supply supplied to the amplification unit 50 is set to be sufficiently high, and the drive signal S is generated based on the voltage error signals EVA and EVB.
FET12,3 by changing the duty ratio of WA, SWB
Since the energization period of 2 is controlled, the output voltages VP and VQ of the voltage varying unit are boosted according to the voltage level of the output signal of the amplifying unit 50, and the audio output signal S due to the low power supply voltage.
A good reproduced sound can be obtained without causing OUT distortion.

Further, when the signal level of the audio output signal SOUT is smaller than the predetermined level and the influence of noise is significant, the FETs 12 and 32 are not driven and the generation of noise caused by the switching operation is stopped. Therefore, a good output signal can be obtained.

In the above power amplifier, the duty ratio of the drive signals SWA and SWB is varied based on the voltage error signals EVA and EVB to vary the energization period of the FETs 12 and 32, and the voltage levels at the connection points P and Q are varied. Although it is assumed that the voltage is boosted according to the voltage level of the audio output signal SOUT of the amplifier 50, the drive signal S is generated based on the voltage error signals EVA and EVB.
The frequencies of WA and SWB may be varied to boost the voltage level at the connection points P and Q. Further, based on the voltage error signals EVA and EVB, the output voltage VP,
When it is determined that the voltage of the audio output signal SOUT of the amplifying unit exceeds the predetermined level with respect to VQ, the FETs 12 and 32 are driven by the drive signal with a constant duty ratio, and the voltage levels of the connection points P and Q are increased. Of course may be boosted to a predetermined voltage level.

By the way, such a power amplifier is also used in an electronic device having a tuner. Therefore, a case where this power amplifier is used in an electronic device having a tuner will be described.

FIG. 4 is a diagram showing a configuration of an embodiment of this electronic device. In FIG. 4, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

The reference oscillating section includes the reference oscillating circuit 55 and the frequency divider 5.
7. The reference oscillator circuit 55 includes an oscillator 56.
Are connected, and an oscillation signal FT having a constant frequency is generated based on the oscillator 56. The oscillation signal FT is frequency-divided by the frequency divider 57 and supplied as a signal CC to the phase comparator 58 which is an error detection unit. Further, the phase comparator 58 is supplied with a frequency-divided signal CD from a frequency-dividing unit 64, which will be described later.
FC is generated. The frequency error signal EFC is supplied to the base of the NPN transistor 60 via the low pass filter 59.

The oscillating section 61 is composed of a CR oscillating circuit, for example, and generates an oscillating signal FS having a constant frequency. The frequency of the oscillation signal FS is set by the resistor 62 and the capacitor 63. The emitter of the transistor 60 is connected to the connection point of the resistor 62 and the capacitor 63, and the collector of the transistor 60 is connected to the other terminal of the resistor 62.
By this, the resistance value between the terminals of the resistor 62 is changed, and the frequency of the oscillation signal FS is changed. The oscillation signal FS generated by the oscillator 61 is supplied to the pulse width control circuits 23 and 43 and the frequency divider 64.

In the frequency division section 64, a tuning microcomputer (hereinafter referred to as "microcomputer") for a tuner section in which the oscillation signal FS supplied from the oscillation section 61 receives a radio broadcast.
The frequency is divided by the frequency division control signal BC.

FIG. 5 shows the configuration of the tuner section.
In FIG. 5, the signal RS received by the antenna 70 is
It is supplied to the high frequency amplifier circuit 71. High frequency amplifier circuit 71
Then, the signal of the broadcast radio wave to be selected is selectively amplified and supplied to the mixing circuit 72 as a high frequency signal RF.

In the mixing circuit 72, a single frequency signal IFA is generated based on the high frequency signal RF from the high frequency amplifier circuit 71 and a local oscillation signal FO from a local oscillation circuit 76 described later. The frequency signal IFA is amplified by the intermediate frequency amplifier circuit 73 and the band thereof is limited.
Is supplied to the detection circuit 74.

In the detection circuit 74, the intermediate frequency amplification circuit 73
The signal IFB from is detected and an audio signal SA is generated. The audio signal SA is output from the audio output terminal 75.

Next, the microcomputer 90 generates a tuning signal BA for selecting a broadcast radio wave and a control signal BB for setting the inter-station frequency of the broadcast radio wave to be selected. The tuning signal BA is supplied to the frequency divider 77, and the control signal BB is supplied to the frequency divider 78. Further, the microcomputer 90 generates a frequency division control signal BC for varying the frequency of the oscillation signal FS generated by the oscillator 61 shown in FIG. 4 according to the selected broadcast radio wave. The frequency division control signal BC is supplied to the frequency division unit 64 shown in FIG.

The frequency divider 77 is supplied with the local oscillation signal F0 from the local oscillation circuit 76, and the local oscillation signal F0 is frequency-divided by a frequency division ratio based on the channel selection signal BA to obtain a frequency division signal CA.
Is generated. The divided signal CA is supplied to the phase comparator 81.

A reference oscillator circuit 79 is connected to the frequency divider 78, and the oscillator 8 connected in the reference oscillator circuit 79 is connected.
Based on 0, an oscillation signal FR having a constant frequency is generated.
This oscillation signal FR is supplied to the frequency divider 78. Frequency divider 7
In 8, the oscillation signal FR is divided by the division ratio based on the control signal BB from the microcomputer 90, and the reference signal CB having a predetermined frequency is generated. For example, when the broadcast wave is AM broadcast, the frequency of the reference signal CB is equal to the inter-station frequency 9
kHz. This reference signal CB is supplied to the phase comparator 81.

The phase comparator 81 compares the frequency-divided signal CA with the reference signal CB to generate the frequency error signal EFA. The frequency error signal EFA is supplied to the local oscillation circuit 76 via the low pass filter 82.

The local oscillation circuit 76 generates a local oscillation signal FO having a constant frequency, and the local oscillation signal FO is generated based on the frequency error signal EFA from the phase comparator 81.
The frequency of is changed.

Therefore, the tuning signal B from the microcomputer 90
The frequency of the local oscillation signal FO is controlled by the local oscillation circuit 76 so that the frequency of the frequency-divided signal CA and the reference signal CB obtained from the local oscillation signal F0 with the frequency division ratio based on A becomes constant, A single frequency signal IFA based on the desired broadcast radio wave is generated from the mixing circuit 72, and the audio signal SA of the desired broadcast radio wave can be obtained from the audio output terminal 75.

A display unit 91 is connected to the microcomputer 90, and a display signal DP is supplied from the microcomputer 90 to display on the display unit 91 the frequency selected by the tuner section.

Next, the operation will be described with reference to FIG. In the oscillator 61, for example, the oscillation signal F of 100 kHz
S is generated. In the pulse width control circuits 23 and 43, based on the oscillation signal FS, the duty ratio is varied based on the voltage error signals EVA and EVB from the above-described error amplification units 22 and 42 while having the same frequency as the oscillation signal FS. Drive signals SWA and SWB are generated.

Therefore, the FETs 12 and 32 are 100 k
Since the drive is performed based on the drive signals SWA and SWB of Hz, noise components as shown by the broken line in FIG. 6 are generated.

In the frequency division section 64, the oscillation signal FS is 1
The frequency is divided into / 20 to generate the divided signal CD of 5 kHz. In the frequency divider 57, the oscillation signal FT generated by the reference oscillation circuit 55 is frequency-divided to generate a signal CC of 5 kHz, for example. In the phase comparator 58, the signal CC and the divided signal CD
And the frequency error signal EFC is generated and supplied to the transistor 60, the frequency of the oscillation signal FS generated by the oscillator 61 is held at 100 kHz.

Here, when the tuner section is operated to receive the broadcast radio wave of 999 kHz, for example, the frequency division control signal BC from the microcomputer 90 shown in FIG. 5 causes the frequency division section 64 shown in FIG. , Oscillation signal FS is 1/2
The frequency is divided by 1 to generate the divided signal CD. At this time,
The phase comparator 58 compares the signal CC with the frequency-divided signal CD to generate a frequency error signal EFC, and the frequency error signal EFC drives the transistor 60. Therefore, the resistance value between the terminals of the resistor 62 is made small, and the frequency of the oscillation signal FS generated by the oscillator 61 is increased until the frequencies of the signal CC and the divided signal CD match.

That is, the frequency of the oscillation signal FS is 1 so that the divided signal CD of 5 kHz can be obtained by dividing 1/21.
05kHz, FET12,32 is 105kHz
Since it is driven based on the oscillation signal FS of z, the noise is assumed to have a frequency different from the reception band of the broadcast radio wave to be received and the signal IFB which is an intermediate frequency signal as shown by the solid line in FIG. Can be prevented.

As described above, in the above electronic equipment, the FET is
The frequencies of the drive signals SWA and SWB are set so that the fundamental wave component and the higher harmonic wave component of the noise generated by the switching operations of 12 and 32 are different from the frequency of the signal selected by the tuner unit or the signal obtained by the tuner unit. Since the setting is made, it is possible to prevent the reception failure due to noise regardless of the selected signal.

By the way, in this electronic apparatus, the reference oscillation circuit for selecting a channel in the tuner section and the reference oscillation circuit of the reference oscillation section are separately provided. However, an electronic apparatus sharing these reference oscillation circuits is implemented. FIG. 7 shows the configuration of this form. 7, parts corresponding to those in FIGS. 1 and 4 are designated by the same reference numerals, and detailed description thereof will be omitted.

In FIG. 7, the phase comparator 58 shown in FIG.
The phase comparator 65 corresponding to the reference signal CB of the predetermined frequency generated by the frequency divider 78 of the tuner section shown in FIG.
Is supplied. In the phase comparator 65, the reference signal CB
And the frequency-divided signal CD from the frequency division unit 64 are compared, and the frequency error signal EFE is generated similarly to the phase comparator 58 of FIG. 4 and is supplied to the transistor 60 via the low-pass filter 59.

Here, in the frequency division section 64, the oscillation signal FS is frequency-divided into, for example, 1/12 to generate a frequency-divided signal CD, which is supplied to the phase comparator 65. When the inter-station frequency of the broadcast radio wave received by the tuner unit is, for example, 9 kHz, the reference signal CB of 9 kHz is supplied to the phase comparator 65. Therefore, the frequency of the oscillation signal FS generated by the reference oscillation circuit is controlled to 108 kHz based on the frequency error signal EFE based on the reference signal CB and the divided signal CD.

At this time, assuming that the broadcast radio wave of 1080 kHz is received, the harmonic component of the noise from the voltage variable section driven based on the oscillation signal FS having the frequency of 108 kHz is the frequency of the broadcast radio wave to be received. Is equal to However, by the frequency division control signal BC from the microcomputer 90 shown in FIG. 5, the frequency division unit 64 shown in FIG. 7 changes the frequency division ratio of the oscillation signal FS to 1/13 to generate the frequency division signal CD. It For this reason, it is 9k with a division of 1/13
Since the frequency of the oscillation signal FS is set to 117 kHz so that the frequency-divided signal CD of Hz can be obtained, the harmonic component of noise is assumed to have a frequency different from the reception band of the broadcast radio wave to be received, thereby preventing reception failure. be able to.

The frequency-divided signal CD is compared with the reference signal CB of a predetermined frequency of the tuner section, and the drive signal SW is generated based on the frequency error signal EFE generated by the phase comparator 65.
Since the frequencies of A and SWB are controlled to drive the FETs 12 and 32, it is not necessary to separately provide an oscillation circuit that generates a signal of a constant frequency in order to generate the frequency error signal EFE, and the configuration is simple and inexpensive. Can be

In the above electronic equipment, the oscillation signal FS
It is assumed that the frequency division unit 64 divides the
Even if the drive frequency of 2 is detected and the detected frequency is divided to generate the divided signal CD, the same effect can be obtained.

Further, in the above-mentioned electronic device, the frequency division control signal BC is obtained from the tuner section to generate the oscillation signal FS, and the oscillation signal FS is used to supply the power input terminal 50 of the amplifier section 50.
Although the case where the voltage supplied to A and 50B is boosted has been described, the voltage may be stepped down using this oscillation signal FS. Here, the case where the voltage is stepped down will be described with reference to FIG.

In FIG. 8, the oscillation signal FS obtained as shown in FIG. 4 or 7 is supplied to the pulse control circuits 23 and 43.

The amplification section 95 is composed of an amplification stage for amplifying the audio input signal SIN and an output stage for outputting the signal amplified by the amplification stage. The power supply voltage + VIN is supplied to the power supply input terminal 95A of the amplification stage of the amplifier 95 and the drain of the FET 96. The source of the FET 96 is connected to the cathode of the diode 97 and one terminal of the choke coil 98. The anode of the diode 97 is grounded, and the other terminal of the choke coil 98 is connected to the capacitor 14 and the resistor 20.
And the power input terminal 95C of the output stage of the amplifier 95. Further, the drive signal SWA is supplied from the pulse width control circuit 23 to the FET 96.

The power supply voltage -VIN is supplied to the power supply input terminal 95B of the amplification stage of the amplifier 95 and the drain of the FET 106. The source of the FET 106 is connected to the cathode of the diode 107 and one terminal of the choke coil 98.
The anode of the diode 107 is grounded and the other terminal of the choke coil 98 is connected to the capacitor 34, the resistor 40 and the power input terminal 95D of the output stage of the amplifier 95. Further, the drive signal SWB is supplied from the pulse width control circuit 43 to the FET 106.

The power input terminal 95A is connected to the cathode of the Zener diode 16 via the resistor 99, and the cathode of the Zener diode 16 is connected to the connection point of the capacitor 17 and the resistor 18. The power input terminal 95B is connected to the anode of the Zener diode 36 via the resistor 109, and the anode of the Zener diode 36 is connected to the connection point of the capacitor 37 and the resistor 38. The audio input signal SIN is supplied to the signal input terminal 95E, and the amplified audio output signal SOUT is output from the signal output terminal 95F.

In FIG. 8, the other parts are constructed in the same manner as in FIG. 4 or 7. In FIG. 8, the voltage variable portion is composed of FETs 96 and 106 and a diode 9
7, 107, choke coils 98, 108, and capacitors 14, 34 form a voltage variable section.

In the electronic device shown in FIG. 8, as shown in FIG. 9, during the period TUD in which the signal level of the audio output signal SOUT exceeds the predetermined level LU, the voltage supplied to the power supply input terminal 95C of the amplification section 95. VP is stepped down according to the level of the audio output signal SOUT. Further, in the period TLD in which the signal level of the audio output signal SOUT exceeds the predetermined level LL,
The voltage VQ supplied to the power input terminal 95D of the amplifier 95 is stepped down according to the level of the audio output signal SOUT. Also, the signal level of the audio output signal SOUT is a predetermined level L
When in the range of U and LL, the voltages VP and VQ are stepped down to constant levels. Therefore, the power supply voltage of the output stage of the amplifier 95, which has a large power loss, is controlled according to the audio output signal SOUT, so that the power loss can be reduced.

By the way, the reception disturbance is remarkable when the fundamental wave component and the harmonic wave component of the noise are substantially equal to the frequencies of the reception band of the broadcast radio wave and the substantially equal periods have a certain time width. Therefore, even when the frequencies are substantially equal to each other, when the period is short, it is possible to receive the broadcast radio wave without causing a large reception obstacle. Therefore,
An embodiment of a power amplifier that does not need to change the oscillation frequency according to the received broadcast wave will be described with reference to FIG. Note that, also in FIG. 10, parts corresponding to those in FIGS. 1, 4 and 7 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In FIG. 10, the oscillator 6 is included in the oscillator circuit 66.
7 is connected, and an oscillation signal FU having a constant frequency is generated based on the oscillator 67. This oscillation signal FU is supplied to the frequency divider 68.

A frequency division control unit 69 is connected to the frequency divider 68, and the frequency division control unit 69 continuously switches the frequency division ratio of the oscillation signal FU in the frequency divider 68 at predetermined time intervals. Alternatively, a frequency division control signal BD for discontinuously switching is generated.

Based on the frequency division control signal BD, the frequency divider 6
The frequency-divided signal obtained by dividing the oscillation signal FU in 8 is supplied to the pulse width control units 23 and 43 as the oscillation signal FS, and the drive signal S is generated based on the oscillation signal FS as described above.
WA and SWB are generated and the FETs 12 and 32 are driven.

At this time, since the frequency division ratio of the oscillation signal FU in the frequency divider 68 is switched at a predetermined time interval, the frequencies of the drive signals SWA and SWB are also switched at a predetermined time interval.

As described above, according to this power amplifier, the frequency of the drive signals SWA and SWB is changed continuously or discontinuously by the frequency division control unit 69, and the FET1
The frequencies of the fundamental wave component and the higher harmonic wave component of the noise generated by the switching operation of 2, 32 are not constant and are dispersed. Therefore, the frequencies of the fundamental wave component and the harmonic component of the noise can be changed in a short time, so that the noise amount per unit time of the predetermined frequency can be reduced, and the generated noise has no practical problem. Can be reduced to a level.

It should be noted that the frequencies and frequency division ratios shown in the power amplifiers and electronic devices described above are merely examples, and other frequencies and frequency division ratios may be used.

[0071]

According to the present invention, it is determined based on the voltage error signal from the error amplifier that the voltage of the output signal of the amplifier exceeds the predetermined level with respect to the output voltage of the voltage variable unit. In some cases, the control unit generates a drive signal to drive the switching element, so that the power supply voltage of the amplification unit is boosted by the voltage variable unit. Further, the control unit generates a drive signal according to the voltage error signal from the error amplification unit, and boosts the output voltage of the voltage variable unit according to the voltage level of the output signal of the amplification unit.

Therefore, a power supply section for generating a high power supply voltage and a power supply section for generating a low power supply voltage are separately provided,
Since it is not necessary to switch the power supply according to the voltage level of the output signal of the amplification section, it is possible to provide a power amplifier which has a simple structure, can be downsized, and is inexpensive and has less power loss.

Further, since the output voltage of the voltage varying section is boosted according to the voltage level of the output signal of the amplifying section and this output voltage is used as the power source of the amplifying section, the power source voltage of the amplifying section is low. Distortion of the output signal can be prevented, and a good output signal without distortion can be obtained.

Further, when the signal level of the output signal is lower than the predetermined level, the switching element does not operate, so that a good output signal can be obtained without generating noise caused by the switching operation.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of a power amplifier.

FIG. 2 is a diagram showing an operation on the positive electrode side according to the embodiment.

FIG. 3 is a diagram showing an operation of the embodiment.

FIG. 4 is a diagram showing a configuration of an embodiment of an electronic device.

FIG. 5 is a diagram showing a configuration of a tuner unit.

FIG. 6 is a diagram showing a relationship between noise of a power amplifier and a signal of a tuner section.

FIG. 7 is a diagram showing another configuration of the electronic device according to the embodiment.

FIG. 8 is a diagram showing another configuration of the electronic device according to the embodiment.

FIG. 9 is a diagram showing an operation of another embodiment.

FIG. 10 is a diagram showing another configuration of the power amplifier according to the embodiment.

FIG. 11 is a diagram showing an operation of a conventional power amplifier.

[Explanation of symbols]

 22, 42 Error amplification section 23, 43 Pulse width control circuit 50, 95 Amplification section 51 Speaker 52, 55, 79 Reference oscillation circuit 57, 64, 77, 78 Frequency division section 58, 65, 81 Phase comparator 59, 82 Low Band filter 61 oscillation unit 66 oscillation circuit 68 frequency divider 69 frequency division control unit 71 high frequency amplification circuit 72 mixing circuit 73 intermediate frequency amplification circuit 74 detection circuit 76 local oscillation circuit 90 microcomputer (microcomputer)

Claims (3)

[Claims] 1. A voltage variable unit that boosts and outputs an input voltage by using a switching element, an amplifier unit that amplifies and outputs an input signal by using the output voltage of the voltage variable unit as a power source, and the voltage variable unit. An error amplifier that generates a voltage error signal by comparing the voltage level of the output signal of the amplifier with the voltage level of the output signal of the amplifier, and a controller that generates a drive signal for driving the switching element. However, when the control unit determines that the voltage of the output signal of the amplification unit exceeds a predetermined level with respect to the output voltage of the voltage variable unit based on the voltage error signal from the error amplification unit. A power amplifier characterized by generating a drive signal to drive the switching element. 2. The control unit generates a drive signal according to the voltage error signal from the error amplification unit, and the drive signal generated by the control unit drives the switching element, The power amplifier according to claim 1, wherein the output voltage of the voltage varying unit is boosted according to the voltage level of the output signal of the amplifying unit. 3. The control unit varies the duty ratio of the drive signal to be generated based on the voltage error signal from the error amplification unit, and drives the switching element with the drive signal generated by the control unit. The power amplifier according to claim 2, wherein the energization period of the switching element is controlled by doing so.