JPH09265895A - Vacuum microelement - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable anode to be integrated by forming an anode, an anode gate, and a gate layer based on the three-layer structure board of Si/oxidation film/Si being structurally stable and providing high pressure resistance, structural strength, and stability. SOLUTION: An Si layer 1 is made by anode-formation, an anode-formation Si layer 2 is formed, this layer is oxidized, an anode-formation thermal oxidation Si layer 3 is formed, them then it is adhered to another Si layer. Here, the thickness of the anode-formation thermal oxidation Si layer 3 is 1 to 200 micrometers and 1/2 of the Si layer 1, and deformation due to stress is prevented. Next, boron is diverged in a gate Si layer with high concentration, and a p++ diffusion layer 6 is formed. Further, an emitter mold 7 is etched, and a thermal; oxidation Si layer 8 is formed to be a gate insulation film. Furthermore, an anode Si layer is etched, and an anode opening 9 is formed. Moreover, an emitter layer 11, an anode gate insulation spacer opening 10, a gate opening 12, and an insulation layer 13 are formed. Thereby, high pressure resistance, structural strength, stability, and integration are ensured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vacuum micro device having a field emission cold cathode.

[0002]

2. Description of the Related Art A field emission type vacuum micro device has been actively used in recent years because of its high-speed response, improved radiation resistance and high temperature resistance, and high definition, self-luminous display. Research and development is being conducted. The beginning was K.K. in 1961. R. Shoulder
Proposed tunnel effect vacuum triode proposed by s et al.
icroelectronics using ele
ctron-beam-activated match
ining techniques, Advance
s in Computers Vol 2, p.
p. 135-293), but in general, the same SRI (Stanford) has attracted attention in this field.
Research Institute) C.I. A.
Report of cold cathode using thin film of Spindt (J. Ap.
pl. Phys. 39, p. 3504, 196
It is from 8). He proposed and reported the basic method of manufacturing and the structure of the most widely used device known as the Spindt method up to the present, by using the sophisticated technique of rotating oblique deposition and sacrificial layer etching. . As shown in the conventional example 1 in FIG. 6, an outline of this method is as follows. First, a thermal oxide film 21 is formed on a Si substrate 20, and, for example, a Mo metal layer 22 is formed as a metal layer to be a gate, and this is patterned. After forming the gate opening 23, the underlying oxide film layer is etched. After thinly depositing, for example, an Al metal layer 24 as a metal serving as a sacrifice layer, for example, a Mo metal layer 25 as a metal forming an emitter layer is deposited by a rotary oblique deposition method. Since the vapor-deposited metal also adheres to the periphery of the opening, the opening becomes narrower, and the Mo emitter 26 having a conical tip is formed inside as shown in the figure. Finally, the extra Mo layer deposited on the gate together with the sacrificial layer Al is removed to complete the emitter.

However, there is a problem that the non-uniformity of the structure of the emitter material causes the non-uniformity of the characteristics because the material is limited to the material which can be formed by the emitter vapor deposition method by this technique. There is also a problem that it is difficult to control the tip shape.

On the other hand, attempts have been made to manufacture an emitter using single crystal Si having higher purity and good reproducibility. In the conventional example 2 of FIG. 7, Betu is shown.
i et al. (K. Betui, 1991 Fabric).
ation and charactersistics
of Si field emitter arra
ys, Technical Digest 4th
Int. Vacuum Microelectron
ics Conf. (Nagahama, Japan
n), pp 26-29. ), In the drawing, the mask thermally oxidized Si layer 28 formed by thermally oxidizing the Si substrate 27 is patterned to form a mask, and Si under the mask is under-etched by isotropic etching. This is further thermally oxidized to form a thermally oxidized Si layer 29, thereby sharpening Si. Furthermore, with the mask left,
For example, SiO ₂ is formed as the deposited gate insulating layer 30,
Subsequently, Mo or the like is formed as the gate metal layer 31. Then, the thermal oxide film is etched and the mask portion is lifted off to form the Si emitter 32 in the gate opening. This method is an excellent method in which a single crystal Si is used as a material, which is stable and has good reproducibility, and an emitter can be formed in a self-aligned manner with a gate.

However, when this method is actually carried out, there are the following problems. First, in the formation of an emitter by isotropic etching of Si, it is difficult to control the etching progress direction and speed at a constant level, and the end point cannot be determined. difficult. As a similar method, there is a method in which this step is performed by anisotropic etching of Si, but this also has the same problem. Especially in any case, if the emitter is thinned and etching is performed to the last, the mask is removed, and the subsequent processes cannot be performed.

Further, in any of the above methods, the gate can be integrally formed, but the anode must be prepared separately, which impedes practical use as an element. That is, it cannot be handled as an integrated element, and it is necessary to provide electrodes in a state of being insulated to the outside and maintaining a constant interval, which makes the handling difficult.
In addition, these complexities have been a cause of impairing reproducibility and reliability in terms of characteristics. This is because the vacuum micro element generally uses a high anode voltage of several hundred to several thousand V, and several tens of kV when considering a power element application, and therefore an integrated anode having sufficient withstand voltage and mechanical strength to withstand this. Is difficult to form.

[0007]

As described above, in the conventional vacuum micro device, the emitter cannot be made fine, and the sufficient withstand voltage and mechanical strength to withstand a high anode voltage of several hundreds V to several tens of kV. It was difficult to form a strong one-piece anode.

In view of the above-mentioned current state of the vacuum micro device, the present invention provides a device structure in which not only an emitter and a gate but also an anode having a high withstand voltage and having high electrical and mechanical reliability are integrated. It is what As a result, it is intended to secure practical usability as an integrated element and to realize an element excellent in withstand voltage, stability and heat resistance. In addition, it aims to secure a sufficient emitter density that is easily damaged by the integration of the anode, and to provide an element suitable for power application that requires high breakdown voltage, large current density, and high reliability in addition to the above-mentioned characteristic improvement. It is a thing.

[0009]

The essence of the present invention is that, first of all, single crystal Si having a thick thermally oxidized Si layer formed by thermally oxidizing a porous Si layer formed by thermal oxidation anodization or CVD. The substrates are bonded to each other in atomic order, preferably by direct bonding without an adhesive layer or the like, and a three-layer substrate of single crystal Si / thick SiO ₂ / single crystal Si is prepared, which is used as an anode / spacer / gate respectively. Especially. Secondly, the emitter is formed by filling the gate Si layer from the non-bonding surface side with a conductive material in a sharpened template formed by, for example, anisotropic etching, and only the emitter layer formation region is sharpened from the opposite side of the substrate. Is formed by removing the Si and Si oxide layers until exposed. More desirably, the gate Si layer also serving as the emitter template has a <100> orientation,
A pyramid-shaped template is formed by anisotropic etching, and this is thermally oxidized to form a gate insulating film, and the tip is sharpened. Also, the anode Si layer has a <110> orientation, which is also anisotropic. The purpose is to keep the emitter density high by forming an anode having vertical sidewalls with respect to the substrate surface by reactive etching. Further, if necessary, the gate Si layer and the emitter layer can be patterned into, for example, orthogonal lines so that each emitter or emitter array cell can be addressed. It can also be adhered to to improve mechanical strength. The azimuths described above may be slightly deviated, and there is no problem even if they are tilted by 2 to 3 degrees from the <100> direction, for example.

According to the present invention, the emitter, the gate, and the anode can all be integrated on a single substrate, and the layers from the gate insulating film, the gate, the gate-anode insulating spacer, and the anode can be glued or the like. It can be monolithically laminated without using. It is possible to join them in the order of atoms. This improves the heat resistance and mechanical strength of the device and improves the reliability.
In addition, the anode layer and the gate layer have different orientations of S.
Since i can be selected, <10
A 0-oriented substrate can be used to make a tip-shaped template for the emitter, while a <110> -oriented substrate can be used for the anode to form the vertical opening.

Furthermore, by using anodized thermal oxidation Si between the layers of the anode / gate layer, a thick and high-quality oxidized Si layer which could not be realized in the past can be obtained.
Although it is a gate-integrated type, the breakdown voltage can be greatly improved. In addition, almost any material can be used as the material for the emitter layer, including refractory metals such as Mo, Ta, and W, as well as materials such as diamond, diamond-like carbon, AlN, and LaB ₆ that can be expected to function after stopping. The mold can be used as an emitter with good shape reproducibility. Especially if the Si emitter material is selected, the whole S
i and its oxide can be formed,
Strength can be improved.

Furthermore, since the entire device is firmly held by the body composed of a thick anodized Si oxide layer / anode Si layer, the back surface of the emitter can maintain its strength without any particular reinforcement. Therefore, it is possible to easily form a resistance layer, various wirings, and a TFT transistor on the back surface. Further, since the strength is maintained by the Si oxide layer and the anode layer as described above, the gate layer can be patterned to be separated into, for example, lines.

Since the emitter is also exposed on the surface, it can be patterned in the same manner. This makes it possible to pattern the emitters and gates, for example, orthogonally to form an address-driven matrix array. Further, the gate openings and the openings of the anodes do not necessarily have to correspond to each other one by one, and one anode opening can be collectively provided for the plurality of emitters and the gate openings corresponding thereto.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a manufacturing process diagram of a main embodiment of the present invention. In this embodiment,
First, as a <110> Si layer 1, a p ⁻ type Si substrate is prepared, and this is anodized in hydrofluoric acid.
Anodized Si layer 2 having a thickness of 10 μm was formed on the surface. An etching solution in which hydrofluoric acid and ethanol were mixed at a volume ratio of 2: 3 was used for this preparation, and anodization was performed at a current density of 10 to 80 mA / cm ² . At this time, the porosity was adjusted to 55% to 70% so that the pores would be minimized after the subsequent oxidation and not excessively swollen to deform the substrate itself. Then, the anodized thermally oxidized Si layer 3 was formed by thermally oxidizing this. If necessary, the surface was flattened and polished, and then adhered to a separately prepared # 5 <100> Si layer. At this time, it is effective to increase the breakdown voltage and reduce leakage by forming a Si oxide film on the <100> substrate surface by thermal oxidation. Also, this interface may be subjected to anodization thermal oxidation. Further, in the case of an element which does not require a high breakdown voltage, an oxide film may be formed on both substrates only by thermal oxidation. In this case, a maximum film thickness of about 3 μm can be obtained, and the total film thickness is 6 μm.
It is possible to obtain up to about 6000 v with a withstand voltage of about μm. On the other hand, in the case of the anodized thermal oxide film, there is almost no restriction on the film thickness, but as the film thickness increases, deformation due to stress with the substrate Si easily occurs. In order to avoid this, it is desirable that the thickness of the oxide film layer is not more than 1/2 of the thickness of Si at the maximum. In this way, a three-layer structure substrate of Si / thick oxide film / Si is obtained, and its thickness is adjusted by mechanical polishing or the like. In particular,
The thickness of the gate Si layer is adjusted to 3 to 10 μm. Next, boron is highly diffused in the gate Si layer to form the p ++ diffusion layer 6. This is to selectively etch stop the gate Si layer later. Next, the emitter mold 7 is formed by anisotropic etching so that the height thereof is almost the same as the p ⁺⁺ region, and a thermally oxidized Si film 8 is formed to serve as a gate insulating film and at the same time, the tip of the emitter mold is removed. Sharpen.
At this time, the tip of the gate oxide film is made to protrude beyond the p ⁺⁺ region. Next, the anode Si layer is opened by anisotropic etching so as to have a wall surface perpendicular to the substrate, and the anode opening 9 is formed. For example, as shown in FIG. 2, the openings have a stripe shape when viewed from the top surface of the substrate, and the emitter array is formed corresponding to the stripe openings. As a result, the normal <1
The effective opening region can be made larger than that in the case of using the 00> substrate, and the effective emitter density can be increased. This opening may be formed by ordinary etching or RIE or the like. Also,
The opening shape is not limited to the stripe shape, and any shape is possible. Further, in the case of a striped opening shape, the structural strength can be improved by appropriately bridging. Next, as the emitter layer 11, diamond-like carbon is deposited by the CVD method in this embodiment, and further, the anode / gate insulating spacer opening 10 is opened by etching. Si in this state
Since the layer surface is exposed, the surface is anisotropically etched with a mixed etching solution of ethylenediamine, pyrocatechol, water and pyrazine. As a result, the p ⁺⁺ region diffused with a high concentration of boron is etch-stopped, and the gate is formed in a self-aligned manner. Next, the gate oxide film near the emitter tip exposed by buffered hydrofluoric acid is removed by etching to form the gate opening 12. Furthermore, here, the back surface of the emitter is coated with polyimide varnish by spin coating,
The insulating layer 13 is formed by curing. Although this insulating layer is not essential, it is useful for preventing a short circuit and deterioration of the emitter layer with the outside. The emitter thus manufactured has high heat resistance and can withstand baking at 350 ° C. or higher. This enables sufficient degassing of the emitter surface, and a high degree of vacuum can be maintained even in vacuum sealing. The emitter of this embodiment has an emitter base dimension of 2 μm, a gate oxide film thickness of 0.1 μm, and a gate-anode oxide film thickness of 10 μm, and an anode voltage of 100 V.
Then, the current flows from the gate voltage of 15 V, and the current-voltage characteristics according to the Fowler-Nordheim relationship are shown. Further, the anode breakdown voltage was about 10 kV, which was almost the same as the value expected from the breakdown voltage of the thermally oxidized Si layer.

FIG. 3 shows an embodiment in which the upper part of the anode is vacuum-sealed, and the opening of the anode layer is sealed in a vacuumed state by, for example, an electrostatic bonding method to seal the vacuum chamber. It is possible to obtain a completely self-standing vacuum micro device that is equipped with a single unit. Usually, the effective anode electrode, that is, the electron is actually incident on the inner wall of the opening, but it is also possible to make the lid body conductive and make it contact with the anode layer to function as a part of the anode. it can. Further, it is also possible to use the opening as a control electrode, provide a conductive lid that is insulated from this portion, and use this as an anode. In this case, the lid may be made of glass and an alliance electrode, and a phosphor may be applied so that light emission can be observed from the upper side, so that it can be used for a fluorescent display element or an array thereof, a display, or the like.

FIG. 4 shows an embodiment in which the gate line and the emitter line are patterned, and FIG. 5 shows the manufacturing process thereof. In this example, as shown in (d), the patterned gate Si line layer 16 was formed by simultaneously etching the Si layer in regions other than the mold when the emitter mold was formed. In this embodiment, the anode opening 9 that opens the gate Si layer later is used.
Was patterned into lines along the stripes. This was thermally oxidized to form a gate insulating film, and then the emitter layer 11 was laminated. Further, this emitter layer was patterned to form a patterned emitter line layer. Further, here, in order to reinforce the patterned line, after forming the insulating layer 13 and flattening the back surface of the emitter, an Al electrode is formed as the adhesive layer 15 and glass is electrostatically adhered as the supporting substrate 19. . As an insulating layer, in addition to insulating properties, heat resistance and low degassing,
The ability to flatten the surface is important, and SOG and polyimide are suitable. By spin-coating and heat-treating any of these materials, a final compound is generated with reflow, and the surface can be smoothed. In the case of SOG, the thickness is as thin as about several μm, but by completely skipping the organic substance, a flattened insulating layer having high heat resistance and less risk of degassing can be realized. In the case of polyimide,
By selecting the material and viscosity of the polyimide varnish, 1
A thick film having a thickness of 0 μm or more can be obtained. This is advantageous not only for planarization, but also for reducing the stray capacitance between the emitter layer and the adhesive layer. Also, when manufacturing such a device, alignment between layers is important, but the alignment mark for this purpose is not a normal mark but the same as or smaller than the emitter mold. It is effective to use dots. That is, in the case of including the step of forming the emitter mold as in the present invention, if the alignment pattern and the like are simultaneously formed on the etching mask, it is also etched. As a method of avoiding this, a dot pattern that is the same as or smaller than the emitter is used as the alignment mark, and it is preferable to collect a plurality of dot patterns and use them as marks of practical size.
Just like the emitter mold, the alignment mark is once <1
When it reaches the 11> plane and becomes a pyramid shape, etching does not proceed from there and the accuracy of the pattern can be maintained.

As described above, fine lines are protected, mutual insulation is completely maintained, mechanically strengthened, and sufficient strength against vacuum drawing is exhibited. Also,
In the embodiment, the stripe-shaped gate openings are formed for the emitters in one row, but one anode opening may be formed for the emitters in a plurality of rows. May be adhered. Further, the Si oxide layer used in the above embodiment is not limited to thermal oxidation and anodic oxidation, but may be formed by a CVD method.

[0018]

According to the present invention, not only the emitter / gate portion but also the anode can be integrated while having a high breakdown voltage and structural strength / stability. This is based on a three-layer structure of Si, an oxide film, and Si that has a thickness of an insulating layer necessary to secure a breakdown voltage and is structurally stable. Each of them has an anode layer, an anode / gate insulating layer, and a gate layer. It was realized by using as. Further, since the anode layer and the anode-gate insulating layer have the structural strength of the device, the gate layer and the emitter layer can be freely processed. This makes it possible to realize patterning of the gate and emitter layers, which has been difficult in the past. Further, since the emitter is manufactured using the mold, it is possible to form the emitter with good reproducibility even if it is difficult to control the shape. Moreover, the back surface of the emitter layer can be freely accessed as it is after it is formed in the mold, and an auxiliary circuit structure such as a resistance layer or a transistor can be easily added. In addition, the anode layer supporting the structure is usually expanded by etching in the depth direction, so that the opening diameter is widened, and as a result, the density of the emitter cannot be increased. However, in the present invention, the anode layer and the gate layer can be arbitrarily formed. Since it is possible to select Si having the azimuth and characteristics, it is possible to form an opening substantially vertically by using the <110> substrate on the anode layer side, and it is possible to increase the effective density of the emitter. .

[Brief description of drawings]

FIG. 1 is a process cross-sectional view for explaining a first embodiment of the present invention.

FIG. 2 is a perspective view for explaining the first embodiment of the present invention.

FIG. 3 is a cross-sectional view for explaining an embodiment of the present invention in which the anode upper part is vacuum-sealed.

FIG. 4 is a cross-sectional view for explaining an embodiment of the present invention.

FIG. 5 is a process cross-sectional view for explaining the second embodiment of the present invention.

FIG. 6 is a diagram for explaining a conventional example.

FIG. 7 is a diagram for explaining a conventional example.

[Explanation of symbols]

1: <110> Si layer 2: anodized Si layer 3: anodized thermally oxidized Si layer 4: direct bonding interface 5: <100> Si layer 6: p ^{+ +} diffusion layer 7: emitter mold 8: thermally oxidized Si film 9: Anode opening 10: Anode / gate insulating spacer opening 11: Emitter layer 12: Gate opening 13: Insulating layer

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Naoshi Sakuma 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Incorporated Toshiba Research and Development Center

Claims (5)

[Claims] 1. A first single crystal Si layer forming an anode and a second single crystal Si layer having a <100> orientation forming a gate are bonded to each other through an Si oxide layer. 2. A vacuum microdevice comprising: an emitter layer formed by using a recess formed in the second Si layer from the non-adhesive surface side as a template; and a through opening formed so that a tip of the emitter layer is exposed. 2. The first Si layer has a <110> orientation plane as a main surface, and the anode side of the through opening is formed so as to have a side wall perpendicular to the main surface. The vacuum micro-element according to claim 1. 3. The thickness of the Si oxide layer is 1 μm or more and 200 μm.
2. The vacuum micro device according to claim 1, wherein the thickness does not exceed 1/2 of the thickness of the anode Si layer within m. 4. The oxidized Si layer is thermally oxidized, anodized or CV.
The vacuum micro device according to claim 1, wherein the vacuum micro device is formed by a D method. 5. The vacuum micro device according to claim 1, wherein the through opening is formed by anisotropic etching.