JPH09265774A - Laminated memory module substrate and access system to its substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accelerate write or erase for a laminated memory module substrate by performing write access or erase access with interleave control. SOLUTION: A command cycle is issued to a memory chip 1, and while the memory chip 1 is performing a write execution cycle, the command cycle is issued to a memory chip 2. Then, while the memory chip 2 performs the write execution cycle, a confirm cycle is issued to the memory chip 1. Succeedingly, when the confirm cycle of the memory chip 1 is ended, the confirm cycle is issued to the memory chip 2. In such a manner, by performing simultaneous concurrent access with the interleave control, a write time is accelerated. Further, even for an erase operation mode, by changing a command value and a data value of a write operation mode, high speed erase becomes possible.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an access method for a plurality of stacked memory modules and a stacked memory module board on which a plurality of stacked memory modules are mounted.

[0002]

2. Description of the Related Art A plurality of stacked memory modules mounted therein have a very large storage capacity, as known from Japanese Patent Laid-Open No. 1-309362. However, when normally writing with a 16b bus width to a laminated memory module substrate having a memory capacity of 800 MB class, for example, a writing time of about 30 minutes or more is extremely high. It was supposed to take a long time.

[0003]

In the above-mentioned prior art, no consideration has been given to performing writing at a high speed for a plurality of stacked memory modules mounted.

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems of the prior art, an object of the present invention is to enable a laminated memory module substrate on which a plurality of laminated memory modules are mounted to be written or erased at high speed. It is to provide an access method for modules.

Another object of the present invention is to provide a laminated memory module substrate on which a plurality of laminated memory modules are mounted so that the heat concentration of the modules can be alleviated and writing or erasing can be performed at high speed. It is to provide an access method for a memory module.

Another object of the present invention is to provide a laminated memory module substrate on which a plurality of laminated memory modules are mounted so that the concentration of heat generated by the modules can be alleviated and writing or erasing can be performed at high speed. It is to provide a memory module substrate.

[0007]

In order to achieve the above object, the present invention provides a memory chip between stacked memory modules in a stacked memory module substrate on which a plurality of stacked memory modules are mounted, or a memory chip in the stacked memory module. Is an access method for a stacked memory module, which is characterized by performing write access or erase access to each memory chip by interleaving control.

Further, according to the present invention, a write operation is performed for each memory chip by interleaving control between the above-mentioned laminated memory modules in a laminated memory module substrate on which a plurality of laminated memory modules are mounted or between memory chips in the laminated memory module. It is an access method to a laminated memory module substrate, which is characterized in that the increase in heat generation in the module is suppressed by performing access or erase access.

Further, the present invention is characterized in that, in the method of accessing the laminated memory module substrate, the laminated memory module is a laminated flash memory module.

In addition, according to the present invention, in a laminated memory module substrate on which a plurality of laminated memory modules are mounted, interleave control is performed between the laminated memory modules or between the memory chips in the laminated memory modules so that each memory chip can be controlled. A laminated memory module substrate is provided with an interleave control circuit for write access or erase access.

As described above, according to the present invention, a stacked memory module substrate having a three-dimensional mounting structure for realizing a large capacity memory can be accessed at high speed without damaging the module due to concentrated heat generation. . For example, a 32 Mb memory chip, 8 layers, and 26 modules can provide a memory capacity of 840 MB. When a series is accessed to this stacked memory module, it takes about 44 minutes to write with a 16b bus width, whereas writing can be performed in about 100 seconds or less by interleave control.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described with reference to the drawings.

First, FIG. 1 is a diagram showing a plurality of stacked memory modules mounted on a substrate, (a) is a plan view,
(B) is a front view. FIG. 2 is a perspective view showing a case where stacked memory modules are arranged and mounted in a row: W direction and a column: S direction on a mother substrate. That is, the laminated memory module 1 is formed, for example, by stacking the memory chips 4 mounted on the film-shaped substrate 3 connected to the outer leads 2 (for example, the number of layers H = 8 layers). That is, in the module as a whole, the chip select CSs are independently provided for the number of layers (in this case, for example, 8), and the other pins have a pin arrangement common to the eight layers. This stacked memory module 1
Row the stacked memory modules 1 on the mother board 21:
W direction and column: It is mounted by arranging in the S direction. The read / write control circuit 2 provided on the mother board 21
2 is connected to each memory chip 4 of each laminated memory module 1 via the outer lead 2.

FIG. 3 shows a single flash memory chip 4a. As shown in FIG. 3, the flash memory chip 4a includes an AD (address designation) terminal, a DT (data input / output) terminal, an OE (output enable) terminal, a WE (write enable) terminal, a CS (chip select) terminal, and a VP.
And a P (voltage application) terminal. Then, in the flash memory chip 4a, a high voltage is applied from the VPP terminal during the write operation.

FIG. 4 shows a write operation mode for the flash memory chip 4a. AD, DT, CS, WE,
OE indicates a signal input / output to / from each terminal in each cycle (TC, TE, TS). The write operation mode to the flash memory chip 4a includes a command cycle TC (100 to 200 ns as a typical numerical value example), a write execution cycle TE (1 to 6 μs as a typical numerical value example), and a confirm cycle TS (100 n as a typical numerical value example).
s) and.

FIG. 5 shows an erase operation mode for the flash memory chip. AD, DT, CS, WE, O
E indicates a signal input / output to / from each terminal in each cycle (TC, TE, TS). The erase operation mode for the flash memory chip 4a also includes a command cycle, an erase execution cycle, and a confirm cycle. In the above description, the confirm cycle is a cycle for checking whether the data has been written or erased by reading the status signal from the memory chip, and is a cycle omitted depending on the type of the memory chip used or the usage method. is there.

Next, the write operation mode based on the interleave control for the plurality of flash memory chips 4a according to the present invention will be described with reference to FIG. However, the case where the number of interleaves = 2 is shown. First, a command cycle is issued to the memory chip 1. The memory chip 1 judges the contents of the command cycle and enters the write execution cycle. A command cycle is issued to the memory chip 2 while the memory chip 1 is performing a write execution cycle. The memory chip 2 judges the contents of the command cycle, and issues a confirm cycle to the memory chip 1 during the write execution cycle. When the confirm cycle of the memory chip 1 is completed, the confirm cycle is issued to the memory chip 2. That is, interleave control (simultaneous parallel access) in which the write operation mode for the memory chip 2 is shifted by the write execution cycle with respect to the write operation mode for the memory chip 1
By performing the above, the write time can be shortened. In particular, since heat is generated in the write execution cycle TE in the memory chip, even if the memory chip 1 and the memory chip 2 are adjacent to each other by performing interleave control shifted by the write execution cycle, for example, in the module It is possible to suppress an increase in heat generation, improve the heat dissipation effect, and prevent the memory chip from malfunctioning. Further, if a cooling fin is provided for each stacked memory module 1 to enhance the cooling effect, the number of memory chips that simultaneously execute write execution cycles can be increased in the module. Particularly, in order to suppress the heat generation concentration in the module, it is desirable to perform interleave control between the memory chips between the modules. This is because the heat generation cannot be immediately dissipated even if the heat generation is reduced at the end of the write execution cycle TE in the memory chip.

FIG. 7 shows an example of a signal connection relationship between the read / write control circuit 22 and each memory chip 4 of each laminated memory module 1. However, W = 3, S = 2, H = 4
The case of is shown. In the read / write control circuit 22,
The ADP terminal has an address signal bus (AD
P) is input, a 16-bit data bus signal (DTP) is input and output to the DTP terminal, a read / write signal is input to the R / W terminal, and a clock signal is input to the CK terminal. Address bus signal (ADP) shown in FIG.
Is the MSB (Most Significant Bit) to the LSB (L
ast Significant Bit), a side ID number, a module number, a chip number, and a byte number, and is represented by the number of bytes of the chip: P = 2 to the Qth power. Of these, the side ID is a signal for grouping and identifying a plurality of memory modules, for example, one on the front surface of the motherboard and one on the back surface of the motherboard.

AD from read / write control circuit 22
The (address) signal is an output signal, is transmitted to the AD terminal of the memory chip of each module, and has a DT (16 bit)
Data) signal is transmitted / received to / from the DT terminal of the memory chip of each module, and OE (output enable: Outpu
The t Enable signal is transmitted to the OE terminal of the memory chip of each module, and WE (write enable: Write Enable).
le) signal is transmitted to the WE terminal of the memory chip of each module, and CS (chip select) signals (CS1 to CS2
4) is CS1 to CS4 of the memory chip of each module
(When H = 4) is transmitted to the terminal.

FIG. 9 is an expanded view of the structure of six stacked memory module substrates when W = 3, S = 2, and H = 4, and is the case where P = 8 in FIG. 10 and 11 and 12 show control of the six stacked memory module substrate configurations shown in FIG. 9 by time base, (a) showing a non-interleaved case, and (b) showing The case of intra-module interleave control is shown, and (c) shows the case of inter-module interleave control. Note that although T = 1 to P is shown in FIGS. 10, 11 and 12, P = 8 is shown in FIG.

In the case of non-interleave as shown in FIGS. 10 (a), 11 (a) and 12 (a), for example, a memory capacity of 840 MB is provided by 32 Mb memory chips, 8 layers and 26 modules. It takes about 44 minutes to access the laminated memory module substrate structure and write with the 16b bus width. However, FIG. 10 (b) and FIG. 11 (b) and FIG.
If interleave control is performed as shown in (b) and FIGS. 10 (c), 11 (c), and 12 (c), for example, a 32 Mb memory chip, 8 layers, and a stacked memory having a memory capacity of 840 MB by 26 modules When the module board configuration is accessed and writing is performed with a 16b bus width, the writing can be performed in about 60 seconds, which is less than about 100 seconds, without damaging the memory chip due to heat generation concentration.

As shown in FIGS. 10 (b), 11 (b), and 12 (b), rather than interleave control between layers in each stacked memory module 1, FIGS. 10 (c) and 11 (c) are used. Also, as shown in FIG. 12C, interleave control between the stacked memory modules 1 is preferable because heat is not concentrated in the stacked memory modules. For convenience of explanation, when interleaving in the stacked memory module, in FIG. 10 (b) and FIG. 11 (b),
The access order of the chips in the module is H = 1 → 2 → 3 →
However, the access order can be arbitrarily changed as H = 1 → 4 → 2 → 3 according to the form of the module to be used and the characteristics of the memory chip. Also in the case of interleaving between stacked memory modules, FIG.
11 (c) and 12 (c), (W, S)
= (1,1) → (2,1) → (1,2) → (2,2), but similarly (W, S) = (2,1) →
The access order can be arbitrarily changed as in (2,2) → (1,1) → (1,2).

In particular, if a cooling fin is attached to each laminated memory module 1 to improve the heat radiation efficiency, as shown in FIG.
As shown in FIG. 0 (b) and FIG. 11 (b), even in the interleave control between layers in each laminated memory module 1, a laminated memory module substrate configuration having a large memory capacity of, for example, 840 MB is obtained without damaging the memory chip. On the other hand, writing or erasing can be executed in a very short time of 100 seconds or less.

Next, another embodiment of the write operation mode based on the interleave control for the plurality of flash memory chips 4a according to the present invention will be described with reference to FIG. The command cycle is composed of two patterns, but since pattern 1 represents the type of command such as read or write, all the data input to the memory chips subject to interleaving are the same. Therefore, pattern 1
6 are simultaneously input to the memory chips to be interleaved, and for pattern 2 and subsequent ones, the number of interleaving can be further increased by continuously inputting the memory chips in the access order as in FIG. 6, and the access time can be shortened. .

FIG. 14 shows an example of a circuit configuration for realizing the write operation based on the interleave control shown in FIG. However, the number of interleaves = 4, the number of memory chips = 1
The case of 6 is shown. The address decoder 31 selects a memory block to be interleaved, and the address decoder 3
2 selects the memory chip to be accessed, but performs the decoding function only when the EN signal is valid (logical value H in this circuit example). The command flag CF is a signal that outputs a logical value H when the pattern 1 of the command cycle shown in FIG. 13 is generated. First, the address decoder 3
At 1, only EN of the address decode 32 connected to the memory block to be interleaved is validated.
The selected address decoder 32 selects the memory chip 4 to be accessed according to the input address value. However, when the command cycle pattern 1 is input, the command flag CF becomes the logical value H, so the block to be interleaved. Commands are written in all the memory chips of. After the pattern 2 of the command cycle, the write operation shown in FIG. 13 is realized by setting the logical value of the command flag CF to L and accessing the memory chips 4 individually. It should be noted that this embodiment can cope with any number of interleaves and memory chips. Further, since there is no restriction on the access order of the memory chips, interleaving between the memory modules can be realized, so that it is possible to deal with the heat generation concentration countermeasure when the memories are stacked.

Although the write operation mode of the memory has been described above, also in the erase operation mode, high speed erase can be performed by changing the command value and the data value of the write operation mode.

Although the above embodiment has been described with respect to the structure of the laminated memory module substrate composed of the flash memory, it can be applied to the SRAM and the DRAM.

As for the read operation, the read operation may be performed in the written order.

[0029]

As described above, according to the present invention,
For example, for a stacked memory module substrate structure having a large memory capacity of 840 MB, writing or erasing can be executed in a very short time of 100 seconds or less without damaging the memory chip or the module. Further, according to the present invention, since writing or erasing (erasing) can be executed in a very short time of 100 seconds or less without damaging a memory chip or a module, a laminated memory composed of a readable / writable flash memory. An excellent effect can be exerted on the module substrate configuration.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a stacked memory module according to the present invention, in which (a) is a plan view and (b) is a front view.

FIG. 2 is a perspective view showing a laminated memory module substrate configuration in which a plurality of laminated memory modules according to the present invention are arrayed and mounted on a mother substrate.

FIG. 3 is a diagram showing an embodiment of a flash memory chip according to the present invention.

FIG. 4 is a diagram showing a write operation mode to a flash memory chip according to the present invention.

FIG. 5 is a diagram showing an erase operation mode for a flash memory chip according to the present invention.

FIG. 6 is a diagram showing a write operation mode based on interleave control for a flash memory chip according to the present invention.

FIG. 7 is a diagram showing a circuit configuration of a laminated memory module substrate according to the present invention.

8 is a diagram showing a number structure (data structure) of an address bus signal (ADP) input to the read / write control circuit shown in FIG. 7.

FIG. 9 is an expanded view of the configuration of six stacked memory module substrates when W = 3, S = 2, and H = 4.

FIGS. 10A and 10B are diagrams showing a part to be controlled in a stacked memory module substrate configuration according to the present invention, where FIG. 10A shows a case of non-interleave, FIG. 10B shows a case of inter-module interleave control, and FIG. 8] is a diagram showing a case of interleaved control between modules.

FIG. 11 is a diagram showing an intermediate part following FIG. 10 of control in the stacked memory module substrate configuration according to the present invention;
(A) shows the case of non-interleave, (b) shows the case of inter-module interleave control, (c) is the figure which showed the case of inter-module interleave control.

FIG. 12 is a diagram showing a part subsequent to FIG. 11 of control in the stacked memory module substrate configuration according to the present invention,
(A) shows the case of non-interleave, (b) shows the case of inter-module interleave control, (c) is the figure which showed the case of inter-module interleave control.

FIG. 13 is a diagram showing a write operation mode based on interleave control for a flash memory chip according to the present invention.

FIG. 14 is a diagram showing a circuit configuration of a laminated memory module substrate according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Laminated memory module, 2 ... Outer lead, 3 ... Film substrate, 4 ... Memory chip, 4a ... Flash memory chip, 21 ... Mother substrate, 22 ... Read / write control circuit, 31 ... Address decoder, 32 ... Address decoder.

Claims (7)

[Claims] 1. A write access or an erase to each memory chip by interleaving control between the stacked memory modules in a stacked memory module substrate on which a plurality of stacked memory modules are mounted or between memory chips in the stacked memory module. A method for accessing a laminated memory module substrate, which is characterized by accessing. 2. Write access or erase to each memory chip by interleaving control between the stacked memory modules in a stacked memory module substrate on which a plurality of stacked memory modules are mounted or between memory chips in the stacked memory module. A method for accessing a laminated memory module substrate, which is characterized in that access is prevented from being concentrated on a specific module. 3. The method for accessing a laminated memory module substrate according to claim 1, wherein the laminated memory module is a laminated flash memory module. 4. In a laminated memory module substrate having a plurality of laminated memory modules mounted thereon, interleave control is performed between the laminated memory modules or between memory chips in the laminated memory module to write to each memory chip. A laminated memory module substrate comprising an interleave control circuit for access or erase access. 5. An interleave control method, wherein write access or erase access to each memory chip is speeded up by continuously writing command cycles to the memory chip. 6. A memory chip by simultaneously writing a write command or an erase command to all memory chips in a memory block to be interleaved, and continuously writing a write address and write data at the time of writing or erase data at the time of erasing to the memory chip. The interleave control method is characterized by accelerating write access and erase access to. 7. An address decoder for selecting a memory block to be interleaved, an address decoder for selecting a memory chip, and a command flag signal, wherein a command flag signal is used to access a single memory chip or all memory chips in an interleaved block. The interleave control circuit according to claim 6, wherein the interleave control according to claim 6 is performed.