JPH09261544A - Solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To always enables satisfactory video signal processing or iris control by performing the sample/hold of a reset level corresponding to the light shield picture element part of a CCD output when signal level abnormality corresponding to the light shield picture element part is detected. SOLUTION: A CDS circuit 1 has an OB level abnormality detection circuit 3 for detecting the abnormality of a signal level during an OB period based on the difference between the reset level and this signal level during the OB period and a pulse switching circuit 2 for performing the sample/hold of the reset level while switching the phase to sample/hold the CCD output through this CDS circuit 1 only during this OB period when the abnormality of the signal level corresponding to the light shield picture element part is detected. Thus, even when the signal level is fluctuated during the OB period of the CCD output by letting an electric charge overflow from the vertical CCD of a light receiving picture element part by inputting the excessive quantity of light to the CCD solid-state imaging device, this signal level can be almost equalized with the original black level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device, and more particularly to signal processing by a correlated double sample hold circuit (hereinafter also referred to as a CDS circuit) in the solid-state image pickup device.

[0002]

2. Description of the Related Art Conventionally, a correlated double sample and hold circuit (CDS circuit) having a configuration as shown in FIG. 5 has been generally used for the purpose of removing a clock in an output signal of a CCD solid state image pickup device and reducing noise. ing.

FIG. 5A shows an example of the structure of a CDS circuit in a conventional solid-state image pickup device.
Reference numeral 0 denotes a CDS circuit that performs signal processing of the output signal (CCD output) of the CCD solid-state image sensor, and a first sample hold circuit (1) 211 that samples and holds the reset level of the CCD output based on the pulse signal φCDS. A second sample and hold circuit (2) for sampling and holding the signal level of the CCD output based on the pulse signal φS
And 212.

Further, the CDS circuit 210 has the first
Of the sample and hold circuit 211, and a third sample and hold circuit (3) 213 that samples and holds the output of the sample and hold circuit 211 based on the pulse signal φS, and outputs of the second and third sample and hold circuits 212 and 213. Is subtracted by the subtractor 214. Here, the third sample hold circuit 213 is a CCD
Before the subtraction between the output reset level and the signal level, the C held by the first and second sample and hold circuits is held.
It is provided to match the phase of the CD output level.

FIG. 6 is a signal waveform diagram for explaining the operation of the CDS circuit 210. In the CDS circuit 210, the CCD output reset level (CCD output A period level) and the signal level (CCD output B period level) are set at the timings shown in FIG. The hold circuits 211 and 212 sample and hold, and the difference between these signal levels, that is, the signal component is taken out by the subtractor 214.

By such signal processing of the CCD output,
It is possible to remove the clock component in the CCD output and reduce noise.

FIG. 5B shows another structure of the CDS circuit in the conventional solid-state image pickup device.
220 is a pulse φCD reset level of CCD output
It has a clamp circuit 221 that clamps based on S, and a sample hold circuit 222 that samples and holds the output of the clamp circuit 211 based on the pulse signal φS.

In the CDS circuit 220 having such a structure,
After the reset level of the CCD output is clamped, the level of the signal period of the CCD output is sampled and held to perform the same signal processing of the CCD output as the CDS circuit 210.

In the CCD solid-state image pickup device, a portion where light-shielding pixels are arranged (hereinafter, also referred to as an OB portion), which is called an optical black portion (optical black portion), is an ordinary light-receiving pixel arrangement portion (light-receiving pixel). It is common to provide a signal level as a black reference from the light-shielded pixel when the iris control or the video signal processing is performed by being provided adjacent to the (part).

FIG. 7 is a diagram for explaining the structure of the OB portion. Reference numeral 300 denotes a CCD solid-state image pickup element, which is a light receiving pixel portion 300a in which light receiving pixels are arranged, and a position adjacent to the light receiving pixel portion. And a light-shielding pixel portion (OB portion) 300b in which light-shielding pixels are arranged.

The light receiving pixel portion 300a and the OB portion 3
00b includes a photodiode 301 corresponding to each pixel.
And a vertical CCD unit 310 that transfers the output signal of each photodiode by the drive signals φV1 to φV4.

Further, the CCD solid-state image pickup device 300 is provided with a horizontal CCD 320 for horizontally transferring the transfer signal from the vertical CCD 310 corresponding to each pixel column by the drive signals φH1 and φH2.
From the charge detection unit 330 as an output circuit.

By the way, in the CCD solid-state image pickup device having the OB portion as described above, there is a problem that electric charge leaks from the light receiving pixel portion to the OB portion. Therefore, as a method for preventing such leakage of electric charges, Japanese Patent Laid-Open No. Sho 60-
In Japanese Patent No. 109272, a horizontal CCD corresponding to each pixel is provided by separately providing an OB pixel portion and a light receiving pixel portion.
Also disclosed is a solid-state imaging device provided independently.

FIG. 8 shows an example of the overall circuit configuration of a conventional CCD solid-state image pickup device. In the figure, 40
Reference numeral 0 is a CCD solid-state image pickup device that picks up an image of a subject and outputs a video signal, and this is configured to perform exposure control using an electronic shutter function. This solid-state imaging device 400
Is a configuration in which light coming from a subject obtained through the optical lens 401 is photoelectrically converted by a CCD unit (CCD solid-state image sensor) 402, and further the CCD output is signal-processed by the CDS circuit 403 as described above. ing. That is, the C
By processing the CCD output in the DS circuit 403, the clock component in the CCD output is removed and noise is reduced.

In the solid-state image pickup device 400, the CDS
The output of the AGC circuit 404 is gain-controlled, the gamma correction circuit 405 performs gamma correction, and the black clip / pedestal processing circuit 406 performs signal processing. Then, in this solid-state imaging device 400,
The output of the processing circuit 406 is subjected to synchronous mix processing, and output as a video signal. Further, the solid-state imaging device 400 includes a detection circuit 408 which receives the CDS output as an input, and a C circuit based on the detection output.
It has a circuit 409 for performing drive control and exposure control of the CCD in the CD section.

The CCD section 402 has the above-mentioned OB portion, and the signal processing such as the gamma correction, the black clip, the pedestal and the like is based on the signal level from the OB portion, that is, the signal level is DC. It is done by clamping to the level. Further, also in the gain control in the AGC circuit 404 and the exposure control in the control circuit 409,
Signal detection is performed with the signal level from the OB portion as a reference.

[0017]

However, CCDs
In the solid-state image sensor, when spot light, the sun, etc. are imaged and extremely strong light is incident on the light receiving pixel portion, the charge generated in the light receiving pixel portion exceeds the capacity of the vertical CCD and the scanning period of the horizontal CCD. It overflows into the horizontal CCD,
Further, a phenomenon occurs in which electric charges overflow beyond the capacity of the horizontal CCD, and a considerable amount of electric charges are transferred during the electric charge transfer period (OB period) corresponding to the OB portion where the electric charges are essentially not transferred. The problem in this case will be described with reference to the output waveform of each part in the circuit configuration of FIG.

FIG. 9 is a diagram showing waveforms of CCD output, CDS output, and video output in the solid-state image pickup device shown in FIG. 8. FIG. 9A shows CCD output Xa and CDS output during normal operation. FIG. 9B shows Ya and the image output Va, and FIG. 9B shows the CCD output Xb and the CDS output Y when intense light is incident and the above-mentioned charge overflow phenomenon occurs.
b and the video output Vb are shown.

As shown in FIG. 9B, when the charge overflow phenomenon occurs, the signal level in the OB period at the CCD output becomes higher than usual, so that the blackened and sunk screen appears. Becomes

In the exposure control, since the signal level in the OB period is higher than usual, the signal level from the light receiving pixel portion obtained by comparison with this is lower than the actual signal level. In this case, the exposure time is controlled to be extended, and the charge overflow phenomenon is further promoted. Therefore, when the amount of light received in the light receiving pixel portion is large, the screen becomes black.

Although such a charge overflow phenomenon has been improved in the solid-state image pickup device described in Japanese Patent Laid-Open No. 60-109272, the CCD solid-state image pickup device itself has a special structure. It is necessary to drive the horizontal CCDs corresponding to the OB portion and the light receiving pixel portion at different timings, that is, the circuit configuration is complicated.

The present invention has been made in order to solve the above-mentioned problems, in which an excessive amount of light is incident on the CCD solid-state image pickup device, whereby charges overflow from the vertical CCD in the light-receiving pixel portion. Even if the charges due to photoelectric conversion are transferred during the OB period in one horizontal period, the OB
The output level from the CDS circuit during the period can be maintained at a level equivalent to the original black level, which allows an excessive light amount to the CCD solid-state image sensor without changing the configuration of the CCD solid-state image sensor. It is an object of the present invention to obtain a solid-state imaging device that can always perform good video signal processing and iris control regardless of incidence of light.

[0023]

A solid-state imaging device according to the present invention (claim 1) is a light-receiving pixel portion for photoelectrically converting incident light to generate photocharges, and a light-shielding pixel shielded against incident light. CCD solid-state imaging device having a portion, and the C
A correlated double sample hold circuit is provided which receives a CCD output from the CD solid-state image pickup device, samples and holds the reset level and the signal level of the CCD output, and performs signal processing of the CCD output.

Further, the solid-state image pickup device according to the present invention includes an abnormality detecting means for detecting an abnormality in the signal level corresponding to the light-shielded pixel portion in the CCD output, and the abnormality detection means in the output period corresponding to the light-shielded pixel portion in one horizontal period. Phase detection means for switching the phase at which the CCD output is sampled and held by the correlated double sample and hold circuit based on the output of the abnormality detection means, and an abnormality in the signal level corresponding to the light-shielded pixel portion is detected. When this is done, the correlated double sample and hold circuit is configured to sample and hold the reset level corresponding to the shaded pixel portion in the CCD output. Thereby, the above object is achieved.

A solid-state image pickup device according to the present invention (claim 2) is a CCD solid-state image pickup device having a light-receiving pixel portion for photoelectrically converting incident light to generate photocharges, and a light-shielding pixel portion shielded from incident light. Equipped with elements.

Further, the present solid-state image pickup device receives the CCD output from the CCD solid-state image pickup device, clamps the reset level at the CCD output to a reference voltage, and samples and holds the signal level of the CCD output clamped at the reset level. Then, a correlated double sample-and-hold circuit for performing signal processing of the CCD output, an abnormality detecting means for detecting an abnormality of a signal level corresponding to the light-shielded pixel portion in the CCD output, and the light-shielded pixel portion for one horizontal period. In the output period corresponding to
A phase switching means for switching the phase at which the CD output is sampled and held based on the output of the abnormality detecting means, and when the abnormality of the signal level corresponding to the light-shielded pixel portion is detected, the correlated double sample The hold circuit is configured to sample and hold the reset level corresponding to the light-shielded pixel portion in the CCD output. Thereby, the above object is achieved.

The operation of the present invention will be described below. According to the present invention (claims 1 and 2), an abnormality detecting means for detecting an abnormality in the signal level corresponding to the light-shielded pixel portion in the CCD output is provided, and when an abnormality in the signal level corresponding to the light-shielded pixel portion is detected. In the correlated double sample and hold circuit, the reset level corresponding to the light-shielded pixel portion in the CCD output is sampled and held. Therefore, when the excessive amount of light is incident on the CCD solid-state image pickup element, the vertical CCD of the light receiving pixel portion Even if the charge overflows and the charge is transferred by photoelectric conversion during the OB period in one horizontal period, the signal level of the CCD output during the OB period is sample-held by the correlated double sample-hold circuit. The reset level is sampled and held.

Therefore, even when an excessive amount of light is incident on the CCD solid-state image pickup device, the output level from the CDS circuit in the OB period can be maintained at a level almost equal to the original black level. This makes it possible to always perform good video signal processing and iris control without changing the configuration of the CCD solid-state image sensor to a special one, regardless of the incidence of an excessive amount of light on the CCD solid-state image sensor.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the basic principle of the present invention will be described. FIG. 1 is a diagram for explaining the basic configuration of a solid-state image pickup device of the present invention. In FIG. 1, reference numeral 100 denotes the solid-state image pickup device of the present invention. In addition to the CDS circuit 1 adopting the configuration shown in FIG. 5A or FIG. 5B, the OB period (1
Corresponding to the OB level abnormality detection circuit 3 for detecting an abnormality in the signal level in the output period corresponding to the light-shielded pixel portion in the horizontal period based on the difference between the reset level and the signal level in the OB period, and the light-shielded pixel portion. When an abnormal signal level is detected, the phase at which the CCD output is sampled and held by the CDS circuit is switched only during the OB period,
And a pulse switching circuit 2 that samples and holds the reset level. The OB level abnormality detecting means 3 and the pulse switching circuit 2 are supplied with a predetermined timing signal from the CCD drive timing generating circuit 102. Note that in FIG. 1, the signal processing circuit subsequent to the CDS circuit as shown in FIG. 8 is omitted.

With such a structure, the vertical CC of the light receiving pixel portion is generated by the incidence of an excessive amount of light on the CCD solid state image pickup device.
Even if the charge overflows from D and the signal level in the OB period of the CCD output fluctuates, the CDS output of the CDS circuit that removes the clock of the CCD output and reduces noise is originally the signal level in the OB period. It can be almost equal to the black level of.

Next, the basic operation of the solid-state image pickup device of the present invention will be briefly described with reference to the timing waveform chart of FIG. FIG. 2A shows the waveform of the CCD output Xa during the normal operation, the first and second sample hold pulses S1 and S.
2 and the waveform of the CDS output Ya are shown in FIG.
(B) is a waveform of CCD output Xb when an excessive amount of light is incident,
The waveforms of the first and second sample and hold pulses S1 and S2 and the waveform of the CDS output Yb are shown.

Usually, C in the solid-state image pickup device 100 is
In the DS circuit 1, the first sample hold pulse S
1 to sample and hold the reset level of the CCD output Xa, and the second sample and hold S2 to set CC
The signal level of the D output is sampled and held, and the difference between the reset level and the signal level is output as the CDS output Ya.

In such an operating state, when intense light is incident on the CCD solid-state image pickup device and charges overflowing from the light receiving pixel section are transferred inside the horizontal CCD, the CCD output is
The waveform Xb is as shown in FIG. At this time, in the normal operation state, the signal level in the OB period, which is almost equal to the reset level, has a considerable difference from the reset level, although there is a slight difference due to the induction of pulses and the like.

According to the present invention, when the difference between the signal level in the OB period and the reset level exceeds a certain level, the signal level in the OB period is determined to be abnormal, and the sample and hold of the signal level of the CCD output is held. The phase (timing) of the pulse is changed as shown by the pulse waveform S2 in FIG. Then, by such a phase change of the sample hold pulse, in the OB period,
The reset level of the CCD output is sampled and held. As a result, in the conventional CDS circuit, when the intense light is incident on the CCD solid-state image sensor, the CDS output is generated as shown in FIG.
As shown by the dotted line of the waveform Yb in (b), what is largely deviated from the original black level (portion) can be made to have a level almost equal to the original black level as shown by the solid line of the waveform Yb. it can.

Hereinafter, embodiments of the present invention will be described. FIG. 3 is a diagram showing a specific circuit configuration of a main part of a solid-state imaging device according to an embodiment of the present invention (claim 2). In the figure, the same reference numerals as those in FIG. 1 are explanations of the basic principle of the present invention. The same thing as that shown in is shown. Note that FIG.
Then, the CCD drive timing generation circuit 10 in FIG.
2, and the circuit configuration of the latter stage of the CDS circuit in FIG. 8 is omitted. Further, FIG. 4 is a diagram for explaining the operation of the solid-state imaging device according to the above-described embodiment, and shows the signal waveform in each circuit constituting the solid-state imaging device.

In the figure, reference numeral 100 denotes the solid-state image pickup device of this embodiment, which is a light-receiving pixel portion 101a for photoelectrically converting incident light to generate photocharges, a light-shielding pixel portion 101b shielded from incident light, and a horizontal CCD 101c. CC having the same configuration as the solid-state image sensor shown in FIG.
It has a D solid-state image pickup device 101 and a correlated double sample hold circuit (CDS circuit) 1 which receives CCD output from the CCD solid-state image pickup device and performs signal processing of the CCD output.

The solid-state image pickup device 100 has the C
An OB level abnormality detection circuit 3 for detecting an abnormality in the signal level (signal level in the OB period) corresponding to the light-shielded pixel portion in the CD output, and corresponding to the light-shielded pixel portion in one horizontal period based on the abnormality detection output. The pulse switching circuit (phase switching means) that switches the sample hold pulse supplied to the CDS circuit 1 in the output period (OB period) during
2, the CDS circuit 1 is configured to sample and hold the reset level in the CCD output corresponding to the light-shielded pixel portion when an abnormality in the signal level corresponding to the light-shielded pixel portion is detected.

Here, the CDS circuit 1 includes a clamp circuit 1a for clamping the CCD output from the CCD solid-state image pickup device 101 to a clamp reference voltage, and the clamped C.
It is composed of a sample hold circuit 1b which samples and holds the CD output. The clamp circuit 1a is
A clamp capacitor 4 for receiving the CCD output X, a buffer amplifier 7 for receiving the CCD output via the clamp capacitor 4, a reference power source 6 for generating the clamp reference voltage, and inputs of the reference power source and the buffer amplifier 7. And an analog switch 5 whose opening and closing is controlled by the first sample and hold pulse S1. The sample-hold circuit 1b is connected between the hold capacitor 9 that holds the output of the buffer amplifier 7 and the output terminal of the buffer amplifier 7 and the hold capacitor 9, and is connected by the output Ph of the pulse switching circuit 2. It is composed of an analog switch 8 which is controlled to be opened and closed, and a buffer amplifier 10 which outputs the voltage held in the hold capacitor as a CDS output Y.

The pulse switching circuit 2 receives the output of the OB abnormality detection circuit 3 and the OB period designating pulse Pd indicating the OB period in one scanning period at its high level, and the AND circuit 12 and the AND circuit. The output of the switch 12 includes a selector switch 11 for switching the control signal of the analog switch 8. Here, the output terminal 11c of the changeover switch 11 is connected to the control input of the analog switch 8, and the first input terminal 11 thereof is
The first sample-and-hold pulse S1 whose pulse section is synchronized with the reset period for sampling and holding the reset level of the CCD output is supplied to a, and the signal level of the CCD output is supplied to the second input terminal 11b. A second sample-hold pulse S2 whose pulse period is synchronized with the signal period for sample-holding is supplied.

The OB level abnormality detection circuit 3 is a CCD
It has a clamp circuit 3a that clamps the CCD output from the solid-state image sensor 101 to a clamp reference voltage, and a sample hold circuit 3b that samples and holds the clamped CCD output.

The clamp circuit 3a generates a clamp capacitor 15, which clamps the CCD output from the CCD solid-state image pickup device 101, a buffer amplifier 19 which receives the CCD output via the clamp capacitor 15, and the clamp reference voltage. The reference power source 17 is connected between the input to the buffer amplifier 19 and the reference power source 17, and
And an analog switch 16 whose opening and closing is controlled by the output Pf of the AND circuit 13. The sample-hold circuit 3b is connected between the hold capacitor 21 that holds the output of the buffer amplifier 19 and the output end of the buffer amplifier 19 and the hold capacitor 21, and the output Pg of the second AND circuit 14 is connected. It is composed of an analog switch 20 whose opening and closing is controlled by. The voltage held in the hold capacitor 20 is supplied to one input of the voltage comparator 22.

Here, in the first AND circuit 13,
As its input, the first sample hold pulse S
1 and OB period designating pulse Pd are supplied, and the second AND circuit 14 is supplied with the second sample hold pulse S2 and the OB period designating pulse Pd as its inputs.

Further, the reference power supply 17 is connected in parallel with first and second resistance elements 18a and 18b connected in series, and the connection point of these resistance elements is the voltage comparator 2 described above.
2 is connected to the other input. At the connection point, the resistance values of the both resistance elements are set so that a voltage slightly lower than the clamp reference voltage generated by the reference power supply 17 is generated. Further, by adjusting the voltage generated at the connection point, it is possible to determine how large the fluctuation of the signal level during the OB period is to be determined to be abnormal.

In the present embodiment as well, the first and the first
The second sample hold pulses S1 and S2 and the OB period instruction pulse Pd are supplied to each circuit from the CCD drive timing generation circuit 102 shown in FIG.

Next, the function and effect will be described. In the solid-state imaging device 100 having such a configuration, when the CCD output of the CCD solid-state imaging device 101 is input to the CDS circuit 1, the CCD output of the clamp circuit 1a is synchronized with the timing of the first sample hold pulse S1. , Is clamped to the reference voltage generated by the reference power supply 6. In the sample hold circuit 1b, the clamped C
The CD output is sampled and held at the timing of the CDS sample and hold pulse Ph which is the control signal from the changeover switch 11.

During normal operation, the change-over switch 11 outputs the second sample-hold pulse S2 for sample-holding the signal level of the CCD output. Therefore, both the video period and the OB period are outputted. In both cases, a voltage corresponding to the difference voltage between the reset level and the signal level is output from the CDS circuit 1 as the CDS output Y.

Further, in the OB level abnormality detection circuit 3, O
By the B period instruction pulse Pd, the clamp circuit 3a and the sample hold circuit 3b operate only during the OB period.
Then, in the reset period of the OB period, the CC
The D output is clamped to the clamp reference voltage generated by the reference power source 17 by the clamp circuit 3a, and in the signal period of the OB period, the signal level of the CCD output is sampled and held by the sample and hold circuit 3b and sampled and held. The signal level in the OB period is supplied to one input of the voltage comparator 22. This voltage comparator 2
The other input of 2 is supplied with a voltage slightly lower than the clamp reference voltage.

In the normal operation, the reset level and the signal level in the OB period are almost equal to each other, so that the sample hold result is almost equal to the clamp reference voltage, and the voltage comparator 22 does not output the abnormality detection signal.

On the other hand, when intense light is incident on the CCD solid-state image pickup device and photocharges are transferred during the OB period, the signal level during the OB period is reset as shown by the dotted line of CCD output X in FIG. The potential is considerably lower than the level. Therefore, the sample hold result of the CCD output by the sample hold circuit 3b becomes lower than the clamp voltage, and as the output of the voltage comparator 22, the abnormality detection signal of the signal level in the OB period is output.

Upon receipt of this abnormality detection output, the output of the changeover switch 2 is the second sample hold pulse S2.
From the first sample-hold pulse S1 to the CDS sample-hold pulse Ph.
The waveform is as shown by the dotted line in FIG. With this, CD
The sample hold circuit 1b of the S circuit 1 samples and holds the reset level during the OB period.
Even if an excessive amount of light enters the CCD solid-state image sensor, C
The DS output Y is the OB at the normal time, as shown by the dotted line in FIG.
The level is equivalent to the signal level (solid line) during the period.

In the above embodiment, as the CDS circuit, the reset level of the CCD output from the CCD solid-state image pickup device 101 is clamped to the reference voltage during normal operation.
When the signal level of the CCD output with the reset level clamped is sampled and held, and when an abnormality of the signal level corresponding to the light-shielded pixel portion is detected, the CCD output is replaced with the signal level corresponding to the light-shielded pixel portion. Although the configuration in which the reset level corresponding to the light-shielded pixel portion of the output is sampled and held is shown, the configuration of the CDS circuit is not limited to this.

For example, the CDS circuit samples and holds the reset level and the signal level of the CCD output from the CCD solid-state image pickup device 101 during normal operation, and when an abnormality in the signal level corresponding to the light-shielded pixel portion is detected, Instead of the signal level corresponding to the light-shielded pixel portion of the CCD output, the reset level corresponding to the light-shielded pixel portion of the CCD output may be sample-held. In this case, the solid-state imaging device corresponds to the invention of claim 1, and also in this case, the same effect as that of the above embodiment can be obtained.

[0053]

As described above, according to the solid-state image pickup device of the present invention, the abnormality detecting means for detecting the abnormality of the signal level corresponding to the light-shielded pixel portion in the CCD output, and the one based on the abnormality detection output In the output period corresponding to the light-shielded pixel portion in the horizontal period, there is provided a phase switching means for switching the phase at which the CCD double sampling and holding is performed by the correlated double sample-hold circuit, and the signal level corresponding to the light-shielded pixel portion is provided. When the abnormality is detected, the correlation double sample and hold circuit is configured to sample and hold the reset level corresponding to the light-shielded pixel portion in the CCD output, so that the CCD solid-state image sensor has a special configuration. Always perform good video signal processing and iris control without changing, regardless of the incidence of excessive light on the CCD solid-state image sensor. An effect that can be obtained.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the basic configuration of a solid-state imaging device according to the present invention.

FIG. 2 is a waveform diagram for explaining the basic operation of the solid-state imaging device of the present invention, and FIG. 2 (a) is a waveform diagram during normal operation.
2 shows the waveforms of the CD output Xa, the first and second sample and hold pulses S1, S2, and the CDS output Ya, and FIG.
(B) shows the CCD output Xb, the first and second sample-hold pulses S1, S2, and CD when an excessive amount of light is incident.
The waveform of the S output Yb is shown.

FIG. 3 is a diagram showing a specific circuit configuration of a main part of the solid-state imaging device according to the embodiment of the present invention.

FIG. 4 is a diagram for explaining the operation of the solid-state imaging device according to the above-described embodiment, showing a signal waveform in each circuit constituting the solid-state imaging device.

FIG. 5 is a diagram for explaining signal processing by a CDS circuit in a conventional CCD solid-state imaging device, and FIG.
Is a configuration of a CDS circuit that samples and holds the reset level and the signal level of the CCD output, FIG.
Shows the configuration of a CDS circuit for sampling and holding a signal obtained by clamping the reset level of the CCD output.

FIG. 6 is a signal waveform diagram for explaining the operation of a CDS circuit in a conventional CCD solid-state imaging device.

FIG. 7 is a diagram showing a configuration of a CCD unit (CCD solid-state imaging device) in a conventional CCD solid-state imaging device.

FIG. 8 is a block diagram showing an overall configuration of a conventional CCD solid-state imaging device.

9A and 9B are diagrams for explaining a problem in a conventional CCD solid-state imaging device, FIG. 9A shows a signal waveform during a normal operation, and FIG. 9B shows a signal waveform when an excessive amount of light is incident. Shows.

[Explanation of symbols]

 1 CDS circuit 1a, 3a Clamp circuit 1b, 3b Sample and hold circuit 2 Pulse switching circuit 3 OB level abnormality detection circuit 4,15 Clamp capacitor 5, 8, 16, 20 Analog switch 6,17 Reference power supply 7, 10, 19 Buffer amplifier 9, 21 Hold capacitor 11 Changeover switch 12, 13, 14 AND circuit 18a, 18b Resistance element 22 Voltage comparator 100 Solid-state image pickup device 101 CCD solid-state image pickup element 101a Light-receiving pixel portion 101b Light-shielding pixel portion 101c Horizontal CCD 102 CCD drive timing generation circuit Pd OB period instruction pulse Pf First detection sample hold pulse Pg Second detection sample hold pulse Ph CDS sample hold pulse S1, S2 First and second sample hold pulse X, Xa, b CCD output Y, Ya, Yb CDS output

Claims (2)

[Claims] 1. A CCD solid-state image pickup device having a light-receiving pixel portion for photoelectrically converting incident light to generate a photocharge, and a light-shielding pixel portion shielded from incident light, and a CCD output from the CCD solid-state image pickup element. Received the CC
Correlation double sample and hold circuit for sample-holding reset level and signal level at D output and performing signal processing of the CCD output, and abnormality detection for detecting abnormality of signal level corresponding to light-shielded pixel portion at the CCD output Means and the output period of one horizontal period corresponding to the light-shielded pixel portion, the phase at which the CCD double sampling and holding is performed by the correlated double sample and hold circuit is switched based on the output of the abnormality detecting means. A phase switching means, and when an abnormality in the signal level corresponding to the light-shielded pixel portion is detected, the correlation double sample hold circuit
A solid-state imaging device configured to sample and hold a reset level corresponding to a shaded pixel portion in an output. 2. A CCD solid-state image pickup device having a light-receiving pixel portion for photoelectrically converting incident light to generate a photocharge, and a light-shielding pixel portion shielded from incident light, and a CCD output from the CCD solid-state image pickup element. Received the CC
Correlation double sample and hold circuit that clamps the reset level at the D output to a reference voltage, samples and holds the signal level of the CCD output that clamps the reset level, and performs signal processing of the CCD output, and light shielding at the CCD output Abnormality detection means for detecting an abnormality in the signal level corresponding to the pixel portion, and in the output period corresponding to the light-shielded pixel portion in one horizontal period, the correlation double sample and hold circuit performs sample hold of the CCD output. A phase switching means for switching the phase to be performed based on the output of the abnormality detecting means, and when an abnormality in the signal level corresponding to the light-shielded pixel portion is detected, the correlation double sample hold circuit
A solid-state imaging device configured to sample and hold a reset level corresponding to a shaded pixel portion in an output.