JPH09261230A - Cell transmission method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the cell transmission method sending cells with high priority in precedence over usual cells in the cell transmission method dividing cells from a high speed transmission line and sending received cells through a low speed transmission line. SOLUTION: Upon the receipt of a priority cell by a high speed cell reception circuit 11, even when cells disassembled from usual cells generated by a cell disassembly circuit 15 are outputted from a low speed cell transmission circuit 15 are outputted from a low speed cell transmission circuit 18, the output is tentatively stopped, the received priority cells are disassembled by a priority cell disassembly circuit 16 and the disassembled cells are generated and outputted from the low speed cell transmission circuit 18 in a form of a interruption to the disassembly cell of the usual cell being outputted. Upon the receipt of disassembled cells of priority cells by a low speed cell reception circuit 20, even when part of disassembled cells of usual cells is received earlier, a cell check assembly circuit 21 assembles the disassembled cells of the received priority cells with priority to generate the original priority cells, which are outputted from a high speed cell transmission circuit 25.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell transmission method, and more particularly to a cell transmission method for dividing a cell transmitted through a high speed transmission line and transmitting the divided cell through a low speed transmission line.

[0002]

2. Description of the Related Art In packet communication, transmission information is divided into blocks (packets) of an appropriate size, control information such as a destination is added, and the packets are transferred through a communication line. This communication line is generally composed of multiple transmission lines with different transmission rates, and packets are transferred from a high-speed transmission line with a high transmission speed to a low-speed transmission line with a low transmission speed or from a low-speed transmission line to a high-speed transmission line. Is transmitted. However, there are cases where the packet transmitted through the high speed transmission line cannot be transmitted as it is through the next low speed transmission line. For example, the low-speed transmission line is a time division multiplex transmission line that transmits information in time slots, and the size of the packet that can be transmitted in one time slot is smaller than the size of the packet transmitted by the high-speed transmission line. If it is small, the packet transmitted through the high speed transmission line cannot be transmitted as it is in one time slot of the time division multiplex transmission line.

Therefore, when a packet that has been conventionally transmitted by a high-speed transmission line cannot be transmitted by one time slot of the time division multiplex transmission line, the packet is transmitted by one time slot on the transmission side of the time division multiplex transmission line. It is divided into packets of a size that can be inserted into a slot, the top information indicating the beginning is added to the first packet of the divided packets, and the last information indicating the end is given to the last packet and the size of the packet. Is added to the time division multiplex transmission line sequentially. Then, on the receiving side, the divided packets sequentially transmitted by the time division multiplexing transmission line are input, and the original packet is assembled based on the head information, the final information and the capacity information added to the packet, and the next packet is assembled. It was output to a high-speed transmission line.

[0004]

However, since the transmission speed of the time division multiplex transmission line is lower than that of the high speed transmission line, it takes a longer time to transmit all the divided packets than in the case of the high speed transmission line. For this reason, there is a case where packets are continuously received from the high-speed transmission path and the next packet is received before the division and output of the previously received packet are completed. The conventional packet transmission method divides the packets transmitted through the high-speed transmission line in the order in which they are received and outputs them to the time division multiplex transmission line.Therefore, the information in the next packet becomes the information in the previous packet. In comparison, if the delay due to transmission is a problem, that is, even if the priority of the next packet is higher than that of the previous packet, the next packet is kept waiting until the division and output of the previous packet are completed, It had the drawback of arriving late to the other party.

A drawback of such a packet transmission method is that ATM (As) that transfers transmission information by dividing the transmission information into fixed-length blocks (cells) and adding control information such as the destination
The same occurred in the cell transmission method by the low-speed transmission line in synchronous transfer mode) communication.

The present invention solves the above-mentioned drawbacks of the prior art, and when a cell with a high priority is received from a high speed transmission line, a cell with a low priority received previously is being transmitted through the low speed transmission line. Even if the cell transmission method is temporarily stopped, the cell having the higher priority is preferentially transmitted through the low-speed transmission path to prevent the information having the higher priority from arriving late to the other party. With the goal.

[0007]

According to the present invention, in order to solve the above-mentioned problems, on the transmitting side, the priority order of a cell received from a high-speed transmission line is determined by the information in the header of the cell, and the priority order is determined. Separately, the cells are independently divided into blocks of a predetermined size, and divided cells are generated by adding information indicating the priority order corresponding to each of the blocks, and the generated divided cells are classified according to the priority order. Among the divided cells with the highest priority among them, even if other divided cells are being output, they are preferentially output to the low-speed transmission line by interrupting them, and the receiving side sequentially outputs the divided cells input from the low-speed transmission line. It is temporarily stored in a memory, and the divided cells are assembled into the original cells in the order in which all the divided cells necessary for assembling the original cells are prepared and output to the next high-speed transmission line.

Further, according to the present invention, the transmitting side divides the cell received from the high-speed transmission line into blocks of a predetermined size to generate divided cells and outputs the divided cells to the low-speed transmission line. A cell transmission method in which divided cells input from a low-speed transmission line are assembled into an original cell and output to the next high-speed transmission line, in which the user information contained in the cell is predetermined on the transmission side. When it is detected that the information is the information in the header of the cell, only the header is extracted from the cell, and the divided cell is generated by adding the information indicating that the information is deleted to the header to generate the low speed. When the information is output to a transmission line and the receiving side detects the information from the divided cells input from the low-speed transmission line, the header is extracted from the divided cells and the information prepared in advance in the header is extracted. It is intended to assemble the original cell by the addition.

Further, according to the present invention, on the transmission side, a cell received from the high-speed transmission line is divided into blocks of a predetermined size to generate divided cells and output to the low-speed transmission line. A cell transmission method for assembling a divided cell input from a low-speed transmission line into an original cell and outputting the cell to the next high-speed transmission line, the method comprising: when the transmission side does not receive a cell from the high-speed transmission line. , A divided cell is generated by adding information indicating that fault monitoring data is included in a block of a predetermined size that accommodates fault monitoring data, and the divided cell is output to the low-speed transmission path. When the information is detected from the divided cells input from the low speed transmission line, the fault monitoring data is extracted from the divided cells.

Further, according to the present invention, on the transmitting side, a cell received from the high-speed transmission line is divided into blocks of a predetermined size to generate divided cells and output to the low-speed transmission line. A cell transmission method for assembling divided cells input from a low-speed transmission line into original cells and outputting the cells to the next high-speed transmission line, in which the last divided block is larger than the predetermined size on the transmission side. When it is smaller, the fault monitoring data is added to the last block to form the block of the predetermined size, and then the divided cells are generated and output to the low-speed transmission line. The fault monitoring data is extracted from the last divided cell input from.

Further, according to the present invention, on the transmitting side, a cell received from the high-speed transmission line is divided into blocks of a predetermined size to generate divided cells, and the divided cells are output to the low-speed transmission line. A cell transmission method for assembling a divided cell input from a low-speed transmission line into an original cell and outputting the original cell to the next high-speed transmission line, wherein the transmission side includes failure information in all of the generated divided cells. And the reception side extracts the failure information and the like from all of the divided cells input from the low-speed transmission path.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of a cell transmission method according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram showing a configuration example of an ATM communication system to which an embodiment of the cell transmission method according to the present invention is applied. This ATM communication system is an ATM switching main unit 3
And a remote ATM switching device 4 installed at a remote place, a high-speed cell transmission line 5 having a high transmission rate (for example, 25 Mbps) and a time division multiplexing transmission line 7 having a low transmission rate (for example, 8 Mbps).
) And a high-speed cell transmission line 6 (for example, 25 Mbps), and a cell disassembly and assembly control device 1 is provided between the high-speed cell transmission line 5 and the time-division multiplex transmission line 7 to connect the time-division multiplex transmission line 7 and the high-speed The cell disassembly / assembly control device 2 is provided between the cell transmission line 6 and the cell transmission line 6. Then, the ATM exchange main unit 3 and the remote AT
The M switching device 4 exchanges information with each other by inputting / outputting cells to / from the high speed cell transmission line 5 or 6.
The cell disassembling and assembling control devices 1 and 2 perform high speed cell transmission line 5 by buffering and disassembling and assembling cells.
Alternatively, the transmission speeds of 6 and the time division multiplex transmission line 7 are matched.

First, a configuration example of a cell transmitted by the high speed cell transmission line 5 or 6 and a configuration example of a divided cell transmitted by the time division multiplexing transmission line 7 will be described with reference to FIGS.

FIG. 3 (a) is an ATM switching main unit 3 shown in FIG.
FIG. 3 is a diagram showing a configuration example of a cell output from the remote ATM switching apparatus 4 and transmitted by the high speed cell transmission line 5 or 6. In the present embodiment, the cell 26 is a 5-byte header 26A including a virtual path, a cell identifier, header error detection information and the like.
And a 48-byte user information block 26B containing user information or control information and a fixed-length cell of 53 bytes. The information contained in the header 26A can be used to identify whether the information contained in the user information block 26B is user information or control information, and whether it is invalid or fixed data such as empty cells. it can.

FIG. 3 (b) is a diagram showing an example of the configuration of a divided cell which is output from the cell disassembly / assembly control device 1 or 2 shown in FIG. 2 and transmitted by the time division multiplex transmission line 7. If the size of a divided cell that can be transmitted in one time slot of the time division multiplex transmission line 7 is smaller than the size of the cell transmitted by the high speed cell transmission line 5 or 6, the cell transmitted by the high speed cell transmission line 5 or 6 Cannot be transmitted through the time division multiplex transmission line 7 as it is, so it is necessary to divide the cell into a plurality of divided cells. Therefore, the size of a divided cell that can be transmitted in one time slot of the time division multiplex transmission line 7 in this embodiment is set to 9 bytes, and 53by shown in FIG.
The cell 26 of te is divided into 9-byte divided cells shown in Fig. 3 (b).
A method of generating 27 to 33 will be described.

First, the 53-byte cell 26 shown in FIG. 3 (a) is divided by 8 bytes in order from the beginning, and six 8-byte divided cell user information blocks 27C to 32C and 1 shown in FIG. 3 (b).
It is divided into 5 byte blocks (the divided cell user information blocks 29C to 32C are not shown). Next, at the beginning of the divided cell user information blocks 27C to 32C, 4bit divided cell sequence number blocks 27A to 32A and 4bit
9 by adding the divided cell control information blocks 27B to 32B
The divided cells 27 to 32 of te are generated (1 byte = 8 bits). However, for the last divided 5-byte block, a 3-byte divided cell special data block is added after that to generate an 8-byte divided cell user information block 33C. Then, a 4-bit divided cell sequence number block 33A and a 4-bit divided cell control information block 33B are added to the head of the divided cell user information block 33C to generate a 9-byte divided cell 33. Since the last divided block is 5 bytes, a 9-byte divided cell 33 is generated by adding a 3-byte divided cell special data block, and the size of the divided cell that can be transmitted in one time slot is 9
It effectively uses bytes.

Here, the divided cell sequence number block
27A to 33A contain sequence numbers. This sequence number is a continuous number that displays the order of the divided cells 27 to 33, and also displays the priority of the cells. On the receiving side, this sequence number determines whether or not all the divided cells necessary to assemble the original cell have been received,
Also, it is determined whether or not to assemble with priority. In this embodiment, sequence numbers 8H to EH are given to divided cells 27 to 33 generated by dividing a cell with a high priority (priority cell), and other cells (normal cells) are divided. Sequence numbers 1H to 7H are given to the generated divided cells 27 to 33. The priority order is set in advance corresponding to the contents of the header 26A of the cell 26.

In this embodiment, two types of priority, priority and normal, are set, but two or more types may be set.
When setting two or more types of priority or when the number of divided cells increases to 7 or more, it is necessary to increase the divided cell sequence number blocks 27A to 33A to 4 bits or more. Further, in the present embodiment, since the number of divided cells is 7 as described above, the final divided cell can be identified by detecting the sequence number 7H or EH on the receiving side. However, in the case of dividing a variable-length packet, the number of divided cells changes, so it is necessary to add information indicating the final divided packet to the final divided packet.

Further, divided cell control information blocks 27B to 33
B accommodates various control information and failure information necessary for operating the time division multiplex transmission line 7 and the cell disassembly / assembly control device 1 or 2. By adding a divided cell control information block to all divided cells, control information, failure information, etc. are sent periodically. The above-mentioned divided cell special data block contains special data for monitoring a failure of the time division multiplex transmission line 7 and the cell disassembly / assembly control device 1 or 2.

FIG. 4 shows time division multiplexing transmission when the information contained in the user information block 26B of the cell 26 transmitted by the high speed cell transmission line 5 or 6 is invalid or fixed data such as an empty cell. It is a figure which shows the structural example of the division cell transmitted by the path | pass 7. FIG. 4 (a) shows an example of the structure of the cell 26 transmitted by the high speed cell transmission line 5 or 6, which is similar to the cell 26 shown in FIG. 3 (a). However, the information contained in the user information block 26B of the cell 26 is invalid or fixed data such as an empty cell. FIG. 4B is a diagram showing a configuration example of the divided cells transmitted by the time division multiplexing transmission line 7.

First, only the 5-byte header 26A is extracted from the cell 26, and the user information block 26B is discarded. Then, as shown in FIG. 4 (b), by adding a special data block of 3 bytes after the extracted header 26A, 8
Generate a divided cell user information block 34C of byte.
Then, at the beginning of the divided cell user information block 34C, a 4-bit divided cell sequence number block 34A and a 4-bit divided cell control information block 34B are added.
A byte divided cell 34 is generated. Here, the divided cell sequence number block 34A includes the user information block 26B.
It contains a sequence number, such as FH, that indicates that the information within was invalid or fixed data. The divided cell control information block 34B contains the same information as in the case of FIG. 3 (b). The special data block in the divided cell user information block 34C contains special data for monitoring a failure of the time division multiplex transmission line 7 and the cell disassembly / assembly control device 1 or 2.

On the receiving side, when the sequence number of the received divided cell is FH, the header 26A is extracted from the divided cell user information block 34C of the received divided cell 34. Then, in the header 26A, a user information block 26B containing invalid or fixed data prepared in advance.
Is added to assemble the original cell 26 shown in FIG. 4 (a). Since invalid or fixed data is determined in a predetermined pattern and can be prepared in advance on the receiving side, it is excluded from the transmission target of the time division multiplex transmission line 7 to reduce the amount of transmission information, and other cells can be reduced. And the effective use of the time division multiplex transmission line 7 are realized.

FIG. 5 is a diagram showing a configuration example of a divided cell to be output to the time division multiplex transmission line 7 when the cell is not transmitted from the high speed cell transmission line 5 or 6. This split cell
35 is a 4-bit divided cell sequence number block 35A,
4bit divided cell control information block 35B and 8byte
This is a 9-byte divided cell constituted by the divided cell user information block 35C. Here, the divided cell sequence number block 35A contains a sequence number that can be distinguished from other divided cells, for example, 0H. The divided cell control information block 35B contains the same information as in the case of FIG. 3 (b). The divided cell user information block 35C contains special data for monitoring a failure of the time division multiplex transmission line 7 and the cell disassembly / assembly control device 1 or 2. The above-mentioned special data is transmitted when there is no cell to be transmitted, and the time division multiplex transmission line 7 is effectively used.

Next, the cell disassembly / assembly control apparatus 1 shown in FIG. 2 for dividing the cells and assembling the divided cells described above.
Will be described in detail. The configuration and operation of the cell disassembly / assembly control device 2 are the same as those of the cell disassembly / assembly control device 1, and therefore a description thereof will be omitted.

FIG. 1 is a block diagram showing a configuration example of the cell disassembly / assembly control device 1. This cell disassembly and assembly control device 1
Divides the cell 26 transmitted by the high-speed cell transmission line 5 into divided cells 27 to 33 and outputs the divided cells to the time division multiplex transmission line 7 and the divided cells 27 to 33 transmitted from the time division multiplex transmission line 7. 33 is assembled into the original cell 26 and the high-speed cell transmission line 5
Output to First, a case where the cell 26 transmitted through the high speed cell transmission line 5 is divided into divided cells 27 to 33 and output to the time division multiplex transmission line 7 will be described.

The high-speed cell receiving circuit 11 of the cell disassembling and assembling control device 1 includes the high-speed cell transmission line 5 connected to the input side as shown in FIG.
The cell 26 having the configuration shown in (a) is received and output to the memory control circuit 12 connected to the output side. The memory control circuit 12 inputs the cell 26 output from the fast cell receiving circuit 11 and identifies the priority order based on the information contained in the header 26A. Then, when the cell 26 is a normal cell, it is output to the cell memory 13 connected to the output side, and when the cell 26 is a priority cell, to the priority cell memory 14 connected to the output side. Output. Further, the memory control circuit 12 outputs the control signal for controlling the operation of each circuit, the synchronization signal for outputting the divided cells to the time division multiplex transmission line 7, and the assembled cell to the high speed transmission line 5. Generates and outputs the synchronization signal of.

The cell memory 13 and the priority cell memory 14 are
Each has a memory capable of storing one or more cells, the cell memory 13 temporarily stores the normal cells from the memory control circuit 12, and the priority cell memory 14 stores the priority cells from the memory control circuit 12. Stores temporarily and both function as a buffer. Also, the cell memory 13 and the priority cell memory
14 constantly reports the number of stored cells to the memory control circuit 12. When the cell memory 13 or the priority cell memory 14 stores one or more cells 26, the memory control circuit 12 sends a control signal to the cell disassembly circuit 15 or the priority cell disassembly circuit 16, and the cell memory 13 or the priority cell memory The cell 26 stored in 14 is read to instruct to generate a divided cell. Cell memory 13 and priority cell memory 14 are cells 26
When not stored, a control signal is sent to the cell disassembly circuit 15 to instruct to generate the divided cells shown in FIG.

Cell disassembly circuit 15 or priority cell disassembly circuit 16
According to the instruction of the control signal from the memory control circuit 12,
Cell memory 13 or priority cell memory connected to the input side
The cells 26 are read one by one from 14, and it is discriminated whether or not the information in the user information block 26B is invalid or fixed data such as empty cells based on the information contained in the header 26A. If the data is not invalid or fixed, in this embodiment, the cell 26 is divided into seven divided cells shown in FIG. 3 (b).
Produces 27-33. If the data is invalid or fixed, only the header 26A is extracted from the cell 26 to generate the divided cell 34 shown in FIG. 4 (b). However, if no cell is stored in the cell memory 13 or the priority cell memory 14,
According to the instruction of the control signal from the memory control circuit 12, FIG.
The divided cell 35 shown in is generated.

Next, the cell disassembly circuit 15 or the priority cell disassembly circuit 16 reports to the memory control circuit 12 that the generation of the divided cells has been completed. The memory control circuit 12 sends a control signal to the reporting cell disassembly circuit 15 or the priority cell disassembly circuit 16 to output the generated divided cells, and also sends a control signal to the selector 17 to disassemble the cell. Circuit 15
Alternatively, an instruction is issued to select the output of the priority cell disassembly circuit 16. The cell disassembling circuit 15 or the priority cell disassembling circuit 16 sequentially outputs the generated divided cells to the selector 17 connected to the output side according to the synchronization signal output from the memory control circuit 12. If two or more cell priorities are provided, a system including the priority cell memory 14 and the priority cell disassembling circuit 16 may be added in accordance with the number of types.

The selector 17 inputs the divided cells output from the cell disassembling circuit 15 or the priority cell disassembling circuit 16 according to the instruction of the control signal from the memory control circuit 12, and the low speed cell sending circuit 18 connected to the output side. Output to. The low-speed cell transmission circuit 18 outputs the divided cells from the selector 17 to the time division multiplex transmission line 7 connected to the output side and transmits them to the cell disassembly and assembly control device 2 of the other party. It should be noted that the cell disassembly circuit 15 or the priority cell disassembly circuit 16 reports the fact to the memory control circuit 12 when the output of the generated divided cells is completed.

Next, while the cell disassembling circuit 15 is outputting the divided cells 27 to 33 to the selector 17, the high speed cell receiving circuit 11
A case will be described in which a priority cell having a high priority is received from the fast cell transmission line 5.

The memory control circuit 12 is a fast cell receiving circuit 11
The priority cell output from is input, and this is output to the priority cell memory 14. The priority cell memory 14 temporarily stores the priority cell in the memory. Then, the memory control circuit 12
A control signal is sent to the priority cell disassembling circuit 16 to instruct the priority cell memory 14 to read the priority cell and generate a divided cell. When the cell disassembling circuit 15 receives a report from the priority cell disassembling circuit 16 that the generation of the divided cells has been completed.
To instruct to suspend the output of the divided cells generated by sending a control signal to the. Next, a control signal is sent to the selector 17 to instruct to select the output of the priority cell disassembling circuit 16, and a control signal is sent to the priority cell disassembling circuit 16 to output the generated divided cells. .

In this way, the divided cells of the priority cell are
It is preferentially output to the time division multiplex transmission line 7 by interrupting the divided cells of the normal cell being output. Memory control circuit 12
Upon receiving a report from the priority cell disassembling circuit 16 that the output of the divided cells has been completed, a control signal is sent to the cell disassembling circuit 15 to instruct to restart the output of the remaining divided cells, and to the selector 17. A control signal is sent to instruct to select the output of the cell disassembly circuit 15.

By the way, as described above, the transmission speed of the time division multiplex transmission line 7 is lower than that of the high speed cell transmission line 5. Therefore, the memory of the cell memory 13 or the priority cell memory 14 may overflow depending on its capacity. Therefore, in this embodiment, the buffer busy control circuit 19 is provided to prevent overflow.

More specifically, the memory control circuit 12 constantly monitors the use status of the memory by the reports sent from the cell memory 13 and the priority cell memory 14. When the high-speed cell receiving circuit 11 receives the next cell when there is a possibility of overflow, the memory control circuit 12 outputs the cell from the high-speed cell receiving circuit 11 to the buffer busy control circuit 19 and outputs a control signal. Send out and instruct the cell to send it back to the sender as a receive buffer busy (receive cell memory overflow). Buffer busy control circuit 19
According to the instructions of the memory control circuit 12,
Selector 24 that inputs cells from 12 and is connected to the output side 24
In addition to outputting to the cell check assembling circuit 21, a control signal is sent to the cell check assembling circuit 21 to instruct the cells output from the buffer busy control circuit 19 to be output to the high speed cell transmission line 5 with priority.

The cell check assembling circuit 21 sends a control signal to the selector 24 according to the instruction of the buffer busy control circuit 19 and instructs the selector 24 to select the output of the buffer busy control circuit 19. In this way, the cell received from the high speed cell transmission line 5 is output as it is to the high speed cell transmission line 5 as the reception buffer busy and is sent back to the transmission source. The memory control circuit 12 includes a cell memory 13 or a priority cell memory 14
Each circuit is controlled so that the received cell is sent back to the transmission source as a reception buffer busy until there is a free space required for storing one or more cells in the memory. When the transmission source receives the cell (reception buffer busy), the transmission source retransmits the received cell (reception buffer busy) to the cell disassembly / assembly control device 1 after a certain period of time. This avoids memory overflow and prevents loss of cells. However, the cell memory 13 and the priority cell memory 14 are
It is equipped with a memory of sufficient capacity based on the results calculated by the traffic conditions in the system.

Next, a case where the cell disassembly / assembly control device 1 assembles the divided cells 27 to 33 transmitted by the time division multiplex transmission line 7 into the original cells 26 and outputs the assembled cells to the high speed cell transmission line 5 will be described. .

The low-speed cell reception circuit 20 of the cell disassembly / assembly control device 1 sequentially inputs the divided cells 27 to 33 shown in FIG. 3 (b) from the time division multiplex transmission line 7 connected to the input side, and outputs them to the output side. Output to the connected cell check assembly circuit 21. The cell check assembly circuit 21 is a divided cell from the low speed cell reception circuit 20.
Enter 27 to 33 to check the sequence number in the divided cell sequence number block of each divided cell. And
In the present embodiment, when the sequence number is 1H to 7H or 8H to EH, the divided cells are divided cells for assembling the original cells, so that they are sequentially stored temporarily in the memory (not shown). Then, when all the divided cells having a sequence number of 1H to 7H or all the divided cells having a sequence number of 8H to EH are received, the divided cells 27 to 33
The divided cell user information blocks 27C to 33C are extracted from them and connected in the order of the sequence numbers in the divided cell sequence numbers 27A to 33A to assemble the cell 26 having the configuration shown in FIG. 3 (a).

Further, in this embodiment, the sequence number is FH.
, The divided cell is a divided cell having the configuration shown in FIG. 4 (b), and the user information block 26 of the original cell is
Does not include B, which contains invalid or fixed data. Therefore, the cell check assembling circuit 21 extracts the header portion from the received divided cells, and based on the information contained in the header 26A, the user information block of the original cell 26.
Determine whether the information in 26B is invalid or fixed.
Then, the invalid data or fixed data stored in advance in the memory (not shown) is read out to generate the user information block 26B, and the user information block 26B is added to the extracted header 26A and added to the extracted header 26A.
Assemble the original cell 26 shown in (a). However, when the sequence number is 0H, the divided cell is a divided cell for transmitting special data for fault monitoring, and therefore the cell is not assembled. The cell check assembly circuit 21 outputs the assembled cell 26 to the cell buffer 22 connected to the output side when the sequence number is 1H to 7H, and the output side when the sequence number is 8H to EH. To the priority cell buffer 23 connected to.

As mentioned above, the divided cells of the priority cell may be transmitted by the time division multiplex transmission line 7 in such a manner as to interrupt the divided cells of the normal cells. In this case, the cell check assembling circuit 21 stores the divided cells of the normal cell temporarily stored in the memory (not shown) in the receiving order, and then stores the divided cells of the priority cell to be received next in the memory in the receiving order. Will be temporarily stored in. Then, when all the divided cells necessary for assembling the priority cell are received, the priority cell is assembled and output to the priority cell buffer 23. Then, the assembly of the normal cells is started after waiting for the remaining divided cells of the normal cells to arrive. In this way, priority cells having a higher priority are assembled preferentially and output to the high-speed cell transmission line 5, whereby the delay due to the transmission of the priority cells is reduced.

Further, the cell check assembly circuit 21 extracts and monitors control information, failure information, etc. from the divided cell control information blocks 27B to 35B for all the received divided cells. Further, when the sequence number 0H, 7H, EH or FH is detected, special data is extracted from the divided cell user information block of the received divided cell, and the failure of the time division multiplex transmission line 7 and the cell disassembly / assembly control device 2 is detected. To monitor.

Cell buffer 22 and priority cell buffer 23
Each have a memory capable of storing one or more cells 26, the cell buffer 22 temporarily stores normal cells from the cell check assembly circuit 21, and the priority cell buffer 23 has priority from the cell check assembly circuit 21. It temporarily stores cells and functions as a buffer together. Further, the cell buffer 22 and the priority cell buffer 23 constantly report the number of stored cells to the cell check assembly circuit 21. In the cell check assembly circuit 21, the cell buffer 22 or the priority cell buffer 23 is set to 1
When more than one cell 26 is stored, a control signal is sent to the selector 24 to instruct to select the output of the cell buffer 22 or the priority cell buffer 23. Then, the cell 26 is read from the cell buffer 22 or the priority cell buffer 23 at a timing suitable for the synchronization signal from the memory control circuit 12, that is, the transmission speed of the high-speed cell transmission path 5, and output to the selector 24. If the cell check assembly circuit 21 is instructed by the buffer busy control circuit 19 to preferentially output the output of the buffer busy control circuit 19 to the high speed cell transmission line 5, the cell buffer 22 or the priority cell buffer 23. Suspend the reading of cells from. And selector 24
To the buffer busy control circuit 19 to instruct to select a cell (reception buffer busy).

The selector 24 inputs the cell 26 output from the cell buffer 22, the priority cell buffer 23, or the buffer busy control circuit 19 according to the control signal from the cell check assembly circuit 21, and is connected to the output side at a high speed. Output to the cell sending circuit 25. The fast cell sending circuit 25 inputs the cell 26 from the selector 24, outputs it to the fast cell transmission line 5 connected to the output side, and sends it to the ATM switching main unit 3 shown in FIG.

As described in detail above, according to the present embodiment, when the cell transmitted by the high speed transmission line 5 or 6 is transmitted by the time division multiplex transmission line 7, the transmission side has a high priority. Cells are preferentially divided and output, and the receiving side preferentially assembles the original cells to preferentially transmit cells with a higher priority, so priority processing is performed compared to conventional cell transmission methods. It becomes possible to transmit information regarding required tasks and the like without delay.

When the cell transmitted by the high speed transmission line 5 or 6 is transmitted by the time division multiplex transmission line 7, if the user information of the cell is invalid or fixed data such as an empty cell, the transmission is performed. On the side, invalid or fixed data is deleted and transmitted, and on the receiving side, it is added to assemble the original cell, so it is possible to reduce the amount of information transmitted by the time division multiplexing transmission line 7, It is possible to realize the rapid transmission of the cells, the effective use of the time division multiplex transmission line 7, and the like.

If there is no cell transmitted by the high-speed transmission line 5 or 6, a divided cell containing special data for fault monitoring is generated and transmitted by the time division multiplex transmission line 7, so that a fault occurs. Early detection and effective use of the time division multiplex transmission line 7 can be achieved. Further, when the cells transmitted by the high-speed transmission line 5 or 6 are transmitted by the time division multiplex transmission line 7, the fault monitoring information or the like which is the control information is added to all the divided cells, and the cells are transmitted periodically. ,
When there is a room to add information to the divided cell, special data for fault monitoring is added to the divided cell and transmitted, so that the state of the partner device can be always grasped.

In this embodiment, the cells transmitted by the high-speed cell transmission line 5 or 6 and the time division multiplex transmission line 7
Although the case where the divided cell transmitted by the above has the configuration shown in FIGS. 3 to 5, the description is not limited to this. Further, the case where the low-speed transmission line is the time division multiplex transmission line 7 has been described, but the present invention is not limited to this, and the size of the cell that can be transmitted at one time is the high-speed cell transmission line 5.
Alternatively, a low-speed transmission line smaller than the cell transmitted by 6 may be used. In addition, the divided cell control information block 27B ~
Although the information for fault monitoring is transmitted by 35B etc., the information transmitted is not limited to the information for fault monitoring. Furthermore, although the present embodiment is a cell transmission method in ATM communication, it is naturally applied to a packet transmission method in packet communication for transmitting variable-length packets.

[0049]

As described above, according to the present invention, when a cell transmitted through a high-speed transmission line is transmitted through a low-speed transmission line, the transmission side preferentially divides and outputs a cell having a high priority. , Since the receiving side preferentially assembles the original cell into cells with a higher priority, the task requiring priority processing is transmitted without delay compared to the conventional cell transmission method. It becomes possible.

In addition, when the user information of the cell is invalid or fixed data such as an empty cell when the cell transmitted by the high speed transmission line is transmitted by the low speed transmission line, the invalid or fixed data is transmitted on the transmitting side. Is deleted and transmitted, and the original cell is assembled by adding it on the receiving side, so it is possible to reduce the amount of information transmitted by the low-speed transmission path, and to speed up the transmission of other cells and low-speed transmission. It is possible to realize effective use of the road.

If there is no cell transmitted through the high-speed transmission line, divided cells containing special data for fault monitoring are generated and transmitted through the low-speed transmission line, so that early detection of a fault and low-speed transmission are possible. The road can be effectively used. Further, when transmitting cells transmitted through the high-speed transmission line through the low-speed transmission line, control information, fault monitoring information, etc. are added to all the divided cells and transmitted periodically,
If there is room to add information to the divided cells,
Since the special data for fault monitoring is added to the divided cells and transmitted, the state of the partner device can always be grasped.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a cell disassembly / assembly control device to which a cell transmission method according to an embodiment of the present invention is applied.

FIG. 2 is a block diagram showing a configuration example of an ATM communication system.

FIG. 3 is a diagram showing a configuration example of a cell and a divided cell.

FIG. 4 is a diagram showing a configuration example of a divided cell when the cell includes invalid or fixed data.

FIG. 5 is a diagram showing a configuration example of a divided cell when there is no cell to be transmitted.

[Explanation of symbols]

 1-2 Cell disassembly and assembly control device 11 High speed cell reception circuit 12 Memory control circuit 13 Cell memory 14 Priority cell memory 15 Cell disassembly circuit 16 Priority cell disassembly circuit 17, 24 Selector 18 Low speed cell transmission circuit 19 Buffer busy control circuit 20 Low speed cell Reception circuit 21 Cell check assembly circuit 22 Cell buffer 23 Priority cell buffer 25 High-speed cell transmission circuit

Claims (5)

[Claims] 1. The transmitting side discriminates the priority of a cell received from a high-speed transmission line from the information in the header of the cell, and divides the cell into blocks of a predetermined size independently for each priority. Then, a divided cell is generated by adding information indicating the corresponding priority order to each of the blocks, and the divided cell with the highest priority among the generated divided cells according to the priority order is output to another divided cell. Even if it is in the middle, it preferentially outputs it to the low-speed transmission line in the form of interrupting it, and on the receiving side, the divided cells input from the low-speed transmission line are temporarily stored in memory sequentially, and all the cells necessary for assembling the original cell A cell transmission method, characterized in that the divided cells are assembled into an original cell in the order in which the divided cells are arranged and output to a next high-speed transmission line. 2. A transmission side generates a divided cell by dividing a cell received from a high-speed transmission line into blocks of a predetermined size and outputs the divided cell to a low-speed transmission line, and a reception side outputs from the low-speed transmission line. A cell transmission method for assembling an input divided cell into an original cell and outputting it to the next high-speed transmission line, in which the user information contained in the cell on the transmission side is predetermined information. Is detected from the information in the header of the cell, only the header is extracted from the cell, and information indicating that the information is deleted is added to the header to generate a divided cell and output to the low-speed transmission line. However, on the receiving side, when the information is detected from the divided cells input from the low-speed transmission line, the header is extracted from the divided cells and the prepared information is added to the header. A cell transmission method comprising assembling an original cell. 3. The transmitting side generates a divided cell by dividing a cell received from the high speed transmission line into blocks of a predetermined size and outputs the divided cell to the low speed transmission line, and the receiving side outputs from the low speed transmission line. A cell transmission method for assembling an input divided cell into an original cell and outputting it to the next high-speed transmission line, which is for fault monitoring when the transmission side does not receive a cell from the high-speed transmission line. A divided cell is generated by adding information indicating that fault monitoring data is contained in a block of a predetermined size for storing data, and the divided cell is output to the low-speed transmission line. A cell transmission method, wherein when the information is detected from an input divided cell, fault monitoring data is extracted from the divided cell. 4. The transmitting side generates a divided cell by dividing a cell received from the high speed transmission line into blocks of a predetermined size and outputs the divided cell to the low speed transmission line, and the receiving side outputs from the low speed transmission line. A cell transmission method for assembling an input divided cell into an original cell and outputting the cell to a next high-speed transmission line, wherein the transmitting side, when the last divided block is smaller than the predetermined size, By adding failure monitoring data to the last block, the block having the predetermined size is created, and then the divided cells are generated and output to the low-speed transmission line. A cell transmission method, wherein the fault monitoring data is extracted from the last divided cell. 5. The transmitting side generates a divided cell by dividing the cell received from the high speed transmission line into blocks of a predetermined size and outputs the divided cell to the low speed transmission line, and the receiving side outputs from the low speed transmission line. A cell transmission method for assembling an input divided cell into an original cell and outputting the cell to the next high-speed transmission line, wherein the transmitting side stores fault information or the like in all of the generated divided cells, The cell transmission method, wherein the receiving side extracts the failure information and the like from all of the divided cells input from the low-speed transmission path.