JPH09261053A - D/a conversion output circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize efficient offset cancel while simplifying a circuit by providing an offset adjusting circuit detecting an offset voltage in first and second amplifier circuits and obtaining the average of this voltage to add to the input digital signal of a D/A converter. SOLUTION: This circuit is provided with the D/A converter, the first amplifier circuit (+1) receiving an output signal from the D/A converter and forming a moninverted output signal of a common mode with it, and the second amplifier circuit (-1) receiving an output signal from the D/A converter and forming an inversion output signal of an opposite mode with it. With respect to this D/A conversion output circuit, the offset voltages with respect to an analog middle point voltages in the first and second amplifier circuit are respectively detected to add the digitized average to the input digital signal of the D/A converter. Consequently, offset is canceled on the side of a differential circuit depending on the reception of a noninverted or inversion output by simple constitution like this way.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D / A conversion output circuit, and is mainly used for an offset canceling technology which is mounted on a modem (modulation / demodulation circuit) for modulating and demodulating a transmission / reception signal mounted on a mobile communication terminal device. It is related to effective technology.

[0002]

2. Description of the Related Art In a modem of a mobile communication terminal device, a modulated signal is output as a normal signal and an inverted complementary signal which are in-phase with each other and are input to a differential circuit in a high frequency section to cancel a noise component. It is performed by doubling to improve the S / N (signal to noise ratio). However, in general, an amplifier circuit for forming the non-inverted signal and the inverted signal, which is composed of active elements, has some offset voltage due to manufacturing variations of the semiconductor integrated circuit. If such an offset voltage remains, noise and DC components that cannot be ignored are generated in the output signal of the differential circuit of the high frequency section. Therefore,
It is standardized that the offset voltage in the high frequency section is equal to or lower than a predetermined value. Regarding such an offset adjusting circuit and a mobile communication terminal device including the same, there is, for example, Japanese Patent Laid-Open No. 6-303137.

[0003]

The offset adjustment circuit disclosed in the above publication detects the offsets of the normal output and the inverted output with respect to the respective reference voltages (analog midpoint voltage), and outputs analog and digital correction values. . In this configuration, there is a problem that the number of circuit elements increases because two sets of correction output circuits corresponding to the normal rotation and inversion amplification circuits are required.

It is an object of the present invention to realize a D / A which realizes highly accurate offset cancellation while simplifying the circuit.
It is to provide a conversion output circuit. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0005]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, the D / A converter and the D
A first amplifier circuit that receives the output signal from the A / A converter and forms a normal output signal in phase with it, and forms an inverted output signal that is the opposite phase of the output signal from the D / A converter. To a D / A conversion output circuit including a second amplifier circuit for detecting the offset voltage with respect to the analog midpoint voltage in the first and second amplifier circuits, respectively, and calculating a digitized average value thereof. It is added to the input digital signal of the D / A converter.

[0006]

FIG. 1 is a block diagram showing an embodiment of a mobile communication terminal device equipped with a D / A conversion output circuit having an offset adjusting circuit according to the present invention. This mobile communication terminal device includes an audio codec unit 10
0, a TDMA control unit 200, a modem unit 300, and a high frequency unit 400. Control of the operation sequence of these units 100 to 400 and activation / activation of circuits is controlled by signals or pulses from the microcomputer unit 500, the regulator 600, the reset generation circuit 700, and the clock generation circuit 800.

Speech codec (encoding / decoding) 100
Is suppressed into a digital signal by the A / D converter 101 by suppressing a high frequency noise component in the transmission analog voice signal input from the microphone with a pre-filter (not shown). The compression circuit 102 band-compresses the digital signal by digital signal processing. Contrary to the above, the band-compressed received digital voice signal is expanded by the expansion circuit 103.
To the original band. A digital signal processor may be used to perform the digital signal processing of these digital compression operation and decompression operation. The expanded digital signal is supplied to the D / A converter 1
A sound analog signal is converted by 04, a harmonic component contained in the output is suppressed by a post filter (not shown), and the output is amplified to drive a speaker or the like.

Channel codec (TDMA control) 2
00 performs time-division processing, code generation for error correction, error checking, assembling and analyzing transmission / reception signal frames, etc., and transmits signal SD (384 kbps) and reception signal RD.
(384 Kbps) is formed.

The modem (modulation / demodulation) 300 uses the TDMA.
Modulation suitable for wireless transmission of the transmission signal SD output from the control 200, for example, π / 4 shift cue peak
Waveform generator 301 for performing S.K. (QPSK) modulation, D / A converter 302 for converting the output into an analog signal, post filter 303 for suppressing the harmonic component contained in the output, and the normal rotation. The signal and the inverted signal are formed by the output buffer 304. Output buffer 3
04 is an I (normal signal) IB composed of 96 KHz, for example.
(Inverted signal) and Q (normal signal) and QB (inverted signal) are formed.

Contrary to the above, the received modulated signal is transmitted to the amplifier 30.
5, the phase detection circuit 306 and the delay detection circuit 3 are amplified.
The phase information is temporarily converted into a voltage by 07 and converted into a digital signal by the A / D converter included in the differential detection circuit 307 to form the reception signal RD. The offset adjustment circuit according to the present invention includes an offset detection circuit 309 and a correction circuit 310. As will be described later, this offset adjustment circuit performs an operation of canceling a relative offset between the normal rotation signal and the inverted signal included in the output buffer.

The above-mentioned phase modulation is usually realized by a read-only memory ROM, and the waveform generating circuit 301 and the D / A converter 30 as the phase modulator are usually used.
2, and two sets of post filters 303 are provided in parallel in order to output signals having a phase difference of 90 °, that is, orthogonal signals, according to the I signal and the Q signal.

The high frequency section 400 includes the output buffer 30.
4 Output forward and reverse signals are received by differential signals,
In-phase noise components are removed and the 1 signal and Q
Quadrature-modulates the signal, and further from 800MHz to 2
It is modulated with a radio frequency carrier signal such as 1.9 GHz in the GHz range, amplified to a predetermined transmit power and the antenna is excited via a transmit / receive switch. Further, the signal received via the antenna 232 and the switch is amplified by an amplifier, and an intermediate signal I such as 10.8 MHz is generated.
The frequency is converted to F, and the amplifier 30 of the modem 300 is
Tell the input of 5.

The power switch SW is provided on the housing of the mobile communication terminal device. Before the call, the caller turns on the power switch SW, so that the battery BAT mounted inside the terminal device or the power supply voltage supplied from the outside of the terminal device is supplied to the voltage regulator 60.
The operating voltage is supplied to each unit in the terminal device via 0 or partially directly. Here, the voltage regulator 6
00 is for supplying a substantially constant voltage value to each unit in the terminal device with respect to a change in voltage value due to discharge or charge accompanying the consumption of the battery BAT.

The reset signal generating circuit 700 generates a reset signal or the like for resetting the data stored in the register of each part in the terminal device when the power switch SW is in the ON state. Clock generation circuit 80
0 generates a stable clock which is supplied to each unit in the terminal device and the control microcomputer 500. It is usually composed of a temperature-stabilized crystal oscillator and means for dividing or multiplying its output. From the control microcomputer (MCU) 500, the reset signal generation circuit 700, the clock generation circuit 800, and the battery BAT, in addition to the power switch SW and the voltage regulator 600, although not shown in the figure, a keypad, a dial signal generation And a ringing signal generator.

The voice codec section 100, the channel codec section 200, the modem 300, the high frequency section 400, and other electronic circuits which compose the portable communication terminal device are configured so that they can be operated at low power supply voltage and low power consumption. It For example, in the voice codec 100, the silent state of the voice is detected to stop the operation of the main circuit section, and in the modem 300 and the high frequency section 400, in addition to the operation stop of the main circuit section when there is no sound, a wireless call is also performed. It is configured to suppress power consumption by intermittently operating the main part of the circuit by utilizing the system configuration specification that is time division multiplexing. The microcomputer 500 performs such control by detecting the state of each unit.

In accordance therewith, the offset adjusting circuit according to the present invention is also operated by a predetermined control signal only when the power is turned on and when the standby is released, as will be described later, and when the offset detection is completed, only during the call time. , The operation of only the minimum necessary registers 25 and 26 and the adder to maintain the supply for offset adjustment is maintained, and the other circuit parts are made inactive and disabled.

As a result, it is possible to realize the modem 300, which is most suitable for battery drive, and the mobile communication terminal device equipped with the modem 300. That is, when the mobile communication terminal is powered on and power-on reset, and after the power is supplied, all or part of the circuit included in the modem 300 of the mobile communication terminal is set to a non-communication state and a call is made. Microcomputer 50 when ready to call
0 activates each component circuit portion of the offset adjustment circuit and starts the offset adjustment operation by the offset adjustment circuit.

After the offset adjustment operation is started, the microcomputer 500 performs a series of control operations for offset adjustment, which will be described later, and after the offset adjustment is completed, it is necessary among the constituent circuits of the offset adjustment circuit. Only the registers 25 and 26 and the adder are maintained in an operable state, and the offset adjusting signal is continuously generated. This deactivates unnecessary circuits and substantially suppresses unnecessary power consumption. Then, at least when the modem 300 shifts to the standby state, the signal for offset adjustment is no longer required anymore, so it is said that the microcomputer 500 deactivates all the circuits constituting the offset adjustment circuit. There is no end.

The input circuit 308 of the modem 300 is an interface with the microcomputer 500 and is not particularly limited.
Supplies the address signal and write / read data to various registers and storage circuits included in the modem. A decoder included in the input circuit 308 forms a selection signal for one register or a memory circuit,
Write data is input in the above write operation, and data is output while being held in a register or a memory circuit in the read operation. The control operation for the modem 300 from the microcomputer 500 includes the offset adjustment operation as described above and the signal gain setting in the amplifier 305 and the waveform generation unit 301.

FIG. 2 is a block diagram showing an embodiment of the offset adjusting circuit according to the present invention. Each circuit block in the figure is formed on one semiconductor substrate together with each circuit block constituting the modem by a known semiconductor integrated circuit manufacturing technique.

The D / A converter, the filter and the differential output circuit shown in the figure correspond to the D / A converter 302, the post filter 303 and the output buffer 304 shown in FIG. The differential output circuit includes a normal amplification circuit (+1) that forms a normal output that is in phase with the output signal of the filter, and an inversion that forms an inverted output that is the opposite phase (180 ° phase difference) of the output signal of the filter. It is composed of an amplifier circuit (-1). Although not particularly limited, these amplifier circuits +1 and -1 are composed of a differential amplifier circuit and have a gain of 1 to form the in-phase signal and the inverted signal as described above, respectively. In this case, due to unbalanced characteristics of the pair elements of the differential circuit, the output voltage forms a positive or negative output signal with respect to the above-mentioned midpoint voltage even when the input signal is zero (AC-like midpoint voltage). It has an offset of being lost.

When such an offset voltage exists, the normal output and the inverted output are the high frequency section 400 of FIG.
The noise component contained in the differential amplifier circuit is canceled and doubled to improve the S / N. However, if the offset voltage is as described above, Noise and DC component that cannot be ignored are generated in the output signal of the differential circuit of the above section. Therefore, it is necessary to cancel the offsets in the amplifier circuits (+1) and (-1).

In this embodiment, in order to simplify the offset adjusting circuit for canceling the offset voltage as described above, the circuit is made common. That is, the non-inverted output of the amplifier circuit (+1) and the inverted output of the amplifier circuit (-1) are selectively supplied to one input of the voltage comparator through the analog switches. The reference voltage formed by the reference voltage generation circuit is supplied to the other input of the voltage comparator. This reference voltage corresponds to the center value of the D / A converted output signal, in other words, the midpoint voltage of the analog signal.

The large or small comparison output of the voltage comparator is an up-down signal 1, which is not particularly limited, but is inputted to the majority circuit. As will be described later, the majority decision circuit takes in a plurality of the up / down signals 1 of the voltage comparator in time series in synchronization with a clock by a clock signal, and makes a majority decision of the plurality of magnitude comparison outputs by a majority decision logic circuit. And up-down signal 2 corresponding to the large or small comparison output signal. Up / down signal 2 corresponding to such a large or small comparison output
Is used for counting operation of +1 or -1 in the counter.

The counter is output through a selector 2 which selects a true (non-inverted) output or a bar (inverted) output, and one of them is input to an adder 1 through a selector 3. DC is added to the adder 1 through the selector 4.
Code output is provided. This DC code output is a digital signal corresponding to the center (middle point) voltage of the analog signal.

Since the counter is reset before the offset cancel operation is started, the adder 1 outputs a digital signal corresponding to the DC code output at the start of the offset cancel operation, and outputs the digital signal to the D / A converter. To enter. The D / A converter converts the DC code output into an analog signal, and a voltage corresponding to the midpoint voltage is formed through the filter. Therefore, the first amplifier circuit (+1) of the differential output circuit forms a normal output corresponding to the midpoint voltage. The output signal of the amplifier circuit (+1) is a superposition of the input midpoint voltage and the offset voltage of itself.

The analog switch selects, for example, the output signal of the amplifier circuit (+1) and compares it with the reference voltage.
If the output signal of the amplifier circuit is larger than the reference voltage, a low level output signal (down signal) is formed. If the majority circuit determines that the signal is down,
The counter performs a count operation of -1. The count output of -1 is input to the adder 1 through the selectors 2 and 3. Therefore, with respect to the result of the first comparison operation, D
A digital signal is formed by adding -1 to the C code output, and the D / A converter performs the D / A conversion operation again. At the second time, since the input digital signal is reduced by -1 as described above, the input voltage supplied to the input of the differential output circuit is lowered.

With respect to the input signal thus lowered,
A voltage comparison operation similar to the above is performed. Even if the input signal is lowered, if the output signal of the amplifier circuit (+1) is still larger than the reference voltage, the low level output signal (down signal) is formed again. In the same way as above, with a majority circuit,
If it is determined that the signal is a down signal, the counter again counts by -1, and the total count value becomes -2 (expressed in decimal notation for easy understanding of the invention). The digital signal input to the / A converter is reduced. After that, the same operation is repeated in the voltage comparator until the input voltage becomes smaller than the reference voltage. As a result, a digital signal corresponding to the offset voltage of the amplifier circuit (+1) is formed in the counter.

If the output signal of the amplifier circuit is smaller than the reference voltage at the first time, a high level output signal (up signal) is formed. By the majority decision circuit,
If it is determined that the signal is an up signal, the counter performs a counting operation of +1. This +1 count output is input to the adder 1 through the selectors 2 and 3. Therefore, a digital signal in which +1 is added to the DC code output is formed with respect to the result of the first comparison operation, and the D / A conversion operation is performed again by the D / A converter. In the second time, since the input digital signal is increased by +1 as described above, the input voltage supplied to the input of the differential output circuit is increased. Then, the same operation as described above is repeated until the input voltage becomes higher than the reference voltage in the voltage comparator. As a result, a digital signal corresponding to the offset voltage of the amplifier circuit (+1) is formed in the counter.

When the analog switch is switched and the inverted output of the amplifier circuit (-1) is selected, the amplifier circuit (-) is selected.
The offset voltage of 1) can be detected in the same manner as above. However, since the amplifier circuit (-) forms an inverted output, the polarities of the voltages appearing in the output signal are reversed even if the offset voltage is the same, and the same voltage comparator and majority circuit are used to increase or decrease the voltage. When counting, the polarities are reversed. Therefore, when the offset of the amplifier circuit (-1) is detected by the selector 2, the bar output of the counter is selected. This makes it possible to perform the same operation as described above.

The digitized offset voltage detected by the counter is held in the first register (normal rotation) and the second register (inversion) through the selector 1, respectively. That is, a digital signal corresponding to the offset voltage of the amplifier circuit (+1) is formed and held in the first register through the selector 1, and then the counter is cleared. Then, the amplifier circuit (-
A digital signal corresponding to the offset voltage of 1) is formed, held in the second register through the selector 1, and the counter is cleared.

In this embodiment, the offset voltages held in the first register (normal rotation) and the second register (inversion) are the first amplification circuit (+1) and the second amplification circuit corresponding to the offset voltage, respectively. It is not used to cancel the offset of circuit (-1). The two offset voltages held in the two registers are added by the adder 2.
It is halved by the ½ circuit to obtain the average value. This 1/2 circuit may be realized by a simple wiring path in which the added digital output is shifted by 1 bit, in other words, lowered by one digit and transmitted to the clip circuit, or a 1-bit shift is performed by a shift register. It may be transmitted to the clip circuit. This clip circuit
It is used when it is necessary to limit the maximum value of the calculated result. That is, if the above calculation result is equal to or less than the above maximum value, the calculation result is transmitted to the selector 3 as it is.

The average adjusted voltage with respect to the reference voltage of the two amplifier circuits (+1) and (-1) that has passed through such a clipping circuit is input to the adder 1 through the selector 3. At this time, the selector 4 selects the original data output. That is, the average offset voltage is added to the digital data to be digital / analog converted. Therefore, according to the characteristic offset cancellation method in this embodiment, the difference between the average offset voltage and the offset voltage of each amplifier circuit (+1) and (−1) With the corresponding offset voltage remaining, the averaged offset voltage as the correction voltage is added to the common adders 1 and D.
The circuit is simplified by transmitting it to the differential output circuit through the A / A converter and the filter.

That is, it is the high-frequency section, which is the next-stage circuit, that is inconvenient because the normal output and the inverted output have an offset. In this embodiment, as described above, since the offset voltage is made equal to each of the normal output and the inverted output in the modem section by superimposing the average offset voltage as described above, the high frequency The differential circuit of the high frequency section cancels out like the noise component, and noise and DC component that cannot be ignored are not generated in the output signal of the differential circuit of the high frequency section.

The analog switch has a function of selecting a reference voltage. That is, during normal operation as described above, the analog switch selects the reference voltage and supplies the same reference voltage to the two inputs of the voltage comparator. As a result, the current flowing through the differential circuit forming the voltage comparator becomes uniform, and the characteristic deterioration of the circuit in the voltage comparator due to change over time is prevented.

The selector 5 is provided for inputting external offset data. Although not particularly limited, if there is an offset in the differential circuit of the high frequency section, the offset that the high frequency section itself has remains even if the offset adjustment is performed in the modem section as described above, which is inconvenient. Therefore,
The external input function is provided so that the offset adjustment circuit of the modem section can be used for the offset adjustment of the high frequency section. That is, the modem unit can perform signal processing by forming and inputting a digital signal so as to cause the offset in the high frequency unit to be cancelled, and the entire system can be simplified.

FIG. 3 is a block diagram of another embodiment of the offset adjusting circuit according to the present invention. The modem 300 includes a waveform generator (not shown) as the phase modulator, a D / A converter, a differential output circuit as a filter and an output buffer, which have a phase difference of 90 ° from each other according to the I signal and the Q signal. That is, two sets of circuits are provided in parallel to perform orthogonal signal output. The offset adjusting circuit is commonly used for such two sets of differential output circuits. In the figure, the selector 5 for inputting the external offset data is omitted.

Therefore, the analog switch has a total of 4
The amplifier circuits and the reference voltage are selected. The select 1 is provided with four selection functions corresponding to the total of four forward rotation registers and four inversion registers corresponding to the above two sets of differential output circuits. Corresponding to the two sets of D / A converters, the adder 1, the selector 2 and the selector 4 provided at the input section of the adder 1, and the clip circuit are also provided in two sets. On the other hand, the voltage comparator, the majority circuit, the counter and the adder 2 are commonly used in a time-division manner in the offset canceling operation of the total of four amplifying circuits.

FIG. 4 is a schematic block diagram showing an embodiment of the majority decision circuit included in the offset adjustment circuit. In the voltage comparator as described above, when the difference voltage between the reference voltage and the input voltage is extremely small, even a small noise is affected and the determination accuracy deteriorates. Then, Δ
The up / down signal 1 from the voltage comparator is fetched into the flip-flops FF1 to FF3 in synchronization with the majority clocks 1 to 3 each having a delay time of t. That is, the up / down signal 1 is sequentially taken into the flip-flops FF1 to FF3 each time the delay time Δt elapses. The output signals of these flip-flops FF1 to FF3 are input to the three inputs AI, BI and CI of the majority logic circuit LOG, and the output CO forms the up-down signal 2 in accordance with the majority vote.

With the above configuration, even if an incorrect up / down signal 1 is formed due to noise, the other 2
An up / down signal 2 can be formed corresponding to one correct up / down signal 1. Alternatively, even when the reference voltage and the input voltage are equal and the determination result is different every second, the determination result in a more correct direction can be obtained.

FIG. 5 shows a circuit diagram of an embodiment of the control circuit included in the counter circuit. A count signal is generated in synchronization with the first comparison operation for offset adjustment. As a result, the flip-flop stores the first determination result. As described above, when the first time is the low level, the flip-flop holds the low level. After that, the up-down signal 2 is generated from the majority circuit for each comparison operation, and the up-down signal 2 is counted by the counter circuit. When the output signal of the majority decision circuit changes from the low level to the high level, the low level from the flip-flop and the high level from the majority decision circuit are input to the input of the exclusive OR circuit EXOR, and the count stop signal of the high level is input. Is formed. This stop signal is input to the counter circuit as a stop signal via the OR circuit together with the carry signal of the counter circuit.

The counting operation of the counter circuit is stopped when the determination output initially output from the voltage comparator is inverted corresponding to the counting output of the counter circuit as described above. That is, by using the flip-flop circuit and the exclusive OR circuit as described above, the low level is first output and the high level is output as described above, and the high level is output first. Both can be detected when changing to a low level. When the offset voltage is above the cancellation range, the counter circuit overflows. A stop signal is generated by the carry signal of the counter circuit, and the count value of the counter circuit outputs the maximum or minimum value.

FIG. 6 shows a potential distribution diagram for explaining the offset canceling operation according to the present invention. For example, if the offset voltage of the first amplifier circuit (+1) is X and the offset voltage of the second amplifier circuit (-1) is Y, the offset voltage Y is calculated from the counter circuit as described above. , The average value such as (X + Y) / 2 = Z is formed.
This average value Z is added to the offset voltage X, and the offset voltage from the first amplifier circuit (+1) and Z
Is substantially subtracted from the offset voltage Y to equalize it with the offset voltage from the second amplifier circuit (-1).

That is, the first amplifier circuit (+1) and the second amplifier circuit (-1) have the above-mentioned combined offset voltage in relation to the input and output, respectively. In terms of the relative relationship between the normal output and the inverted output, the two are made equal. Therefore, the differential circuit in the high frequency section in the next stage cancels it out together with the noise. Therefore, the offset in the amplifier circuit forming the normal output and the inverted output in the modem section causes the differential circuit in the high frequency section. There is no noise or DC component that cannot be ignored in the output signal.

FIG. 7 is a flow chart for explaining the adjusting operation of the offset adjusting circuit according to the present invention. This offset adjustment operation is performed during the training period before the start of operation of the modem.

When the activation is started in step (1), the selectors 3 to 5 are set in step (2). That is, the select sector 3 is connected to the selector 2 side in correspondence with the offset detection operation, the selector 4 is set to the tescode output side, and the selector 5 is turned off.

In step (3), the forward rotation side or the reverse rotation side is selected. That is, the selector 2 of the analog switch
Is set to the forward or reverse side. In step (4), the voltage comparison is judged. That is, the up / down signal 2 is formed by the operation of the voltage comparator and the operation of the logarithm determination circuit as described above. In step (5), in response to the up / down signal 2, the counting operation of +1 or -1 is performed in the counter circuit. In step (5),
The count value of the counter is set in the corresponding register.

In step (6), the digital signal obtained by adding the count value of the counter and the DC code output by the adder 1 is DA converted, and the second and subsequent determinations are performed in step (8). In step (9), when the stop signal is not generated (No), the process returns to step (5). After that, until the stop signal is generated (Yes), the above step (5)
Repeated operations are performed by the loop of (9) to (9).

When the stop signal is generated in step (9), the counter is reset in step (10), and it is determined in step (11) whether the positive side and the inversion are completed. If the inversion side is not completed, for example, the process returns to step (3), and the inversion side is selected by the analog switch and the selector 2.
After that, the same operation as described above is performed.

If it is determined in the above step (11) that the normal / reverse has been completed (Yes), step (1)
In 2), the addition of the register (normal rotation) and the register (reversal) and the 1/2 arithmetic processing are performed. In step (13), the average value formed by the arithmetic processing is held in the clip circuit. In step (14), the selectors 3 to 5 are switched so that the adder 1 is set to input the data output and the offset cancel data.

When there are two sets of differential output circuits for performing the offset adjustment as in the embodiment of FIG. 3, after the step (14), both the I signal side and the Q signal side are described above. It is only necessary to determine whether a series of offset canceling operations have ended, and after the differential output circuit on the I signal side has ended, perform the offset canceling operation on the differential output circuit on the Q signal side.

FIG. 8 is a timing chart for explaining the offset detecting operation of the offset adjusting circuit according to the present invention. The following operations are sequentially performed in synchronization with the count signal as the clock signal. Since the counter output is 0 at the beginning, the adder 1 forms 256 output signals corresponding to the midpoint voltage. The D / A converter converts it into an analog voltage, and the first amplifier circuit (+1)
Outputs a non-inverted output, and when it is lower than the reference voltage, the up / down signal 2 becomes high level. Since then
In synchronization with the count signal, the counter output counts +1 and is transferred to the register (normal rotation), the output of the adder 1 is increased to 257, and the normal rotation output is increased accordingly. Corresponding to the counting operation of such a counter circuit, the non-inverted output sequentially increases, and when the reference voltage is exceeded, the up / down signal 2 changes from the high level to the low level. In response to this, a stop signal is generated to stop the operation of the counter circuit, the counter circuit is cleared and returns to 0.

The analog switch or the selector 2 is switched to perform the offset detection operation on the inversion side. Similarly to the above, since the counter output is 0 at the beginning, the adder 1 forms 256 output signals corresponding to the midpoint voltage. D /
The A converter converts it into an analog voltage, the inverted output is output from the second amplifier circuit (-1), and when it is smaller than the reference voltage, the up / down signal 2 becomes high level. After that, the counter output will be + in synchronization with the count signal.
Count one. However, since the counter output is output to the bar side by the selector 2, the counting operation of substantially -1 is performed and the count value is reduced to -1. -1 is transferred to the register. The output of the adder 1 is reduced to 255, and the inverted output is increased accordingly. Corresponding to the counting operation of the counter circuit, the inverting output sequentially increases, and when the reference voltage is exceeded, the up / down signal 2 changes from the high level to the low level. In response to this, a stop signal is generated to stop the operation of the counter circuit, the counter circuit is cleared and returns to 0.

The data transfer to the register is carried out uniformly for each count operation as described above, and it is substantially meaningless to hold the count value in the middle in the register as described above. Therefore, the selector 1 may be controlled so that it is performed only once when the above stop signal is generated.

The control of the counter circuit as described above can adopt various embodiments. As one method, the count data is sequentially incremented from zero as described above in accordance with the up / down signal 2 to be up (+1) or down (-).
The counting operation of 1) is performed.

In this control method, the voltage comparator produces the high-level or low-level up / down signal 1 even when the offset voltage is as close to 0 as described above. As a result, in the subsequent operation as described above, the output of the voltage comparator is no longer inverted, and the offset voltage detection operation is performed until the counter circuit clears. Therefore, the counter circuit operates up to the maximum value of the counter circuit, and there is a possibility that it is erroneously determined that the maximum offset voltage exists.

In the second method, the counter circuit is initialized to the minimum value or the maximum value, and the up / down signal 2 is changed from one level to the other level whenever the offset voltage is within the offset cancel range. It is something to do.

In the third method, the counter circuit is set to zero, and the up / down signal at that time sets the count data to the maximum value or the minimum value, and then the offset detection operation is started. As a result, the operation of the counter can be stopped by detecting the offset voltage between the maximum value or the minimum value and the zero.
That is, according to the second method, in the worst case, it is necessary to operate the counter circuit from the minimum value to the maximum value.
It takes a relatively long time to detect the offset.

FIG. 9 shows a schematic block diagram of an embodiment of the high frequency section. Of the two sets of differential output signals formed by the modem section including the offset adjusting circuit as described above, the normal set signal (I) and the inverted output (I) as the first set.
B) is input to the differential circuit AMP1 and the above noise and offset are canceled to form a doubled I signal.

The normal signal (Q) and the inverted output (QB) as the second set are input to the differential circuit AMP2, and the noise and offset as described above are canceled to form a doubled Q signal. To be done. The Q signal is phase-shifted by 90 ° by the phase circuit, added by the adder circuit, superimposed on the carrier wave formed by the synthesizer, and output as a transmission radio wave.

In such a high frequency section, the differential circuits AMP1 and AMP2 are used as described above, and when an offset is included in them, a DC component corresponding to the offset voltage remains in the output signals I and Q. Therefore, the offset voltage of the differential circuits AMP1 and AMP2 in the high frequency section is detected, and the offset voltage is digitized to obtain the signal shown in FIG.
If it is input as the external offset data of the modem section shown in, the offset voltage in the high frequency section can be canceled by using the offset adjusting circuit provided in the modem section. In FIG. 1, a path indicated by a dotted line from the high frequency section 400 to the input circuit 308 of the modem section 300 represents such external offset data.

The functions and effects obtained from the above-mentioned embodiment are as follows. (1) A D / A converter, a first amplifier circuit that receives an output signal from the D / A converter and forms a normal output signal in phase with the D / A converter, and an output signal from the D / A converter The offset voltage for the analog midpoint voltage in the first and second amplifier circuits is supplied to the D / A conversion output circuit that includes the second amplifier circuit that receives the inverted output signal and forms an inverted output signal. Each is detected, and the digitized average value is added to the input digital signal of the D / A converter to cancel the offset on the differential circuit side of the next stage which receives the normal output and the inverted output. The effect of being able to do is obtained.

(2) In the above (1), the offset is not canceled for each of the first and second amplifying circuits, but the offset adjusting circuit is commonly used for the two amplifying circuits. Therefore, there is an effect that the circuit can be simplified.

(3) A selector is provided at the input of the adder so that only the digital signal corresponding to the midpoint voltage is supplied in the first period and the output signal of the counter is added as a signal in the second period. Is supplied, and the output signal of the clipping circuit and the input digital signal are supplied during the D / A conversion operation, so that the operation efficiency of the circuit can be improved because the operation can be shared for both the offset detection operation and the offset adjustment operation. The effect that the substantial circuit can be simplified is obtained.

(4) At the output of the voltage comparator, a flip-flop circuit that sequentially takes in the magnitude comparison output signals in time series in synchronization with a clock pulse, and a majority circuit that receives the output signal of the flip-flop circuit are provided. By providing the output signal of the majority decision circuit as the large or small comparison output, it is possible to obtain a highly accurate voltage comparison output.

(5) It is said that the offset voltage of the differential circuit in the high frequency section at the next stage can be canceled by allowing the external offset data to be selectively input to the adder. The effect is obtained.

(6) The D / A converter and the first and second
2 sets of amplifier circuits corresponding to I signal and Q signal are provided, and the offset adjustment circuit is commonly used for the two sets of D / A converters and the first and second amplifier circuits. As a result, the effect that the circuit can be simplified can be obtained.

(7) The analog switch supplies a reference voltage when the offset adjusting circuit is in the non-operating state so that both input voltages of the voltage comparator are equalized, so that the voltage comparator changes with time. It is possible to obtain the effect that good characteristics of can be maintained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the counter circuit may invert the up / down signal 2 from the majority circuit to detect the offset on the inversion side and input the inverted signal to the counter circuit. In this case, selector 2
Can be omitted. INDUSTRIAL APPLICABILITY The present invention can be widely used as an offset adjustment circuit of a D / A conversion output circuit including an output buffer that forms a normal output and an inverted output of a D / A converted analog signal.

[0070]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, the D / A converter and the D
A first amplifier circuit that receives the output signal from the A / A converter and forms a normal output signal in phase with it, and forms an inverted output signal that is the opposite phase of the output signal from the D / A converter. To a D / A conversion output circuit including a second amplifier circuit for detecting the offset voltage with respect to the analog midpoint voltage in the first and second amplifier circuits, respectively, and calculating a digitized average value thereof. With the simple configuration of adding to the input digital signal of the D / A converter, the offset can be canceled on the differential circuit side of the next stage which receives the normal output and the inverted output.

[Brief description of drawings]

FIG. 1 is a diagram of a D including an offset adjusting circuit according to the present invention.
It is a block diagram which shows one Example of the portable communication terminal device which mounts the / A conversion output circuit.

FIG. 2 is a block diagram showing an embodiment of an offset adjusting circuit according to the present invention.

FIG. 3 is a block diagram showing another embodiment of the offset adjusting circuit according to the present invention.

FIG. 4 is a schematic block diagram showing an embodiment of a majority decision circuit included in an offset adjustment circuit according to the present invention.

5 is a circuit diagram showing an embodiment of a control circuit included in the counter circuit shown in FIGS. 2 and 3. FIG.

FIG. 6 is a potential distribution diagram for explaining an offset cancel operation according to the present invention.

FIG. 7 is a flow chart for explaining the adjusting operation of the offset adjusting circuit according to the present invention.

FIG. 8 is a timing chart for explaining an offset detection operation of the offset adjustment circuit according to the present invention.

FIG. 9 is a schematic block diagram showing an embodiment of the high frequency unit shown in FIG.

[Explanation of symbols]

100 ... Voice codec section, 101 ... A / D converter,
102 ... compression circuit, 103 ... decompression circuit, 104 ... D / A
Converter, 200 ... Channel codec section, 300 ...
Modem section, 301 ... Waveform generation, 302 ... D / A converter,
303 ... Post filter, 304 ... Output buffer, 30
5 ... Amplifier, 306 ... Phase detection circuit, 307 ... Delay detection circuit, 308 ... Input circuit, 309 ... Offset detection circuit, 310 ... Offset correction circuit, 400 ... High frequency section,
500 ... Microcomputer, 600 ... Regulator, 700 ... Reset generation circuit, 800 ... Clock generation circuit, FF1 to FF3 ... Flip-flop, LOG ... Majority decision logic circuit, EXOR ... Exclusive OR circuit, OR ... OR circuit, AMP1, AMP2 ... differential circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Yuko Tanba 2326 Imai, Ome City, Tokyo Metropolitan area, Device Development Center, Hitachi, Ltd. (72) Inventor Masayuki Yamashita 5-20-1, Mizumizuhonmachi, Kodaira-shi, Tokyo Hitate Super LSI Engineering Co., Ltd.

Claims (7)

[Claims] 1. A D / A converter, a first amplifier circuit for receiving an output signal from the D / A converter and forming a normal output signal in phase with the D / A converter, and a D / A converter from the D / A converter. A D / A conversion output circuit comprising a second amplifier circuit which receives an output signal and forms an inverted output signal having a phase opposite to that of the output signal, wherein the analog / midpoint voltage in the first and second amplifier circuits is digitized. The offset voltage is detected and the average value of the two offset voltages is calculated to obtain the above D / A.
A D / A conversion output circuit comprising an offset adjusting circuit which is added to an input digital signal of the converter. 2. A D / A converter, a low-pass filter that removes harmonic components contained in the output signal of the D / A converter, and a normal output signal in phase with the output signal of the filter. A first amplifier circuit for forming
In a D / A conversion output circuit including a second amplifier circuit which receives an output signal from the A converter and forms an inverted output signal having an opposite phase thereto, an input digital signal supplied to the D / A converter is provided. A first adder to be formed, an analog switch for selecting the output signals of the first and second amplifier circuits, an output voltage through the analog switch, and a reference voltage corresponding to the midpoint voltage of the input signal Of a voltage comparator, a counter for performing an up or down counting operation corresponding to a large or small comparison output of the voltage comparator, and a first and a second for holding the count output of the counter. Register and above first
An offset adjusting circuit including a second adder for adding the output signals of the second register and a clip circuit for holding a signal that is ½ of the output signal of the second adder, In the first period prior to the operation of the A conversion output circuit, the digital signal corresponding to the midpoint voltage is input to the first input of the first adder, and the output signal corresponding to the digital signal is output, First by the analog switch
The output signal of the amplifier circuit is compared with the reference voltage by the voltage comparator, and the counter is operated to count up or down according to the large or small comparison output, and the output signal of the counter is output in the second period. To the second input of the first adder to output the addition signal of the first and second inputs, and to output the output signal of the first amplifier circuit and the reference voltage through the analog switch. The operation of counting up or down the counter according to the large or small comparison output by comparison with the voltage comparator is repeated, and when the large or small comparison output of the voltage comparator is inverted in the third period. The above operation is stopped, the count value of the counter at that time is transferred to the first register, and the first input of the first adder receives the digit corresponding to the midpoint voltage during the fourth period. Input signal to output an output signal corresponding to the input signal, and the analog switch outputs the output signal of the second amplifier circuit to the reference voltage to compare them with a voltage comparator to obtain a large or small comparison output. Correspondingly, the counter is operated to count up or down, and in the fifth period, the output signal of the counter is supplied to the second input of the first adder to add the signals of the first and second inputs. Is output and the output signal of the first amplifier circuit is compared with the reference voltage through the analog switch by a voltage comparator, and the counter is operated to count up or down corresponding to the large or small comparison output. Is repeated, the operation is stopped when the magnitude comparison output of the voltage comparator is inverted in the sixth period, and the count value of the counter at that time is transferred to the second register. Then, in the seventh period, the output signals of the first and second registers are added by the second adder d, and 1 /
A D / A conversion output circuit, characterized in that the second signal is held by a clipping circuit and is added to the input digital signal by the first adder. 3. A signal is provided with a selector at the input of the first adder so that only a digital signal corresponding to the midpoint voltage is supplied in the first period and is added in the second period. The output signal of the counter is supplied as
3. The D / A conversion output circuit according to claim 2, wherein the output signal of the clipping circuit and the input digital signal are supplied during the / A conversion operation. 4. The output of the voltage comparator is provided with a flip-flop circuit that sequentially takes in the magnitude comparison output signals in time series in synchronization with a clock pulse, and a majority circuit that receives the output signal of the flip-flop circuit. 4. The D / A conversion output circuit according to claim 2 or 3, wherein the output signal of the majority decision circuit is the large or small comparison output. 5. The D / according to claim 2 or 3, wherein the first adder is provided with a selector capable of selectively inputting external offset data. A conversion output circuit. 6. The D / A converter and the first and second amplifier circuits are provided in two sets, and the two sets of D / A converters are provided.
The analog switch, the voltage comparator, the counter, and the second adder are commonly used for the A converter and the first and second amplifier circuits, and the first adder, the first and second registers are used. 3. The D / A conversion output circuit according to claim 2, wherein two sets of clipping circuits are provided. 7. The analog switch is provided with a connection switch path for supplying a reference voltage when the offset adjusting circuit is in a non-operating state to equalize both input voltages of the voltage comparator. D / of claim 2
A conversion output circuit.