JPH09260951A - Frequency synthesis circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a step width of an output frequency fine without increasing number of bits of an adder in the frequency synthesis circuit of the direct digital synthesis system. SOLUTION: A control circuit 11 receives a phase increment value 102 outputted from a frequency setting device 2 and a clock signal 101 outputted from a clock generator 1, and when a desired output frequency specified by the frequency of the received phase increment value 102 and the clock signal 101 is a prescribed frequency or below, the frequency of the clock signal 101 is reduced and fed to an adder 3 and the phase increment value 102 is increased in response to a rate of a reduced frequency of the clock signal and the resulting signal is fed to the adder 3. Furthermore, a low pass filter 6 reduces its cut-off frequency depending on the reduction rate of the frequency of the clock signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizing circuit of a direct digital synthesizing method, and more particularly to a frequency synthesizing circuit capable of reducing a step width of an output frequency.

[0002]

2. Description of the Related Art A frequency synthesizing circuit of a direct digital synthesizing system is known, in which an amplitude value corresponding to a phase is stored in a waveform data storage unit and a variable frequency can be obtained by changing a phase increment value. Known from.

FIG. 5 is a block diagram showing a configuration example of a conventional frequency synthesizing circuit of this type.
Frequency setter 2, adder 3, and waveform data storage unit 4
, DA converter 5, low-pass filter 6 '(LPF)
And

The frequency setter 2 outputs the phase increment value 102 corresponding to the desired output frequency set by the user. Phase increment value 102 output from the frequency setter 2
Is supplied to the adder 3. Every time the clock signal 101 of the frequency f _CLK is applied from the clock generator 1, the adder 3 adds the phase increment value 102 and the addition result 1 one clock before.
03 is added and the addition result 103 is output. The addition result 103 indicates the phase.

The waveform data storage unit 4 stores the amplitude value in each phase of the sine wave, and outputs the amplitude value corresponding to the addition result 103 of the adder 3. The amplitude value output from the waveform data storage unit 4 is converted into an analog signal by the DA converter 5.

Here, if the desired output frequency is f _OUT , m × f _CLK ± f _OUT (m = 1, 2, ...) Is unnecessary for the output of the DA converter 5 in addition to the desired output frequency f _OUT. Since the component is included, the unnecessary component m × f _CLK ± f _OUT is reduced by the low-pass filter 6 ′, and the desired output frequency f _OUT is obtained.

Considering the maximum feasible frequency f _MAX of the frequency synthesizer circuit shown in FIG. 5, since the unnecessary component m × f _CLK ± f _OUT is included in the output of the DA converter 5, (1) must be satisfied. f _MAX <1 × f _CLK −f _MAX (1)

By modifying the equation (1), the following equation (2) is obtained. As can be seen from equation (2), the maximum frequency f _MAX that can be output is the frequency f _{CLK of the} clock signal.
And is less than half the frequency f _CLK of the clock signal. f _MAX <f _CLK / 2 (2)

On the other hand, when the number of bits of the adder 3 is N bits, the step width S of the output frequency of the frequency synthesis circuit shown in FIG. S = f _CLK / 2 ^N (3)

As can be seen from the equation (3), in order to make the step width S of the output frequency fine, the frequency f _{CLK of the} clock signal may be lowered or the bit number N of the adder 3 may be increased. .

As described above, in order to make the step width S of the output frequency finer, the frequency f _{CLK of the} clock signal may be lowered or the bit number N of the adder 3 may be increased. _{If CLK} is lowered, the maximum frequency f _MAX that can be output is lowered.
A method of increasing the number N of bits has been generally adopted (for example, JP-A-64-34004).

[0012]

As described above, conventionally, the step width of the output frequency is made fine by increasing the number of bits of the adder. However, the frequency synthesizing circuit of the direct digital synthesizing method is used. Since the power consumption of is determined by the number of bits of the adder, the conventional technique of increasing the number of bits of the adder has a problem that the power consumption increases.

Therefore, an object of the present invention is to perform direct digital synthesis in which the step width of the output frequency can be made fine without increasing the number of bits of the adder, and the maximum output frequency can be made high. The purpose of the present invention is to provide a frequency synthesizing circuit.

[0014]

In order to achieve the above object, the present invention provides an adder which adds an input phase increment value and an addition result output one clock before itself in synchronization with a clock signal and outputs the result. A waveform data storage unit that stores an amplitude value for each phase and outputs an amplitude value corresponding to the output of the adder; a DA converter that DA converts the amplitude value output from the waveform data storage unit; A frequency synthesizing circuit of a direct digital synthesizing method, comprising a low pass filter capable of changing a cutoff frequency, the input of which is an output of a DA converter, and the input of which is a phase increment value and a clock signal. When the output frequency defined by the phase increment value and the frequency of the clock signal is lower than the predetermined frequency, the frequency of the output signal of the low pass filter is kept equal to the specified frequency. , Reducing the frequency of the input clock signal and outputting it to the adder, increasing the input phase increment value and outputting it to the adder, and reducing the cutoff frequency of the low pass filter to the lower frequency side. The control circuit is set to.

In the above configuration, when the output frequency defined by the input phase increment value and the frequency of the clock signal is lower than the predetermined frequency, the frequency of the output signal of the low pass filter is defined by the control circuit. The frequency of the input clock signal is reduced and output to the adder while the same frequency is maintained, and the input phase increment value is increased and output to the adder.

Further, according to the present invention, in order to make it possible to make the step width of the output frequency fine with a simple structure, the control circuit has an output on the lower side of the frequency lower than the specified frequency at the output of the DA converter. A shift register that shifts the input phase increment value in the direction in which the value increases and outputs the shift result to the adder, and a count value that counts the number of shifts of the shift register, in a range in which unnecessary components do not occur. To the low pass filter to set the cutoff frequency of the low pass filter to the lower band side, and the input clock signal is divided according to the count value of the counter to perform the addition. And a frequency divider that outputs the signal to the instrument.

Further, according to the present invention, the control circuit is preset so that the step width of the output frequency can be made finer as compared with the case where the phase increment value is increased by using the shift register. Based on the input phase increment value and the maximum value of the phase increment value that does not generate unnecessary components on the lower frequency side than the specified frequency at the output of the DA converter, An arithmetic circuit that calculates a multiplier and outputs the calculated multiplier to the low-pass filter to set the cutoff frequency of the low-pass filter to a lower frequency side; a multiplier calculated by the arithmetic circuit and the input And a multiplier for outputting the multiplication result to the adder, and the input clock signal is frequency-divided according to the multiplier calculated by the arithmetic circuit and output to the adder. And a frequency divider.

[0018]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. The frequency synthesizing circuit of the present embodiment receives the clock signal 101 of the frequency f _CLK output from the clock generator 1 and the phase increment value 102 output from the frequency setting device 2 as input, and sets the phase of the frequency f _CLK of the clock signal 101 to the phase. Increment value 1
The output signal 108 of the desired output frequency f _OUT defined by the reference numeral 02, and the adder 3, the waveform data storage unit 4, the DA converter 5, the low pass filter (LPF) 6, And a control circuit 11.

The control circuit 11 comprises a shift register 7, a comparator 8, a counter 9 and a frequency divider 10.

The shift register 7 fetches the phase increment value 102 output from the frequency setting unit 2 and the phase fetched every time the clock signal 101 is applied while the output signal 105 of the comparator 8 is logic "0". The increment value 102 is shifted bit by bit in the direction in which the increment value increases.

The comparator 8 outputs the output 10 of the shift register 7.
4 is compared with a predetermined threshold value Th1. If the output 104 of the shift register 7 is less than the threshold value Th1, the output signal 105 is set to logic “0”, and if it is equal to or larger than the threshold value Th1, it is set to logic “1”. . Here, although it is the value of the threshold Th1, in the present embodiment, the desired frequency f to be output to the frequency setter 2 is set.
_The threshold Th1 is the same value as the phase increment value 102 output from the frequency setting unit 2 when f _CLK / 4 is set as _OUT . That is, the threshold value Th1 is set to 1/2 of the maximum value of the phase increment value 102 at which the unnecessary component on the low frequency side of the desired output frequency f _OUT does not occur in the output of the DA converter 5.

The counter 9 outputs the output signal 105 of the comparator 8.
The number of shifts of the shift register 7 is counted by counting the number of clock signals 101 applied while the logic is "0".

The frequency divider 10 has a count value M of the counter 9.
The clock signal 101 is frequency-divided by 2 ^M in accordance with the above, and the frequency-divided clock signal 107 is output to the adder 3.

The adder 3 outputs the output 104 of the shift register 7 obtained by multiplying the phase increment value 102 output from the frequency setting unit 2 by 2 ^M and the addition result 1 output by itself one clock before.
03 and the clock signal 107 output from the frequency divider 10
Add in synchronization with.

The waveform data storage unit 4 stores the amplitude value for each phase, and outputs the amplitude value corresponding to the addition result 103 of the adder 3 indicating the phase.

The DA converter 5 DA-converts the amplitude value output from the waveform data storage unit 4 and outputs an analog signal corresponding to the amplitude value.

The low-pass filter 6 calculates the cutoff frequency f _CUT according to the count value M of the counter 9 by the following equation (4).
It has the function to change as shown in. f _CUT = f _CLK / 2/2 ^M (4)

FIG. 2 is a time chart showing the operation of this embodiment. The operation of this embodiment will be described below with reference to the drawings.

First, the desired output frequency f is set in the frequency setter 2.
Set _OUT . As a result, the frequency setter 2 outputs the phase increment value F1 corresponding to the set frequency. still,
The phase increment value F1 and the desired output frequency f _OUT have the relationship shown in the following equation (5). In the equation (5), N represents the number of bits of the adder 3. F1 = 2 ^N · f _OUT / f _CLK (5)

When the frequency incrementer 2 outputs the phase increment value F1, the shift register 7 takes in the phase increment value F1 and outputs it to the comparator 8.

The comparator 8 compares the phase increment value F1 output from the shift register 7 with a predetermined threshold Th1. If F1 <Th1, the output signal 105 is set to logic "0", and F1≥ In the case of Th1, the output signal 105 is logic "1". Now, assuming that the phase increment value F1 output from the frequency setter 2 is in the range shown in the following equation (6), the output signal 105 of the comparator 8 becomes a logic "0". Th1 / 4 ≦ F1 <Th1 / 2 (6)

After that, the clock generator 1 starts its operation and starts outputting the clock signal 101.

When the first clock signal 101 is applied, the shift register 7 outputs the output signal 105 of the comparator 8.
Is a logical "0", the held phase increment value F1 is shifted by 1 bit in the direction of increasing the value. As a result, the output 104 of the shift register 7 becomes the phase increment value F1 × 2. Also, the counter 9
When the first clock signal 101 is applied, the output signal 105 of the comparator 8 is logic “0”,
The count value is incremented by 1 to "1". Also, the counter 9
Since the count value of 1 becomes “1”, the frequency divider 10 outputs the clock signal 107 obtained by dividing the clock signal 101 by 2 to the adder 3, and the low pass filter 6 outputs the cutoff frequency f _CUT as f _CLK. / 4.

Even if the output 104 of the shift register 7 indicates the phase increment value F1 × 2, since the threshold value Th1 is larger than the phase increment value F1 × 2, the signal 105 output from the comparator 8 is It remains a logic "0".

Thereafter, when the second clock signal 101 is applied, the shift register 7 holds the phase increment value F1 × 2 held therein because the output signal of the comparator 8 is logic "0". Is shifted by 1 bit. As a result, the output 104 of the shift register 7 shows the phase increment value F1 × 4. Also, the counter 9 outputs the output signal 10 of the comparator 8 when the second clock signal 101 is applied.
Since 5 is a logical "0", the count value is incremented by 1 to "2". Further, the count value of the counter 9 is "2".
Therefore, the frequency divider 10 _divides the clock signal 101 having the frequency f _CLK by 4 and adds the clock signal 107 to the adder 3
To the cut-off frequency f
Let _CUT be f _CLK / 8.

When the output 104 of the shift register 7 indicates the phase increment value F1 × 4, the phase increment value F1 × 4 becomes equal to or more than the threshold Th1. Therefore, the comparator 8 outputs the output signal 1
05 is set to logic "1".

When the output signal 105 of the comparator 8 becomes "1", the shift register 7 stops the shift operation and the counter 9 stops the count operation. Therefore, thereafter, the adder 3 is supplied with the clock signal 107 having the frequency f _CLK / 4 and the phase increment value F1 × 4.
As a result, the addition result 103 output from the adder 3 is
F1 is synchronized with the clock signal 107 of frequency f _CLK / 4
× 4, F1 × 8, F1 × 12, ...
It increases in steps.

The waveform data storage unit 4 outputs the amplitude value corresponding to the phase indicated by the addition result of the adder 3, and the DA converter 5
Performs DA conversion of the amplitude value output from the waveform data storage unit 4, and the low pass filter 6 reduces unnecessary components included in the output of the DA converter 5.

As described above, according to the present embodiment, when the desired output frequency f _OUT is lower than ¼f _CLK , the frequency of the clock signal 107 applied to the adder 3 is output from the clock generator 1. Since it becomes lower than the frequency f _CLK of the clock signal 101 to be generated, the step width S of the output frequency can be made small, as can be seen from the above formula (3). As described above, even if the frequency of the clock signal 107 applied to the adder 3 is reduced, the phase increment value supplied to the adder 3 is increased according to the reduction rate, so the low pass filter 6 Output signal 10 output from
The frequency of 8 is the frequency set by the frequency setting device 2. In the above-described embodiment, the value of the threshold Th1 is set to f _CLK / 4, but the value of the threshold Th1 is set to f _CLK depending on the cutoff characteristic of the low pass filter 6 and the purpose of use of the frequency synthesis circuit. The value may be smaller than / 4.

FIG. 3 is a diagram for comparing the present embodiment with the conventional technique shown in FIG. FIG. 3A shows a signal waveform with a frequency of 1.5 MHz. FIG.
(C) is the conventional frequency synthesizer circuit shown in FIG. 5,
In the frequency synthesizing circuit of this embodiment shown in FIG. 1, the number of bits N of the adder 3 is "3", the frequency f _CLK of the clock signal 101 generated by the clock generator 1 is 8 MHz, and the frequency setting unit 2 is Set the desired output frequency f _OUT to 1.5M
It is the figure which showed the output waveform of the low pass filter 6 when it was set to Hz.

The phase increment value corresponding to the desired output frequency f _OUT = 1.5 MHz is "001.1." However, in the conventional frequency synthesizer circuit shown in FIG. 5, the step width S of the output frequency is From the above formula (3), S = 8 MHz / 2 ³
Since it is = 1 MHz, "001" rounded down after the decimal point is added to the adder 3 as a phase increment value. As a result, in the conventional frequency synthesizer circuit shown in FIG.
A signal with a frequency of 1 MHz as shown in FIG. 3B is output.

On the other hand, in the frequency synthesizing circuit of this embodiment shown in FIG. 1, the clock signal 101 having a frequency of 8 MHz output from the clock generator 1 is divided by 2 to generate the clock signal 107 having a frequency of 4 MHz. The phase increment value “00” applied to the adder 3 and output from the frequency setting unit 2
1.1 "is doubled (shifted by 1 bit) and the phase increment value is" 0 ".
11 ”is applied to the adder 3, so that FIG.
A signal of 1.5 MHz as shown in (C) is output.

FIG. 4 is a block diagram of another embodiment of the present invention. The difference between this embodiment and the embodiment shown in FIG. 1 is that
The point is that a control circuit 15 including an arithmetic circuit 12, a multiplier 13, and a frequency divider 14 is provided in place of the control circuit 11.
Note that the same reference numerals as those in FIG. 1 indicate the same parts.

In the arithmetic circuit 12, the maximum value of the phase increment value (the desired output frequency f) that does not generate an unnecessary component in the low frequency side of the desired output frequency f _{OUT at} the output of the DA converter 5 is output.
_The same value as the phase increment value output from the frequency setter 2 when _CLK / 4 is set in the frequency setter 2) is preset as the threshold Th2, and the frequency incrementer 102 outputs the phase increment value 102. And the threshold value Th2 is divided by the phase increment value 102 output from the frequency setting unit 2, and the output signal 109 indicating the integer part D of the division result is output to the multiplier 13, the frequency divider 14 and the low pass filter 6. To do.

The multiplier 13 outputs the phase increment value 102 output from the frequency setting unit 2 and the output signal 109 of the arithmetic circuit 12.
Is multiplied by a value D indicated by and the multiplication result 110 is output to the adder 3.

The frequency divider 14 outputs the clock signal 101 of the frequency f _CLK output from the clock generator 1 to the arithmetic circuit 1.
The clock signal 111 having the frequency f _CLK / D _divided by the value D indicated by the output signal 109 of 2 is output to the adder 3.

The low-pass filter 6 has its cutoff frequency f _CUT according to the value D indicated by the output signal 109 of the calculator 12, as shown in the following equation (7). f _CUT = f _CLK / 2 ÷ D (7)

As described above, in this embodiment, the phase increment value 10
2 is multiplied by D by the multiplier 13, and the frequency of the clock signal applied to the adder 3 is set to 1 / D by the frequency divider 14. Therefore, the step width of the output frequency is set in the same manner as the embodiment shown in FIG. It can be finely divided.

[0050]

As described above, according to the present invention, when the desired output frequency defined by the input phase increment value and the frequency of the clock signal is lower than the predetermined frequency, the output signal output from the low pass filter. A control circuit that keeps the frequency equal to the output frequency specified above, reduces the frequency of the input clock signal and outputs it to the adder, and increases the input phase increment value and outputs it to the adder. Since it is provided, the step width of the output frequency can be made fine without increasing the number of bits of the adder. When the desired output frequency f _OUT is higher than the predetermined frequency, the step width of the output frequency cannot be made fine, but when the desired output frequency f _OUT is high, the frequency accuracy Δf / f _OUT (Δf is Since the difference between the desired output frequency f _OUT and the actual output frequency is a small value, there is no practical problem. Further, when the desired output frequency is higher than the predetermined frequency, the clock signal applied to the adder is not reduced, so that the maximum outputtable frequency can be increased.

Further, according to the present invention, since the phase increment value input by the shift register is increased and the frequency of the clock signal input by the frequency divider is decreased, the step width of the output frequency can be reduced with a simple structure. It can be finely divided.

Further, according to the present invention, the multiplier for the input phase increment value is obtained by the arithmetic circuit, the phase increment value outputted to the adder is increased according to the multiplier obtained by the arithmetic circuit, and the clock outputted to the adder. Since the frequency is reduced, the step width of the output frequency can be made finer than when the phase increment value is increased by using the shift register.

[Brief description of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of FIG.

FIG. 3 is a diagram for comparing the output signal of the frequency synthesis circuit of the embodiment shown in FIG. 1 with the output signal of the conventional frequency synthesis circuit shown in FIG.

FIG. 4 is a block diagram of another embodiment of the present invention.

FIG. 5 is a block diagram for explaining a conventional technique.

[Explanation of symbols]

 1 ... Clock generator 2 ... Frequency setting device 3 ... Adder 4 ... Waveform data storage unit 5 ... DA converter 6, 6 '... Low pass filter (LPF) 7 ... Shift register 8 ... Comparator 9 ... Counter 10 ... Frequency divider 11 ... Control circuit 12 ... Arithmetic circuit 13 ... Multiplier 14 ... Frequency divider 15 ... Control circuit

Claims (3)

[Claims] 1. An adder for adding and outputting an input phase increment value and an addition result output one clock before itself in synchronization with a clock signal, and an amplitude value for each phase is stored to store the amplitude value. The waveform data storage unit that outputs the amplitude value corresponding to the output, and the amplitude value output from the waveform data storage unit are DA
A frequency synthesizing circuit of a direct digital synthesizing method, comprising a DA converter for converting and a low-pass filter having an output of the DA converter as an input and capable of changing a cutoff frequency. When the output frequency defined by the input phase increment value and the frequency of the clock signal is lower than a predetermined frequency, the frequency of the output signal of the low pass filter becomes equal to the defined frequency. To reduce the frequency of the input clock signal to output to the adder and increase the input phase increment value to output to the adder, and further reduce the cutoff frequency of the low pass filter. A frequency synthesizing circuit comprising a control circuit for setting to a low frequency side. 2. The control circuit is configured to increase the input phase increment value in a direction in which the value is increased in a range in which an unnecessary component on a lower frequency side than the specified frequency does not occur in the output of the DA converter. A shift register that shifts and outputs the shift result to the adder, counts the number of shifts of the shift register, and outputs the count value to the low pass filter to lower the cutoff frequency of the low pass filter. The frequency according to claim 1, further comprising: a counter that is set on a frequency range side; and a frequency divider that divides the input clock signal according to a count value of the counter and outputs the divided clock signal to the adder. Synthesis circuit. 3. The maximum value of a phase increment value that does not generate an unnecessary component on the output side of the DA converter, which is lower than the specified frequency, in the control circuit, A multiplier for the input phase increment value is calculated based on the input phase increment value, and the calculated multiplier is output to the low pass filter to set the cutoff frequency of the low pass filter to the lower band side. An arithmetic circuit to be set, a multiplier that multiplies the multiplier calculated by the arithmetic circuit and the input phase increment value and outputs the multiplication result to the adder, and a multiplier that is calculated according to the multiplier calculated by the arithmetic circuit. The frequency synthesizer according to claim 1, further comprising: a frequency divider that divides the input clock signal and outputs the divided clock signal to the adder.