JPH09260646A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely ensure an electrical insulation of a package side electrode plate from a gate runner by a method, wherein in an element of a MOS structure, the pressing force from the package side electrode plate is prevented from being transferred to gate electrodes and the package side electrode plate and the gate runner are prevented from coming into contact with each other. SOLUTION: P-type regions 3 and n-type high-concentration regions 4 are formed in the surface layer of an n-type semiconductor substrate 2, gate electrodes 5 are formed on the surface layer, insulating oxide films 12 are respectively formed on each gate electrode 5, a first layer Al-Si metal film 7 is adhered on the films 12 and an emitter region 11, a polysilicon film 8 is adhered on the film 7, which is positioned on the electrodes 5, a second layer Al-Si metal film 9 is formed on the film 8 and the film 7, which is positioned on the region 11, and the films 7 and 9 are formed into an emitter electrode 13. Here, a gate runner 20, which is connected to the electrodes 5, is formed on the substrate 2 via an oxide film 6a, a polyimide film 8a is formed on a wiring metal film 20b of the runner 20 and a package side electrode plate 30 and the film 20b of the runner 20 are surely insulated from each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is intended for a power switching element having a MOS structure such as an insulated gate bipolar transistor (IGBT), and has a first main electrode (emitter) and a control electrode (gate) on one main surface of a substrate. , A semiconductor device in which a semiconductor chip having a second main electrode (collector) on another main surface is incorporated in a package.

[0002]

2. Description of the Related Art IGBTs are widely used as power switching elements for applications such as motor PWM control inverters. Further, since this IGBT is of a voltage drive type and is easy to handle, the demand for the market is increasing toward a larger capacity, and along with the increase in the size of a semiconductor chip, the capacity of an element tends to be further increased.

By the way, in an insulated gate element (element having a MOS structure) such as an IGBT, an emitter electrode as a main electrode and a gate electrode as a control electrode are formed side by side on one main surface of a semiconductor chip. . Therefore IG
When the BT chip is packaged and assembled, the collector on the second main surface side can be directly mounted on the metal base (provided on the lower surface side of the case) that also serves as a radiator, but The emitter electrode and the gate electrode must be separately drawn out via the external lead-out terminal. Therefore, in the conventional package structure, an external lead terminal for the emitter and the gate is provided on the upper surface side of the case, and an aluminum conductor wire having a wire diameter of about 300 μm is provided between the emitter electrode and the external lead terminal and between the gate electrode and the external lead terminal. The wire is bonded and pulled out.

However, in such a conventional structure, although heat can be dissipated from the collector side, heat cannot be dissipated from the emitter side, which has been a hindrance in increasing the capacity of the device. Therefore, the inventors of the present invention have proposed a structure called an emitter current collecting electrode, which does not form a MOS structure part on a part of the emitter side surface of a MOS structure element and has a role of heat dissipation and a current path. The element called the contact terminal body, which can apply pressure only to the electric electrode, applied pressure to the element, achieving wire bonding to the main electrode (Fuji Times 1994 5
Monthly issue pp283-287).

[0005]

In this structure, not only the heat radiation from the collector side but also the heat radiation from the emitter side is possible, so that the current density can be increased and the wire bonding to the main electrode becomes unnecessary. Although it has the advantage that the reliability can be greatly improved, the
It has a drawback in that it has no choice but to create an invalid area in which the S structure is not provided. The reason for providing this collector electrode is the IGBT.
In an element with a MOS structure like the one described above, the emitter electrode is made to extend over the gate electrode through the oxide film. Therefore, if the package-side electrode plate is brought into pressure contact with the entire surface of the emitter electrode, the gate electrode is also pressed. This is because the characteristics are changed or deteriorated due to the addition of, so that it is not put to practical use. Further, since the gate runner connected to the gate electrode (wired on the semiconductor chip and electrically connected to the gate electrode and the external lead terminal) is not conventionally covered with an insulating film such as polyimide, Contact, emitter
Sometimes the gates were short-circuited.

In order to solve the above-mentioned drawbacks, the present invention provides
In order not to apply pressure to the emitter electrode on the gate electrode, the emitter electrode other than this region is brought into contact with the package-side electrode plate, and the structure in which the invalid region of the collector electrode is not provided is provided. (EN) Provided is a semiconductor device having a MOS structure capable of achieving a large active area with a large double-sided cooling effect without changing the characteristics due to a pressing force, and inserting an insulating film between the package side electrode plates on the gate runner. The gap between this insulating film and the electrode plate on the package side ensures that the gate runner and the electrode plate on the package side do not come into contact with each other, and the electrical connection between the gate runner and the electrode plate on the package side is prevented. An object of the present invention is to provide a highly reliable semiconductor device having a MOS structure by ensuring insulation. It should be noted that the electrical insulation can be secured only by the insulating film without any voids, but the voids are provided in order to further improve the insulating property.

[0007]

In order to achieve the above object, a semiconductor chip of MOS structure having a first main electrode and a control electrode on a first main surface and a second main electrode on a second main surface is provided. , A flat package in which an insulating outer cylinder is interposed between a pair of common electrode plates whose both surfaces are exposed, and between the first main electrode of the semiconductor chip and the common electrode plate on the package side facing the first main electrode. A contact terminal body that also functions as a pressure member, a conductor, and a heat radiator is interposed, and the first main electrode is also covered on the control electrode via the first insulating film on the control electrode. Is a two-layer structure, the second insulating film is sandwiched between the first layer and the second layer of the first main electrode on the region other than the control electrode, and the surface height of the first main electrode other than on the control electrode is In the semiconductor device in which the contact height is higher than the surface height of the first main electrode on the control electrode, Is arranged, a third insulating film configured to be coated on the surface of the wiring metal film connected to the control electrode.
The third insulating film may be formed of the same material and have the same thickness as the second insulating film. Further, the thickness of the second layer of the first main electrode may be 5 μm or more and 20 μm or less.

With the above structure, the surface height of the emitter electrode other than on the gate electrode is made higher than the surface height of the emitter electrode on the gate electrode, so that the emitter electrode on the gate electrode and the electrode plate on the package side However, the emitter electrode in the region other than the gate electrode is in contact with the electrode plate over the entire surface. Therefore, no pressure is applied to the gate electrode, and there is no change in characteristics due to pressurization. On the other hand, the heat dissipation from the emitter electrode is improved and the current collecting electrode is not required, so that the entire chip area can be effectively utilized. If the current capacity is the same, the chip area can be reduced. Also, by sandwiching an insulating film between the gate runner (wiring metal film) and the electrode plate on the package side, or by opening a gap between them, it is possible to prevent contact between the gate runner and the electrode plate on the package side. It is possible to stably secure the voltage between the emitters. In addition, the manufacturing cost can be reduced as compared with the case where the package side electrode plate is processed into a concave shape to prevent contact with the gate runner.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a cross-sectional view of an essential part showing an embodiment of the present invention. A p-type region 3 is selectively formed on the surface layer of one main surface of the n-type semiconductor substrate 2 by diffusion or the like, and a high-concentration n-type region 4 is formed on the surface layer of the p-type region 3 to form a high-concentration n-type. A gate electrode 5 made of polysilicon is formed on a p-type region 3 sandwiched between a region 4 and an n-type semiconductor substrate 2 via a gate oxide film 6, and an insulating oxide film 12 is formed on the gate electrode 5. To be done. A first-layer Al-Si metal film 7 is formed on the oxide film 12 and the emitter region 11 where the semiconductor is exposed, and the Al-S on the emitter region 11 is formed.
A polyimide film 8 is formed on the surface of the i metal film 7 so as to be thicker than the total thickness of the gate electrode 5 and the oxide films 6 and 12, and the polyimide film 8 and the first-layer Al-Si metal film 7 are exposed. A second-layer Al-Si metal film 9 is formed in the region where the metal layer 9 is present. The Al-Si metal films 7 and 9 become the emitter electrode 13. Although not shown, the polysilicon wiring portion 20a of the gate runner that is connected to the gate electrode 5 and is made of polysilicon similar to the gate electrode 5 has an oxide film 6a formed in the same step as the gate oxide film 6. Is formed on the n-type semiconductor substrate 2 via. Furthermore, the above-mentioned insulating oxide film 1
An insulating oxide film 12a is formed on the polysilicon wiring portion 20a in the same step as that of Step 2, and a window is opened to form a first layer of Al--S.
The wiring metal film 20b of the gate runner formed in the same step as the i metal film 7 is connected to the polysilicon wiring portion 20a. Further, the polyimide film 8 is formed on the wiring metal film 20b.
A polyimide film 8a formed in the same step as above is formed. With such a configuration, the electrode plate 30 on the package side (also referred to as an emitter terminal in the contact terminal body) and the wiring metal film 20b of the gate runner are reliably insulated. Further, the thickness of the Al-Si metal film 9 of the second layer is 5 μm.
By setting m to 20 μm (, the gap between the electrode plate 30 on the package side and the polyimide 8a can be maintained even if the pressure portion 10 of the emitter electrode 13 in contact with the electrode plate 30 on the package side is deformed by pressure or power cycle. The minimum thickness of the second Al—Si metal film 9 is set to 5 μm because the deformation of the pressing portion 10 is usually about 2 μm to 4 μm. The value is determined so that the electrode plate 30 on the package side does not come into contact with the wiring metal film 20a of the gate runner by making it thicker than this deformation amount.
Further, the maximum value is set to 20 μm because the deformation amount does not exceed the value even in a severe environment. Of course, there is no problem if it is made thicker. The gate runner 20 is composed of a polysilicon wiring portion 20a and a wiring metal film 20a.

In this structure, the surface of the emitter electrode 13 formed on the polyimide film 8 has a convex shape, and this portion serves as the pressing portion 10 that contacts the electrode plate 30 on the package side. On the other main surface of the n-type semiconductor substrate 2, a p-type layer 1 is formed by diffusion or the like. Further, a portion corresponding to the p-type layer 1 is formed as a p-type semiconductor substrate, and a portion corresponding to the n-type semiconductor substrate 2 is formed as an n-type layer by an epitaxial growth layer.
Other regions may be manufactured so as to have the same structure as described above.

[0011]

According to the present invention, even if the emitter electrode is pressed by the electrode plate on the package side, the pressing force is not directly transmitted to the gate electrode and an unreasonable force is not applied to the gate electrode. Further, since the electrode plate on the package side and the gate runner can be reliably insulated, a highly reliable semiconductor device can be obtained.

Further, since the electrode plate on the package side contacts the emitter electrode, the heat dissipation is better than the contact through the collector electrode, and the area where the collector electrode is formed can be effectively utilized as an active region. Therefore, the current capacity of the element can be increased. If the current capacities are the same, the chip size can be reduced and the chip cost can be reduced.

[Brief description of drawings]

FIG. 1 is a structural diagram of a main part showing an embodiment of the present invention.

[Explanation of Codes] 1 p-type layer 2 n-type semiconductor substrate 3 p-type region 4 high-concentration n-type region 5 gate electrode 6 gate oxide film 6a oxide film 7 first-layer Al-Si metal film 8 polyimide film 8a polyimide film 9 Al-Si metal film of the second layer 10 Pressure part 11 Emitter region 12 Insulating oxide film 12a Insulating oxide film 13 Emitter electrode 20 Gate runner 20a Polysilicon wiring part 20b Wiring metal film of gate runner 30 Package side electrode plate

Claims (3)

[Claims] 1. A semiconductor chip having a MOS structure having a first main electrode and a control electrode on a first main surface, and a second main electrode on a second main surface, and an insulating outer layer between a pair of common electrode plates exposed on both sides. A contact terminal body which is incorporated into a flat package having a cylinder interposed between the first main electrode of the semiconductor chip and a common electrode plate on the package side facing the first main electrode, and which also functions as a pressure member, a conductive member, and a heat radiator. , Via the first insulating film on the control electrode, the control electrode also covers the first main electrode,
The first main electrode has a two-layer structure, the second insulating film is sandwiched between the first layer and the second layer of the first main electrode on the region other than the control electrode, and the first main electrode except on the control electrode. In a semiconductor device in which the surface height of the control electrode is higher than the surface height of the first main electrode on the control electrode, the third insulating film is provided on the surface of the wiring metal film which is arranged under the contact terminal body and is connected to the control electrode. A semiconductor device characterized by the above. 2. The semiconductor device according to claim 1, wherein the third insulating film is formed of the same material and has the same thickness as the second insulating film. 3. The semiconductor device according to claim 1, wherein the thickness of the second layer of the first main electrode is 5 μm or more and 20 μm or less.