JPH09260604A - Manufacture of semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lower the contact resistance of a DRAM (dynamic type semiconductor substrate device) to a bit line and a semiconductor substrate. SOLUTION: A MOS transistor in a memory cell part is formed on a p-type semiconductor substrate 1 and after the formation of an interlayer insulating film 7 on the entire surface of the substrate 1, a storage electrode 8 is formed, so as to come in contact with an N<+> -type source diffused layer 5 of the transistor. Next, a capacitor insulating film 9 is formed, so as to cover the storage electrode 8 and after the formation of a plate electrode 10 so as to cover the capacitor insulating film 9, another insulating film 11 is formed so as to cover the entire surface of the substrate 1 ant then a contact hole 12 coming in contact with an N<+> type drain diffused layer 6 of the transistor is formed. After the formation of a metallic wiring which becomes a bit line in the hole 12, A PSG film 14 containing much phosphorus is to be formed on the entire surface of the substrate 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more specifically, a bit line in a method of manufacturing a dynamic semiconductor memory device (hereinafter referred to as DRAM) having stacked capacitor memory cells. The present invention relates to a technique for reducing the contact resistance between a silicon substrate and a silicon substrate.

[0002]

2. Description of the Related Art Conventionally, in a DRAM, a wiring layer used for a bit line and a wiring layer of a peripheral circuit portion usually have a two-layer structure of a tungsten silicide film (WSix) and a polysilicon film. Hereinafter, a method of manufacturing this type of semiconductor memory device will be described with reference to FIG.

Reference numeral 51 shown in FIG. 4 is a semiconductor substrate of one conductivity type.
For example, on a P-type silicon substrate, a LOCOS oxide film 52 is formed in a field region on the substrate 51, and a gate oxide film 53 is formed in other element forming regions. In this process,
For example, the substrate 51 is a pad oxide film of about 500 Å and about 100
The silicon nitride film deposited by the LPCVD method of 0Å is coated, and the silicon nitride film is patterned so as to cover only the active region. After that, a LOCOS oxide film 52 of about 6000 Å is formed in the field region by selective oxidation. Further, a gate oxide film 53 of about 170 Å is formed on the active region of the substrate 51 by thermal oxidation.

Subsequently, after depositing a polysilicon film on the entire surface by the LPCVD method, impurities such as phosphorus are diffused to render the polysilicon film conductive. Then, this polysilicon film is patterned to form M in the memory cell portion.
The gate electrode 54 of the OS transistor is formed. That is,
In this step, for example, a polysilicon film of about 2000 liters is deposited on the entire surface by the LPCVD method to dope into the N + type. This gate electrode 54 functions as a word line of the memory.

Next, phosphorus, arsenic and the like are implanted by using the LOCOS oxide film 52 and the gate electrode 54 as a mask to form N + type diffusion layers 55 and 56 which form a MOS transistor in the memory cell portion. Then, an interlayer insulating film 57 made of a silicon oxide film is deposited on the entire surface of the substrate by LPCVD.

Next, one diffusion layer, for example, the source diffusion layer 5
After forming a contact hole on the substrate 5, a polysilicon film is deposited by LPCVD and patterned to form a storage electrode 58. In this step, for example, a resist film is used to form the interlayer insulating film 57 and the gate oxide film 53 on the diffusion layer 55.
Contact hole is formed on the surface, and a polysilicon film is
It is adhered to the thickness of 000Å by the LPCVD method. After that, the polysilicon film has increased conductivity due to diffusion of impurities of phosphorus.

Subsequently, a capacitor insulating film 59 made of a silicon oxide film and a silicon nitride film and a polysilicon film are deposited on the entire surface and then patterned to form a cell plate electrode 60. In this process, for example, about 120 Å LP
Attach a silicon nitride film formed by the CVD method,
Dry oxidation is performed at 0 ° C. for 30 minutes. After that, L on the entire surface
Deposit about 1500 Å polysilicon film by PCVD method,
Dope to N + type. Then, a region of the polysilicon film to be the cell plate electrode 60 is covered with a resist film,
Using this as a mask, the polysilicon film, the silicon nitride film, and the silicon oxide film are etched to remove the cell plate electrode 6
Form 0.

Then, after forming an interlayer insulating film 61 on the entire surface, a contact hole 62 is formed on the other diffusion layer, for example, the drain diffusion layer 56. Next, for example, a tungsten silicide film (WSix) and a polysilicon film are formed and patterned to form the metal wiring 63 to be a bit line. In this step, after the tungsten silicide film (WSix) and the polysilicon film are formed, phosphorus is added to, for example, 1E15 / cm 2 or more (1E15).
Means 1 times 10 to the 15th power. The same applies hereinafter. By implanting under the conditions of (1), the contact resistance between the metal wiring 63 and the silicon substrate 51 is reduced. FIG. 5 shows the relationship between the contact resistance and the amount of ion implantation in a conventional semiconductor memory device having, for example, a 0.8 μm rule.
When phosphorus is ion-implanted under the condition of 5 / cm 2, the contact resistance is about 70 [Ω].

Next, a so-called non-doped silicon oxide film 64 containing no impurities is formed by LPCVD or APCVD so as to cover the metal wiring 63 on the entire surface of the substrate, and then an interlayer insulating film 65 is formed thereon. Form. Subsequently, after forming an aluminum film on the interlayer insulating film 65, patterning is performed through a resist film (not shown) to form an aluminum wiring 66, and a passivation film 67 is formed on the entire surface.

In the semiconductor memory device formed as described above, in order to reduce the contact resistance between the metal wiring and the silicon substrate, as described above, a tungsten silicide film (WSix) for metal wiring has been conventionally used. After forming the polysilicon film, for example, 1E15 / cm2
Since it is necessary to perform ion implantation under the high implantation conditions as described above, the number of manufacturing processes is increased and workability is poor.

[0011]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to reduce the contact resistance between the bit line of the DRAM and the silicon substrate by another method instead of the ion implantation step.

[0012]

Therefore, according to the present invention, a MOS transistor of a memory cell portion is formed on a semiconductor substrate,
After forming an insulating film so as to cover the transistor, a storage electrode is formed so as to contact one diffusion layer of the transistor. Next, a capacitance insulating film is formed so as to cover the storage electrode, a cell plate electrode is formed so as to cover the capacitance insulating film, and an interlayer insulating film is formed so as to cover the entire surface of the substrate. After forming a contact hole that contacts the other diffusion layer of the transistor, a bit line is formed in the contact hole. Then, an insulating film containing impurities is formed on the entire surface of the substrate so as to cover the bit lines.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a method for manufacturing a semiconductor memory device of the present invention will be described in detail below with reference to the drawings.
Reference numeral 1 shown in FIG. 1 is a semiconductor substrate of one conductivity type, for example, a P-type silicon substrate, and a LOCOS is formed in a field region on the substrate 1.
The oxide film 2 is formed, and the gate oxide film 3 is formed in the other element formation regions. In this step, for example, about 50
The pad oxide film of 0 Å and the silicon nitride film of about 1000 Å deposited by the LPCVD method are coated, and the silicon nitride film is patterned so as to cover only the active region. After that, about 6000 Å L was added to the field area by selective oxidation.
The OCOS oxide film 2 is formed. Further, a gate oxide film 3 of about 170 Å is formed on the active region of the substrate 1 by thermal oxidation.

Then, after depositing a polysilicon film on the entire surface by the LPCVD method, impurities such as phosphorus are diffused to render the polysilicon film conductive. Then, this polysilicon film is patterned to form M in the memory cell portion.
The gate electrode 4 of the OS transistor is formed. That is, in this step, for example, a polysilicon film of about 2000 liters is deposited on the entire surface by the LPCVD method to dope into the N + type. This gate electrode 4 functions as a word line of the memory.

Next, phosphorus, arsenic, etc. are implanted using the LOCOS oxide film 2 and the gate electrode 4 as a mask to diffuse the N + type source diffusion layer 5 and the N + type drain of the MOS transistor in the memory cell section. Form layer 6. continue,
An interlayer insulating film 7 made of a silicon oxide film is deposited on the entire surface of the substrate by a CVD method. Subsequently, after forming a contact hole that contacts the source diffusion layer 5, a polysilicon film is deposited on the entire surface by LPCVD and patterned to form a storage electrode 8. In this step, for example, a resist film is used to form the interlayer insulating film 7 on the source diffusion layer 5.
A contact hole is formed in the gate oxide film 3 and a polysilicon film is deposited on the entire surface by LPCVD to a thickness of about 3000 Å. After that, the polysilicon film has increased conductivity due to diffusion of impurities of phosphorus.

Next, a capacitor insulating film 9 made of a silicon oxide film and a silicon nitride film and a polysilicon film are deposited on the entire surface and then patterned to form a cell plate electrode 10. In this process, for example, LPCV of about 120Å is
A silicon nitride film formed by the D method is attached, and the temperature is about 900 ° C.
Dry oxidation for 30 minutes. After that, LPC on the entire surface
Approximately 1500Å polysilicon film is attached by VD method, and N +
Dope the mold. Subsequently, a region of the polysilicon film, which will be the cell plate electrode 10, is covered with a resist film, and the polysilicon film, the silicon nitride film, and the silicon oxide film are etched using the resist film as a mask to form the cell plate electrode 10.

After that, an interlayer insulating film 11 is formed on the entire surface, and then a contact hole 12 is formed on the N + type drain diffusion layer 6. Through the steps so far, the semiconductor device becomes
The state shown in FIG. 1 is obtained. Next, as shown in FIG. 2, for example, a tungsten silicide film (WSix) and a polysilicon film are formed and patterned to form the metal wiring 13 to be a bit line.

Then, a so-called PSG (Phosho Silicate Glass) film 14, which is an insulating film containing phosphorus by LPCVD so as to cover the metal wiring 13 on the entire surface of the substrate.
Is formed to about 1000Å to 2000Å. In addition, PS
The phosphorus concentration contained in the G film 14 needs to be such that the PSG film does not flow due to the heat treatment in the subsequent step. For example, when the heat treatment is performed at 900 ° C., the phosphorus concentration is, for example, about 3 wt% (weight percent). The optimum concentration is about 5 wt%. Then, as shown in FIG. 3, an interlayer insulating film 15 is formed on the entire surface of the substrate. As described above, in the above step, the PSG film 14 is formed on the metal wiring 13 in place of the conventional non-doped silicon oxide film, so that the phosphorus contained in the PSG film 14 is automatically converted into metal by the heat treatment in the subsequent step. Since it is diffused into the wiring 13, the contact resistance between the metal wiring 13 and the silicon substrate 1 can be reduced without performing ion implantation as in the conventional case.
The contact resistance value data in this case is conveniently shown in the graph showing the relationship of the contact resistance with respect to the conventional ion implantation amount of FIG. 5. For example, the contact resistance in the semiconductor memory device of the 0.8 μm rule is However, it has been confirmed by experiment that it is about 50 [Ω]. Note that phosphorus may be diffused from the BPSG film 15 formed on the PSG film 14.

Then, after forming an aluminum film on the interlayer insulating film 15, an aluminum wiring 16 is formed by patterning through a resist film (not shown), and a passivation film 17 is formed on the entire surface as shown in FIG. Form. By the heat treatment at about 900 ° C. at the time of forming the passivation film 17, phosphorus in the PSG film 14 is diffused in the metal wiring 13 and the contact resistance is reduced.

As described above, according to the present invention, the PSG film 14 is formed on the metal wiring 13 made of the tungsten silicide film (WSix) and the polysilicon film, so that phosphorus in the PSG film 14 is automatically removed by the heat treatment in the subsequent process. Since it is diffused into the metal wiring 13, the contact resistance between the metal wiring 63 and the silicon substrate 51 can be reduced without performing the conventional step of injecting phosphorus under the condition of 1E15 / cm 2 or more. Since the resistance is reduced, workability is improved.

[0021]

As described above, according to the present invention, the contact resistance between the bit line of the DRAM and the silicon substrate can be reduced and the workability can be improved without performing the ion implantation step which has been conventionally required. To do.

[Brief description of drawings]

FIG. 1 is a first process showing a manufacturing process of a semiconductor memory device of the present invention.
FIG.

FIG. 2 is a second view showing the manufacturing process of the semiconductor memory device of the present invention.
FIG.

FIG. 3 is a third process showing the manufacturing process of the semiconductor memory device of the present invention.
FIG.

FIG. 4 is a sectional view showing a conventional semiconductor memory device.

FIG. 5 is a diagram showing a relationship between a conventional ion implantation amount and contact resistance.

Claims (2)

[Claims] 1. A step of forming a MOS transistor of a memory cell portion on a semiconductor substrate, a step of forming an insulating film so as to cover the transistor, and a storage electrode so as to contact with one diffusion layer of the transistor. A step of forming, a step of forming a capacitive insulating film so as to cover the storage electrode, a step of forming a cell plate electrode so as to cover the capacitive insulating film, and an interlayer insulation so as to cover the entire surface of the substrate. A step of forming a film, a step of forming a bit line in the contact hole after forming a contact hole that comes into contact with the other diffusion layer of the transistor, and an impurity so as to cover the bit line on the entire surface of the substrate. And a step of forming an included insulating film and a step of forming an interlayer insulating film on the entire surface of the substrate. The method of manufacturing a semiconductor memory device that. 2. The method for manufacturing a semiconductor memory device, wherein the impurity contained in the insulating film formed on the bit line is phosphorus.