JPH09260599A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enlarge the electrode surface area and realize as desired electrode configuration by forming a lower electrode by depositing an electrode material in an upper surface of an oxide film wherein an exposed surface, that is, an uneven inner wall of a semiconductor board is deposited on the uppermost layer. SOLUTION: A resist film 7 is formed into a pattern in a lower wiring 1 and a resist film is set by ultraviolet ray irradiation and high temperature baking treatment. An oxide film 8 is deposited in a region except the resist film 7. The resist film 7 of a desired film thickness is formed into a pattern on a resist film of a lower layer changing an opening size. An oxide film 8 is deposited as thick as the resist film 7 and the resist film 7 and the oxide film 8 are laminated one by on. Therefore, a width and a depth of an electrode configuration can be designed freely and a capacitor of a large capacity and a large electrode surface area can be formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor, which comprises forming a lower electrode having a desired shape. More specifically, when forming a capacitor such as a DRAM, an oxidation that can be selectively grown on a resist film is performed. The present invention relates to a method for manufacturing a semiconductor device, which includes forming a lower electrode that enables manufacturing of a large-capacity capacitor by using a film.

[0002]

2. Description of the Related Art MOS type semiconductor memory (DRAM)
Has increased in integration rate four times in about three years, and in order to realize a large capacity DRAM, it is necessary to form a large capacity capacitor in a smaller memory cell. In order to satisfy this, a stack type three-dimensional capacitor has been developed. However, in the stack type, when the height of the electrode is increased to increase the surface area of the electrode, a large step is generated between the memory cell portion and the peripheral portion, which makes post-processes such as photolithography difficult.

As a countermeasure against this, a structure in which the electrode shape itself is devised to increase the surface area is considered. As an example, a cylinder type capacitor is shown in FIGS. This capacitor has a cylindrical lower electrode 31 connected to a lower wiring 1 made of a diffusion layer and a dielectric material 4 on the surface thereof.
And an upper electrode 32 that covers the entire surfaces thereof. In addition, HS with fine irregularities on the surface of this cylinder type electrode
A method of increasing the electrode surface area by depositing G (hemi-spherical-grain) silicon has also been developed (Monthly Semiconductor World 1993.7).

However, in a highly integrated DRAM of 1 G or more, the capacitor forming area becomes smaller, so that it is necessary to increase the electrode surface area by forming the electrodes themselves in a concavo-convex shape. For example, Japanese Patent Application Laid-Open No. 05-206400 discloses a method of forming a capacitor electrode in an uneven shape. According to this method, two kinds of films are alternately deposited, unevenness is formed on the film surface by utilizing the difference in etching rate of the films, and an electrode material is deposited on the unevenness to form a lower electrode. After that, a dielectric material and an electrode material are deposited and processed in this order to form a capacitor having irregularities. The manufacturing method is shown in FIGS. 8 (a) to 8 (c), 9 (d) to 9 (f) and FIG.
0 (a) (b).

FIG. 8A shows that two kinds of films (SiN film 5 and SiO ₂ film 6) are deposited in multiple layers on the upper surface of the lower wiring 1 connected to the capacitor on the SiO ₂ film 2. . Next, the two types of films 5 and 6 are anisotropically etched using the resist film 7 as a mask (FIG. 8B), and the films are made into an uneven shape by utilizing the difference in etching rate by isotropic etching (FIG. 8B). 8 (c)). After that, the electrode material (doped polysilicon film) 3 is deposited to form the lower electrode portion 31 of the capacitor having an uneven shape (FIG. 9).
(D)), it is processed to form two types of films 5 and 6 having uneven shapes
Are removed (FIG. 9E), the derivative material 4 is deposited (FIG. 9F), and doped polysilicon is sequentially deposited and processed as the upper electrode 32 to form a capacitor ( 10 (a) (b)).

However, in the method of forming the unevenness by utilizing the difference in the etching rates of the two kinds of films 5 and 6, as in the above-mentioned example, the selection ratio of the etching of the SiN film 5 and the SiO ₂ film 6 is increased. If a film having a large size is not used, it is not possible to form an uneven shape with good dimensional accuracy. Also S
When a film having a large etching selection ratio such as the iN film 5 and the SiO ₂ film 6 is used to form a multilayer structure, these multilayer films must be removed when the capacitor is formed, but the etching selection ratio is different. The film removal process becomes complicated.

Further, in another example of Japanese Patent Laid-Open No. 5-206400, a resist film is formed in a region where a capacitor electrode is formed, and the side surface of the resist film is made into an uneven shape by a standing wave. A method is disclosed in which an oxide film is selectively grown with respect to a pattern, the resist film pattern is removed to form an insulating film having unevenness on the side surface, and then the lower electrode is formed as described above. In this case, the size of the unevenness is determined by the wavelength and the light intensity. Generally, as the exposure light, light having a specific wavelength such as g-line or i-line is generally used. However, if the intensity of the light is changed, there is a possibility that a sufficient exposure amount cannot be given to the resist film. Not preferable.

For example, when the i-line (365 nm) or g-line (435 nm) of a mercury lamp of a stepper is used, the wavelength is determined, and thus the cycle of unevenness, that is, the width is determined, and the depth of unevenness is determined by the intensity of light. It is not possible to freely change the dimensions of the unevenness. FIG. 11 shows a standing wave 1 that is exposure light.
The relationship between 0 and the period f and the depth d of the unevenness is shown. Further, even if a wavelength other than i-line and g-line is used as the wavelength of the mercury lamp, the intensity is weak in reality and the resist film cannot be efficiently exposed.

[0009]

As the area of the memory cell is reduced with the high integration of DRAM, the capacitor must be three-dimensionalized in order to increase the electrode area.
As a result, a large step is generated between the memory cell portion and the peripheral portion, which makes post-processes such as photolithography difficult. For this reason, the electrode surface area has been increased and improved by devising the shape of the capacitor electrode. But,
With the conventional method, it is difficult to form the desired electrode shape,
It was difficult to increase the electrode surface area.

[0010]

Thus, a resist film having a desired film thickness is patterned on a semiconductor substrate, and an oxide film having the same film thickness as the resist film is selectively formed in a region other than the resist film. , A resist film different in size from the resist film is patterned again on the resist film, and an oxide film having the same thickness as the resist film is selectively deposited in a region other than the resist film. Repeat the process,
Next, the laminated resist film is peeled off to expose the semiconductor substrate, and the exposed surface of the semiconductor substrate, the inner wall having the unevenness of the oxide film laminated in the vertical direction of the semiconductor substrate and the upper surface of the oxide film laminated on the uppermost layer. A method for manufacturing a semiconductor device is provided, which comprises forming a lower electrode by depositing an electrode material on the substrate.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION A lower electrode is formed by the semiconductor manufacturing method of the present invention, and then a dielectric material and an upper electrode are deposited and processed in this order to form a large-capacity capacitor having a large electrode surface area. it can. The desired film thickness in the present invention is an important factor for obtaining the electrode surface area required for forming a capacitor of large capacity DRAM. This film thickness determines the width of the irregularities on the electrode surface, and specifically, it is preferably about 1000 to 2000Å. Further, the depth of the irregularities on the surface of the electrode is determined by the difference in the formation size of the resist film and the oxide film.
The degree is preferred.

The present invention will be described below with reference to the drawings. 2 (a)-(b), 3 (d)-(f) and FIG.
(G) (h) is process explanatory drawing which shows an example of the manufacturing method of the semiconductor device by this invention. In this example, a cylindrical electrode will be described. As the resist film 7, when a positive resist is used, a resist film 7 having a desired film thickness is patterned on the lower wiring 1 by photolithography or the like,
It can be formed by curing. As a curing method,
Known methods can be used, and examples include ultraviolet irradiation and high temperature baking. Further, when a negative resist is used, the curing treatment as described above is not particularly required. Next, the oxide film 8 is selectively deposited in a region other than the resist film to the same thickness as the resist film 7 (FIG. 2A). An LPD oxide film may be used as the oxide film. The LPD oxide film is particularly preferable. Further, before the resist film 7 having a different size from the resist film 7 is formed on the previously patterned resist film 7, an O ₂ plasma treatment 9 is performed on the entire surface of the resist film and the oxide film (FIG. 2).
(B)). This can facilitate the deposition of the oxide film 8 on the resist film 7. O ₂ plasma treatment is
₂ Flow rate: 500 sccm, pressure: 70 Pa, RP power: 700 W, irradiation time: several minutes is preferable.

Further, a resist film 7 having a desired film thickness is patterned again on the lower resist film by photolithography from above, and an oxide film 8 is formed in the other region on the resist film 7 with a different opening size. Is selectively deposited up to the same thickness as that of (FIG. 2 (c)). The width of the opening size of the resist film 7 is preferably in the range of 40 to 80% of the lowermost resist film 7 as a reference. FIG.
By repeating the processes up to (c), the resist film 7 and the oxide film 8 are sequentially laminated as shown in FIG. The treatment may be repeated once or more, and thus the number of layers may be two or more. In order to obtain the electrode surface area required for the formation of a large capacity DRAM capacitor,
The height of the electrode is preferably about 4000 to 6000Å,
Converting from the thickness of the resist film 7 described above, about 3 to 5 layers are preferable.

After that, the resist film 7 is removed by an O ₂ asher or the like (FIG. 3E), and doped polysilicon, which is the electrode material 3, is deposited to connect with the lower wiring 1 (FIG. 3E). (F)), the processing is performed to remove the oxide film 8 (FIG. 4G). Specifically, the deposition thickness of the electrode material 3 is preferably about 300 to 500 Å. Further, the dielectric material 4 is deposited (FIG. 4 (h)). Specifically, the thickness of the dielectric material 4 is preferably about 30 to 100Å. Further, doped polysilicon which becomes the upper electrode 32 is deposited and processed to form a capacitor structure having a cylindrical electrode shape and an uneven shape on the side surface (FIGS. 1A and 1B).

[0015]

Embodiments of the present invention will be described below with reference to the drawings. 2A to 2B, 3D to 3F, and 4G to 4H are process explanatory views showing an embodiment of the method for manufacturing a semiconductor device according to the present invention. In this example, a cylindrical electrode will be described.

As the resist film, a positive type resist is used,
A film thickness of 1000 is formed on the lower wiring 1 by photolithography.
The resist film 7 of Å was patterned, and the resist film was cured by performing ultraviolet irradiation and high temperature baking. Next, an oxide film 8 was selectively deposited in a region other than the resist film 7 up to the same thickness as the resist film 7 (FIG. 2A). As the oxide film, an aluminum plate serving as a reaction accelerator was added to a hydrosilicofluoric acid aqueous solution (H ₂ SiF ₆ ) at 35 ° C., and an LPD oxide film was formed at a depo rate of usually about 300 to 500 Å / h. Before the resist film 7 having a different size from the resist film 7 was formed on the resist film 7 again, O ₂ plasma treatment 9 was performed on the entire surfaces of the resist film 7 and the oxide film 8 (FIG. 2B). O ₂ plasma treatment is
O ₂ flow rate: 500 sccm, pressure: 70 Pa, RP power: 700 W, irradiation time: several minutes.

Further, from above again, a resist film 7 having a film thickness of 1000 Å is formed by patterning on the lower resist film by photolithography with different opening sizes, and an oxide film 8 is formed on the other region of the resist film 7. It was selectively deposited to the same thickness as the film thickness (FIG. 2 (c)). The width of the opening size of the resist film 7 was set to 60% based on the resist film 7 of the lowermost layer. By repeating the processes shown in FIGS. 2A to 2C, a resist film 7 and an oxide film 8 are sequentially stacked to form a height 5000 as shown in FIG. 3D.
The desired electrode shape of Å was formed.

After that, the resist film 7 is removed by O ₂ asher (FIG. 3E), and doped polysilicon, which is the electrode material 3, is deposited to connect the lower wiring 1 (FIG. 3 (E)). f)), the processing was performed, and the oxide film 8 was removed (FIG. 4G). Further, a dielectric material 4 having a film thickness of about 50 Å is deposited (FIG. 4 (h)), and doped polysilicon to be the upper electrode 32 is deposited and processed, whereby the electrode shape is a cylinder type and a concavo-convex shape is formed on the side surface. A capacitor structure having the same was formed (FIGS. 1A and 1B).

Although the above embodiment describes a cylindrical type, the formation pattern of the resist film can be any shape such as a rectangle or an ellipse. FIGS. 5A and 5B show examples of simple rectangular shapes. Further, calculation examples show that the electrode area increases in the semiconductor manufacturing method according to the present invention. In FIG. 5, the dimensions of each part are defined as follows. a: width of the capacitor b: thickness of the capacitor c: height of the side wall convex portion x: depth of the side wall concave portion y: height of the side wall concave portion

Using this figure, the surface area S when a rectangular stack capacitor was formed by the method for manufacturing a semiconductor device of the present invention was calculated. The surface area S was obtained from the following equation by dividing into surface areas as shown in FIG. Upper surface S ₁ = a ^2- (a-2b) ² Side surface (outer) S ₂ = ac × 4 × 2 = 8ac Side surface (outer) S ₃ = y × (a-2x) × 4 = 4y (a-2x) Side surface (outer) S ₄ = [a ^2- (a-2x) ² ] × 2 = 8ax-8x ² Side surface (inner) S ₅ = (cb) × (a-2b) × 4 × 2 = 8 ( c−b) × (a−2b) side face (inside) S ₆ = {(a−2b) ² − [a−2 (x + b)] ² } × 2 = 8ax−8x ² −16bx side face (inside) S ₇ = (Y + 2b) × [a-2 (x + b)] × 4 = 4ay-8xy-8by + 8ab-16bx-16b ² lower surface S ₈ = (a-2b) ² S = S ₁ + S ₂ + S ₃ + S ₄ + S ₅ + S ₆ + value of _{S 7 + S 8 = x (} -16x-16y + 16a-32b) + (a 2 + 16ac + 8ay-16bc-8by) where the surface area S is maximum x is represented by the following equation. 0 = −16x−16y + 16a−32b−16x 32x = 16a−16y−32b x = (a−y + 2b) / 2 where a = 1.0 μm, b = 0.1 μm, c = 0.3 μ
The relationship between the depth x of the sidewall recess and the surface area S when m and y = 0.15 μm is shown in Table 1 and FIG.

[0021]

[Table 1]

In this example, the surface area is increased by a maximum of 26.4% as compared with the case where the side wall has no unevenness.

[0023]

According to the method of manufacturing a semiconductor device of the present invention, a desired electrode shape can be formed without etching by patterning a resist film into an electrode shape of a capacitor and selectively growing an oxide film. . Specifically, this electrode shape can be designed freely in width and depth.
By using this electrode as a lower electrode, and then depositing and processing a dielectric material and an upper electrode in this order, a large-capacity capacitor having a large electrode surface area can be formed without increasing the memory cell occupied area of the DRAM. Moreover, since it is not necessary to increase the height of the capacitor portion, it is possible to reduce the difference from the peripheral step portion, and the post-process such as photolithography becomes easy.

Further, O ₂ is formed on the entire surface of the resist film and the oxide film.
By performing the plasma treatment 9, the oxide film 8 can be easily deposited on the resist film 7. Therefore, according to the present invention, a capacitor having a large electrode surface area can be formed, sufficient capacitance of the capacitor can be ensured even when the memory cell is downsized, and a highly reliable DRAM can be manufactured.

[Brief description of drawings]

FIG. 1 is a schematic sectional view and a schematic perspective view of a semiconductor device manufactured by a method of the present invention.

FIG. 2 is a schematic process sectional view of a method for manufacturing a semiconductor device of the present invention shown in an embodiment.

FIG. 3 is a schematic process sectional view of a method for manufacturing a semiconductor device of the present invention shown in an embodiment.

FIG. 4 is a schematic process sectional view of a method for manufacturing a semiconductor device of the present invention shown in an embodiment.

5A and 5B are a cross-sectional view and a perspective view modeled to calculate an electrode surface area of a semiconductor device of the present invention.

FIG. 6 is a graph showing the relationship between the sidewall recess depth calculated from FIG. 5 and the surface area.

FIG. 7 is a schematic cross-sectional view and a schematic perspective view of a conventional semiconductor device.

FIG. 8 is a schematic process sectional view of a conventional method for manufacturing a semiconductor device.

FIG. 9 is a schematic process cross-sectional view of a conventional semiconductor device manufacturing method.

10 is a schematic cross-sectional view and a schematic perspective view of a semiconductor device manufactured by the method of FIG.

FIG. 11 is a schematic diagram of a standing wave used in a conventional semiconductor device manufacturing method.

[Explanation of symbols]

1 Lower Wiring 2 SiO ₂ Film 3 Electrode Material (Doped Polysilicon Film) 31 Lower Electrode 32 Upper Electrode 4 Dielectric Material 5 SiN Film 6 SiO ₂ Film 7 Resist Film 8 Oxide Film 9 O ₂ Plasma Irradiation 10 Standing Wave

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] March 28, 1996

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Change

[Correction contents]

The present invention will be described below with reference to the drawings. 2 (a)-(b), 3 (d)-(f) and FIG.
(G) (h) is process explanatory drawing which shows an example of the manufacturing method of the semiconductor device by this invention. In this example, a cylindrical electrode will be described. As the resist film 7, when a positive resist is used, a resist film 7 having a desired film thickness is patterned on the lower wiring 1 by photolithography or the like,
It can be formed by curing. As a curing method,
Known methods can be used, and examples include ultraviolet irradiation and high temperature baking. Further, when a negative resist is used, the curing treatment as described above is not particularly required. Next, the oxide film 8 is selectively deposited in a region other than the resist film to the same thickness as the resist film 7 (FIG. 2A). An LPD oxide film may be used as the oxide film. The LPD oxide film is particularly preferable. Further, before the resist film 7 having a different size from the resist film 7 is formed on the previously patterned resist film 7, an O ₂ plasma treatment 9 is performed on the entire surface of the resist film and the oxide film (FIG. 2).
(B)). This can facilitate the deposition of the oxide film 8 on the resist film 7. O ₂ plasma treatment is
₂ Flow rate: 500 sccm, pressure: 70 Pa, RF power
- : It is preferable to carry out under the conditions of 700 W and irradiation time: several minutes.

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0016

[Correction method] Change

[Correction contents]

As the resist film, a positive type resist is used,
A film thickness of 1000 is formed on the lower wiring 1 by photolithography.
The resist film 7 of Å was patterned, and the resist film was cured by performing ultraviolet irradiation and high temperature baking. Next, an oxide film 8 was selectively deposited in a region other than the resist film 7 up to the same thickness as the resist film 7 (FIG. 2A). As the oxide film, an aluminum plate serving as a reaction accelerator was added to a hydrosilicofluoric acid aqueous solution (H ₂ SiF ₆ ) at 35 ° C., and an LPD oxide film was formed at a depo rate of usually about 300 to 500 Å / h. Before the resist film 7 having a different size from the resist film 7 was formed on the resist film 7 again, O ₂ plasma treatment 9 was performed on the entire surfaces of the resist film 7 and the oxide film 8 (FIG. 2B). O ₂ plasma treatment is
O ₂ flow rate: 500 sccm, pressure: 70 Pa, RF power
- : 700 W, irradiation time: several minutes.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0020

[Correction method] Change

[Correction contents]

Using this figure, the surface area S when a rectangular stack capacitor was formed by the method for manufacturing a semiconductor device of the present invention was calculated. The surface area S was obtained from the following equation by dividing into surface areas as shown in FIG. Upper surface S ₁ = a ^2- (a-2b) ² Side surface (outer) S ₂ = ac × 4 × 2 = 8ac Side surface (outer) S ₃ = y × (a-2x) × 4 = 4y (a-2x) Side surface (outer) S ₄ = [a ^2- (a-2x) ² ] × 2 = 8ax-8x ² Side surface (inner) S ₅ = (cb) × (a-2b) × 4 × 2 = 8 ( c−b) × (a−2b) side face (inside) S ₆ = {(a−2b) ² − [a−2 (x + b)] ² } × 2 = 8ax−8x ² −16bx side face (inside) S ₇ = (Y + 2b) × [a-2 (x + b)] × 4 = 4ay-8xy-8by + 8ab-16bx-16b ² lower surface S ₈ = (a-2b) ² S = S ₁ + S ₂ + S ₃ + S ₄ + S ₅ + S ₆ + value of _{S 7 + S 8 = x (} -16x-16y + 16a-32b) + (a 2 + 16ac + 8ay-16bc-8by) where the surface area S is maximum x is represented by the following equation. 0 = −16x−16y + 16a−32b−16x 32x = 16a−16y−32b x = (a−y−2b) / 2 where a = 1.0 μm, b = 0.1 μm, c = 0.3 μ
The relationship between the depth x of the sidewall recess and the surface area S when m and y = 0.15 μm is shown in Table 1 and FIG.

Claims (2)

[Claims] 1. A resist film having a desired film thickness is patterned on a semiconductor substrate, and an oxide film having the same thickness as the resist film is selectively deposited in a region other than the resist film, and the resist film is again formed. The step of pattern-forming a resist film having a size different from that of the resist film on the resist film, and selectively depositing an oxide film having the same thickness as the resist film in a region other than the resist film is repeated, and then stacked. The exposed resist film is peeled off to expose the semiconductor substrate, and an electrode is provided on the exposed surface of the semiconductor substrate, the inner wall having irregularities of the oxide film stacked in the vertical direction of the semiconductor substrate and the upper surface of the oxide film stacked on the uppermost layer. A method of manufacturing a semiconductor device, comprising forming a lower electrode by depositing a material. 2. The manufacturing of a semiconductor device according to claim 1, wherein O ₂ plasma treatment is repeatedly performed on the entire surface of the resist film and the oxide film before the resist film having a different size from the resist film is formed on the resist film again. Method.