JPH09260395A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the patterning process of a polycrystalline silicon film, by selectively growing a polycrystalline silicon film to which impurities of a conductivity type are added, from the side wall surface composed of a silicon nitride film. SOLUTION: A silicon nitride film of abort 100nm in thickness is formed on the whole surface of a substrate containing the side surface of an aperture on the surface of a layer insulating film 16. A side wall 21 of the silicon nitride film is formed on the aperture side surface by etching back the silicon nitride film. A thin insulating film 22 is formed on the surface of a single crystal line silicon film 12. Polycrystalline silicon 31 is selectively frown in the surface of a side wall 21 of the silicon nitride film, and the surface of the thin insulating film 22 is covered with a polycrytstalline silicon film 31. N-type impurities introduced in the polycrytstalline silicon film 31 is subjected to solid phase diffusion ion the single crystalline silicon film of a substrate, and an emitter region 32 is formed, Therefore, the manufacturing process relative to the patterning of the polycrytstalline silicon film can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a transistor in which an impurity region is formed by diffusing impurities from a polycrystalline silicon film.

[0002]

2. Description of the Related Art A conventional method of manufacturing a vertical bipolar transistor (hereinafter simply referred to as a transistor) will be described below with reference to the drawings. First, FIG.
As shown in (a), on the surface of the N-type semiconductor substrate 111,
Single crystal silicon film 1 that will be the collector region of the transistor
12 is formed. Next, LOCOS (Local Oxidation of Silicon) is formed in the element isolation region of the single crystal silicon film 112.
The element isolation layer 113 is formed by an on) method or an STI (Shallow Trench Isolation) method. Next, a resist pattern (not shown) having an opening is formed on the element region between the element isolation regions, and using this as a mask, P is formed on the single crystal silicon film 112.
The base region 114 is formed by introducing a type impurity. Next, on the surface of the single crystal silicon film 112, a polycrystalline silicon film 115 with a high concentration of impurities, which becomes an extraction electrode of the base region, is formed, and this is patterned into a predetermined shape. Next, on the surface of the patterned polycrystalline silicon film 115 and on the surface of the single crystal silicon film 112,
The interlayer insulating film 116 is formed.

Subsequently, as shown in FIG. 2B, a resist pattern (not shown) having an opening in the element forming region is formed on the surface of the interlayer insulating film 116, and the resist pattern is used as a mask to form the interlayer insulating film 116. The crystalline silicon film 115 is etched to expose the single crystalline silicon film 112 in the element formation region. A silicon nitride film or a silicon oxide film is formed on the entire surface of the substrate including the side surface of the opening, and this is etched back to form the sidewall 121 on the side surface of the opening. Next, R is formed on the exposed surface of the single crystal silicon film 112.
Film thickness of 1 nm by TA (Rapid Thermal Anneal) method
A thin insulating film 122 of a silicon oxide film, a silicon nitride film, or the like is formed.

Subsequently, as shown in FIG. 2C, the insulating film 1
A polycrystalline silicon film 131 is formed on the substrate on which 22 is formed, and an N-type impurity such as P is introduced into this polycrystalline silicon film 131 by an ion implantation method or the like. Next, high temperature heat treatment is performed to solid-phase diffuse the N-type impurities introduced into the polycrystalline silicon film 131 into the single crystal silicon film 112 of the substrate to form the emitter region 132. The polycrystalline silicon film 131 may be formed by introducing N-type impurities at the time of formation. Further, as shown in the above steps, the base region 114 is already formed before the formation of the emitter region 132 without depending on the solid phase diffusion from the polycrystalline silicon film 131, but the formation process of the emitter region 132 is performed. alike,
P-type impurities are introduced into the polycrystalline silicon film 131, and high-temperature heat treatment is performed to remove the P-type impurities from the single crystal silicon film 112 of the substrate.
It can also be formed by a method of solid phase diffusion.

Subsequently, as shown in FIG. 2D, a resist pattern (not shown) is formed on the polycrystalline silicon film 131, and the polycrystalline silicon film 131 is patterned using this as a mask to form the polycrystalline silicon film 131. Leave only on the element formation region. The patterning of the polycrystalline silicon film 131 is to secure a position for forming a contact hole for connecting a wiring to the base region 114 and the collector region 112. Next, an interlayer insulating film 141 is formed on the entire surface of the substrate, and on this interlayer insulating film 141, a polycrystalline silicon film 115 to be a lead electrode in the base region, a polycrystalline silicon film 131 to be a lead electrode in the emitter region, and a single film to be a collector region are formed. Contact holes reaching the crystalline silicon substrate 112 are formed. Next, a conductive film is embedded in each contact hole and patterned to form wirings 142 to 144 connected to each impurity region. Through the above steps, the general transistor manufacturing process according to the conventional technique is completed.

In the above description, the manufacturing method of the vertical NPN transistor has been described, but the vertical PNP transistor can be manufactured by almost the same manufacturing process by only changing the conductivity type of the impurities introduced into the substrate. It can be manufactured.

[0007]

The conventional transistor manufacturing method as described above has the following problems. That is, in order to form an emitter region or a base region, a polycrystalline silicon film which is a solid phase diffusion source of the impurity is formed on the element formation region, and then this polycrystalline silicon film is left only on the emitter region. for,
A step of patterning this polycrystalline silicon film is required.

In the step of patterning a predetermined film such as a polycrystalline silicon film formed on a semiconductor substrate, a photoresist is first coated on the substrate, baked, and then exposed, developed, and developed. The predetermined film must be etched using the resist pattern as a mask, and after the etching is completed, the resist pattern used as the mask must be removed by ashing or the like.

That is, the patterning process of the predetermined film is a factor that significantly increases the number of processes in the manufacturing process of the semiconductor substrate. Since the increase in the number of steps has adverse effects on the manufacturing of semiconductor devices such as a decrease in yield, an increase in manufacturing cost, and an increase in manufacturing period, it is desirable to reduce the number of steps, especially the patterning step of a predetermined film as much as possible. Be done.

Further, in the patterning process of the predetermined film, it is necessary to have an alignment margin in the exposure and development for forming the resist pattern. If this alignment margin is taken into consideration,
In some cases, it is necessary to design larger than the minimum element size required to obtain desired element characteristics. Therefore, the patterning process of the predetermined film may hinder the miniaturization of the semiconductor element.

As described above, in the manufacturing process of the semiconductor device, it is advantageous to reduce the patterning process of the predetermined film as much as possible in order to reduce the manufacturing cost and miniaturize the element.
The patterning of the polycrystalline silicon film according to the conventional technique, which is the premise of the present invention, is no exception, and it is desirable to omit the patterning step of the polycrystalline silicon film if possible.

[0012]

The present invention uses the following means in order to solve the above problems. That is, as in the invention according to claim 1, a step of preparing a first-conductivity-type semiconductor substrate to be a collector region, and a step of introducing a second-conductivity-type impurity to a predetermined depth from the surface of the semiconductor substrate, Forming a base region having a second region,
Forming a sidewall of a silicon nitride film on the first region of the base region; forming an insulating film on the second region of the base region; and adding an impurity of one conductivity type from the surface of the sidewall. Selectively growing the formed polycrystalline silicon film to cover the surface of the insulating film, and diffusing the first conductivity type impurity from the polycrystalline silicon film below the second region of the base region to form an emitter region. And a step of forming the semiconductor device.

In addition to the above, a step of preparing a first-conductivity-type semiconductor substrate to be a collector region as in the second aspect of the invention, and introducing a second-conductivity-type impurity to a predetermined depth from the surface of the semiconductor substrate. Forming a base region having first and second regions on the surface, forming a first silicon nitride film on the first region of the base region, and forming a second silicon on the second region of the base region. A step of forming a nitride film, a step of selectively growing a polycrystalline silicon film doped with an impurity of one conductivity type from the surface of the first and second silicon nitride films, and a step of forming a second region below the base region. And diffusing the first conductivity type impurity from the polycrystalline silicon film through the second silicon nitride film to form an emitter region.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to FIG. First, as shown in FIG. 1A, a single crystal silicon film 12 to be a collector region of a transistor is formed on the surface of an N-type semiconductor substrate 11. Next, the LOC is formed in the element isolation region of the single crystal silicon film 12.
OS (Local Oxidation of Silicon) method and STI (Shal
The element isolation layer 13 is formed by the low trench isolation method. Next, a resist pattern (not shown) having an opening is formed on the element region, and a P-type impurity such as B is introduced into the single crystal silicon film 12 using this as a mask.
The base region 14 is formed. Next, the single crystal silicon film 12
On the surface, a polycrystalline silicon film 15 having a film thickness of 100 nm to 300 nm doped with a high concentration of impurities is used as a lead electrode of the base region by CVD (Chemical Vapor Deposi).
formation) method. Next, this single crystal silicon film 1
An interlayer insulating film 16 having a film thickness of 100 nm to 300 nm is formed on the surface 2 by the CVD method.

Subsequently, as shown in FIG. 1B, a resist pattern (not shown) having an opening is formed on the element formation region on the surface of the interlayer insulating film 16, and using this as a mask, the interlayer insulating film 16 and the polycrystalline film are formed. The silicon film 15 is etched to expose the single crystal silicon film 12 in the element formation region. The width of exposing the single crystal silicon film 12 varies depending on the type of device to be manufactured, but is 0.5 μm to 1.0 μm.
Degree. Next, a film thickness of 10 is formed on the entire surface of the substrate including the side surface of the opening.
A silicon nitride film having a thickness of about 0 nm is formed, and this is etched back to form a sidewall 21 of the silicon nitride film on the side surface of the opening. Next, a thin insulating film 22 made of a silicon oxide film or a silicon nitride film having a film thickness of about 1 nm is formed on the exposed surface of the single crystal silicon film 12 by the RTA method or the like. The thin insulating film 22 is preferably formed of a silicon nitride film when the exposed area of the single crystal silicon film 12 is relatively large. The reason for this will be described later. Except that it is essential to form the sidewall 21 with a silicon nitride film until this step,
There is no difference from the conventional manufacturing method.

Subsequently, as shown in FIG. 1C, a polycrystalline silicon film 31 is selectively grown on the surface of the sidewall 21 made of a silicon nitride film, and the polycrystalline silicon film 31 causes the surface of the thin insulating film 22 to grow. cover.

This polycrystalline silicon film 31 is formed by selective growth in a reaction chamber kept at 700 ° C. or higher.
This is performed by placing a substrate on which the above manufacturing steps have been completed and introducing a silicon chloride-based gas such as SiH ₂ Cl ₂ as a Si source gas. As an example thereof, SiH ₂ Cl ₂ which is a silicon chloride gas is introduced into the reaction chamber kept at 800 ° C. or higher at about 0.4 L / min to maintain sufficient selectivity for the silicon oxide film. It has been confirmed by the present inventors that the polycrystalline silicon film 31 can be selectively grown only on the sidewalls 21 formed of the silicon nitride film as it is.

As the gas to be introduced into the reaction chamber, in addition to those mentioned above, a silicon chloride-based gas such as SiH is used.
₄ or Si ₂ H ₆ is a halogen-based gas such as HCl or Cl ₂
It can also be carried out by using a mixed gas of the above and a mixed gas of a silane-based gas and a halogen-based gas.

When, for example, PH ₃ is mixed in the above-mentioned gases, P is introduced into the polycrystalline silicon film to be formed, and when AsH ₃ is mixed, As and B ₂ are mixed. When H ₆ is mixed, B is added, so that the polycrystalline silicon film to be formed can be made conductive and can be used as a solid phase diffusion source for forming an impurity region. . By using the above manufacturing method, the polycrystalline silicon film 31 can be selectively formed only on the surface of the sidewall formed of the silicon nitride film.

As described above, in the present invention, the insulating film 22 is formed on the surface of the single crystal silicon film 12. However, when the exposed area of the single crystal silicon film is relatively large, this exposed surface is not formed. It is preferable that the insulating film 22 formed in the above is formed of a silicon nitride film. That is, in the selective growth of the polycrystalline silicon film, not only is the insulating film 22 covered with the polycrystalline silicon film 31 growing only from the side surface of the sidewall 21 but also the surface of the insulating film 22 formed of the silicon nitride film. Since the polycrystalline silicon film 31 can be grown, the surface of the insulating film 22 can be sufficiently covered with the silicon oxide film 31.

Next, in the selective growth of the polycrystalline silicon film 31, if an impurity is not added at the same time as the selective growth of the polycrystalline silicon film 31, an N type impurity such as P is added to the polycrystalline silicon film 31 by an ion implantation method or the like. Introduce. Next, high temperature heat treatment is performed to remove the N-type impurities introduced into the polycrystalline silicon film 31.
Solid-phase diffusion is performed in the single crystal silicon film 12 of the substrate to form the emitter region 32. In the present invention, the base region 14 is already formed before the formation of the emitter region 32 without depending on the solid phase diffusion from the polycrystalline silicon film 31, but like the step of forming the emitter region 32, first the polycrystalline region is formed. Silicon film 3
1 is formed, or after the P-type impurities are introduced, high-temperature heat treatment is performed to remove the P-type impurities from the single crystal silicon film 12 of the substrate.
It can also be formed by a method of solid phase diffusion.

Subsequently, as shown in FIG. 1D, an interlayer insulating film 41 is formed on the entire surface of the substrate. In the conventional manufacturing process, it was necessary to pattern the polycrystalline silicon film formed on the interlayer insulating film, but according to the present invention, this polycrystalline silicon film is selectively formed only on the sidewall surface. Therefore, it is not necessary to newly process or pattern this. Therefore, the photoresist forming process, the exposure process, the developing process, the etching process, and the like related to the patterning are unnecessary, and the number of processes can be reduced.

Next, contacts reaching the interlayer insulating film 41 to the polycrystalline silicon film 15 serving as the extraction electrode in the base region, the polycrystalline silicon film 31 serving as the extraction electrode in the emitter region, and the single crystal silicon substrate 12 serving as the collector region, respectively. Form a hole. Next, a conductive film is embedded in the contact hole and patterned to form wirings 42 to 44 connected to the respective impurity regions. Through the above steps, the manufacturing process of the transistor according to the embodiment of the present invention is completed. In the above explanation,
Although the manufacturing method of the vertical NPN transistor has been shown,
The vertical PNP transistor can also be manufactured by almost the same manufacturing process only by changing the conductivity type of impurities introduced into the substrate.

Next, the effect of the present invention will be described. According to the present invention, a polycrystalline silicon film serving as a solid phase diffusion source for forming an emitter region can be selectively formed only on the surface of a sidewall formed of a silicon nitride film. Therefore, since it is not necessary to newly process or pattern this polycrystalline silicon film, a photoresist forming step, an exposure step, a developing step, an etching step, etc. relating to this patterning become unnecessary, and the number of steps can be reduced. You can

Further, since the patterning step is unnecessary, the alignment margin in the exposure and development for forming the resist pattern, which was conventionally required for patterning the polycrystalline silicon film, is not required, and the semiconductor element can be miniaturized. Becomes

[0026]

According to the present invention, it is possible to selectively form a polycrystalline silicon film which serves as a solid-phase diffusion source for forming an emitter region, so that this is newly processed or patterned. There is no need to carry out a process. That is, compared with the conventional manufacturing method, it is possible to reduce the number of manufacturing steps for patterning the polycrystalline silicon film. Further, since this patterning step is not necessary, it is not necessary to consider the alignment margin in the exposure and development steps for forming the resist pattern, so that the semiconductor element can be miniaturized as compared with the conventional one.

[Brief description of drawings]

FIG. 1 is a process cross-sectional view illustrating an embodiment of the present invention.

FIG. 2 is a process sectional view illustrating a manufacturing method according to a conventional technique.

[Explanation of symbols]

 11, 111 semiconductor substrate 12, 112 single crystal silicon film (collector region) 13, 113 element isolation layer 14, 114 base region 15, 31, 115, 131 polycrystalline silicon film 16, 41, 116, 141 interlayer insulating film 21, 121 Side Wall 22, 122 Insulating Film 32, 132 Emitter Region 42, 43, 44, 142, 143, 144 Wiring

Claims (5)

[Claims] 1. A step of preparing a first conductivity type semiconductor substrate to be a collector region, and a base having first and second regions on the surface by introducing a second conductivity type impurity to a predetermined depth from the surface of the semiconductor substrate. Forming a region, forming a sidewall made of a silicon nitride film on the first region of the base region, forming an insulating film on the second region of the base region, on the sidewall surface A step of selectively growing a polycrystalline silicon film doped with an impurity of one conductivity type and covering the surface of the insulating film; and the first conductivity type of the polycrystalline silicon film below the second region of the base region. And diffusing impurities to form an emitter region. 2. A step of preparing a first conductivity type semiconductor substrate to be a collector region, and a base having first and second regions on the surface by introducing a second conductivity type impurity to a predetermined depth from the surface of the semiconductor substrate. A step of forming a region, a step of forming a first silicon nitride film on the first region of the base region, a step of forming a second silicon nitride film on a second region of the base region, the first, A step of selectively growing a polycrystalline silicon film doped with one conductivity type impurity on the surface of the second silicon nitride film; and the polycrystalline silicon film under the second region of the base region via the second silicon nitride film. A step of diffusing the first conductivity type impurity from a silicon film to form an emitter region. 3. A step of forming an interlayer insulating film on the surface of the polycrystalline silicon film after the step of forming the emitter region, and a step of forming a contact hole reaching the polycrystalline silicon film in the interlayer insulating film. And a step of burying a conductive film in the contact hole and electrically connecting to the polycrystalline silicon film.
The manufacturing method of the semiconductor device described in the above. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the first impurity is added to the polycrystalline silicon film in the step of forming the polycrystalline silicon film. 5. The polycrystalline silicon film comprises a silicon chloride-based gas, a mixed gas of a silicon chloride-based gas and a halogen gas, or a silane-based gas and a halogen gas in a reaction chamber kept at 700 ° C. or higher. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the mixed gas is formed by inflowing the mixed gas.