JPH09252477A - Image coder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control a code amount without incurring image quality deterioration by distributing properly a code amount to each sub block even when a code amount of one block exceeds a prescribed amount. SOLUTION: In the case of measuring a code amount by one block, the code amount in a time series different from a conventional device is not measured, but quantization data by one block are stored by using a storage circuit 10 equivalent to one block, data by one block stored in the storage circuit 10 are scanned in parallel between sub blocks from data with lower frequencies to measure the code amount and when the integrated result exceeds the threshold level, succeeding data with higher frequencies are replaced with zero data or the like for each sub block to control a code amount. Thus, the code amount distribution to each sub block is uniformized and high image quality deterioration is not caused.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface image encoding device for encoding and recording or transmitting it by utilizing redundancy of an image signal.

[0002]

2. Description of the Related Art In a conventional image coding apparatus, an input image signal is orthogonally transformed, the data thereof is rearranged in frequency order and quantized, and the quantized signal is variable length coded to compress the data and finally In addition, the data compression-encoded signal of the input image signal is used in a recording device, a transmission device, or the like.

After the quantization is performed, the variable length coding is performed. At this time, the code amount of the quantized data of each macroblock is measured, and the code amount exceeds a certain value. In this case, a process of replacing each of the excess data with zero data is performed. This is because, for example, if the code amount of the macroblock is larger than the data amount of the original image, sufficient data compression will not be performed even if variable length coding is performed.

FIG. 4 shows the configuration of a conventional image coding apparatus. In this image encoding device, the input image signal 21
Is separated into a luminance signal Y and a color difference signal C by a Y / C separation circuit block 22. The screen division circuit block 23 divides one frame into blocks of an appropriate size, and the sub block division circuit block 24 further divides one block into sub blocks. FIG. 5 shows an example of one block, and shows a case where the ratio of the luminance signal and the color difference signal is 4: 1: 1 (corresponding to an image in the 4: 2: 0 format).

One block at this time is called a macro block, and this macro block includes four luminance sub blocks Y0, Y1, Y2, Y3 and two color difference sub blocks C.
It is composed of r and Cb.

In the orthogonal transformation circuit block 25, the order of luminance sub-block / color difference sub-block is Y0 → Y1 → Y2 → Y3 →
The orthogonal transformation is performed from Cr to Cb, and each sub-block is separated for each frequency component. In the frequency-order rearrangement circuit block 26, the data in each sub-block is zigzag-scanned and rearranged in order of frequency in the order of sub-blocks subjected to orthogonal transformation. FIG. 6 shows an example of the scanning order in the sub-block after the orthogonal transformation, and shows the case where the size of the sub-block is 8 × 8 in sample point units.

At this time, the data string of Y0 is converted into y ₀ i (i =
1, 2, ..., 64), and the data sequence of Y1 is y ₁ i (i
1, 2, ..., 64), and the data sequence of Y2 is y ₂ i (i =
1, 2, ..., 64), and the data sequence of Y3 is y ₃ i (i =
1, 2, ..., 64), Cr data strings are converted into _cr i (i =
1, 2, ..., 64), and the data string of Cb is c _b i (i =
1, 2, ..., 64), the output data sequence of the frequency order rearrangement circuit block 26 is y ₀ i (i = 1, 2,
, 64), y ₁ i (i = 1, 2, ..., 64), y ₂ i
(I = 1, 2, ..., 64), y ₃ i (i = 1, 2, ..., 64)
64), _cr i (i = 1, 2, ..., 64), c _b i (i
= 1, 2, ..., 64).

This data string is stored in the quantization circuit block 27.
After being quantized by, the encoding circuit block 28 performs encoding processing such as run-length encoding as pre-processing for variable-length encoding.

The encoded data is sent to the code length measuring circuit block 32 via the delay circuit 29, and the code length of each data is measured. This value and the value of the register 34 are added by the adder 33, and the result is stored in the register 34. As a result, the code lengths of encoded data are cumulatively added. The comparator 35 compares the value of the register 34 with the threshold value for each data, and the delay circuit 29
Thus, the data to the switch 30 is delayed by one data. When the value of the register 34 exceeds the threshold value, the switch 30 is connected to the zero signal generating circuit 31 side by the switch control signal 36, and the data thereafter is set to 0 until the end of the block. Otherwise, switch 3
0 is connected to the re-encoding circuit block 37 side.

FIG. 7 shows the data flow from the output of the delay circuit 29 to the input of the re-encoding circuit block 37. Here, over the code length accumulated result of the threshold when you enter y ₃ 2 data, the subsequent data strings are examples to be replaced with all zeros are shown.

Thereafter, the re-encoding circuit block 37 performs variable-length encoding as necessary, and then the output buffer 3
8 Then, finally, the signal 39 obtained by compression-encoding the input image is sent to a recording device, a transmission device, or the like. As the above-mentioned threshold value for one block, a value that does not cause any trouble during reproduction and does not cause deterioration of image quality is selected.

[0012]

However, as described above, in the conventional art, orthogonal transform is performed to sub-block order Y0 → Y1 → Y2 → Y3 → Cr → Cb, and the data in each sub-block is arranged in frequency order. By scanning, the code length of each data is cumulatively added as it is, and the data after the time when the result exceeds the threshold value is forcibly set to 0. Therefore, the distribution of the code amount to the sub-blocks becomes non-uniform, and the large image quality There is a risk of deterioration.

That is, in the example of FIG. 7, the second and subsequent data of the luminance sub-block Y3 and the color difference sub-block C are displayed.
All the data of r and Cb are lost, and a completely colorless block is generated.

It is also conceivable to adopt a method of controlling the code amount so that the code amount of one block does not exceed a certain fixed value again when the code amount of one block becomes large by changing the quantization control signal. However, this method is not suitable for real-time transmission, and also has a drawback that the circuit scale is significantly increased.

The present invention has been made in view of the above circumstances, and enables the code amount to be appropriately distributed to each sub-block even when the code amount of one block exceeds a certain amount, resulting in deterioration of image quality. It is an object of the present invention to provide an image encoding device capable of controlling the code amount without the need.

[0016]

According to the present invention, in an image coding apparatus for coding an image signal, an input image signal is separated into a luminance signal and a color difference signal, and an image provided by the input image signal is Means for dividing into a plurality of blocks each including a luminance sub-block and a chrominance sub-block, an orthogonal transformation means for orthogonally transforming the luminance signal and the chrominance signals contained in the block in units of the sub-blocks, and the orthogonal transformation means Rearranging means for rearranging the signals orthogonally transformed by the transforming means in frequency order for each sub-block,
Quantization means for quantizing the signals rearranged in the frequency order by the rearrangement means, storage means for storing one block of quantized data output from the quantization means, and storage means for the storage means. Quantized data for one block is scanned in parallel between the sub-blocks, and the code length of each data is cumulatively added to measure the code amount, and the code amount measuring unit measures the code amount. And a code amount control means for controlling the code amount for each block based on the code amount.

In this image coding apparatus, when the code amount of one block is measured, the code amount is not measured in time series as in the conventional case, but one block is stored by using the storage means corresponding to one block. Quantized data is stored, the stored data for one block is scanned in order of frequency, for example, data from the lowest frequency in order between sub-blocks, the code amount is measured, and if the cumulative addition result exceeds a certain threshold, For example, the data of high frequency after that is replaced with zero data and the code amount is controlled. As a result, the distribution of the code amount to each sub-block is made uniform, and a large deterioration in image quality does not occur. In addition, the circuit scale does not need to be significantly increased. Further, with this configuration, if the parallel scanning order among the sub-blocks is defined so that the scanning rate differs among the sub-blocks, it is possible to perform the code amount distribution according to the property of the sub-blocks forming one block. Becomes

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of an image coding apparatus according to an embodiment of the present invention. This image encoding device is for encoding and recording or transmitting it by utilizing the redundancy of the input image. In this image encoding device, the input image signal 1 is a Y / C separation circuit block. At 2, the luminance signal Y and the color difference signal C are separated. The screen division circuit block 3 divides one frame into blocks of appropriate size called macroblocks, and the subblock division circuit block 4 further divides one block into subblocks. As described with reference to FIG. 5, one block has four luminance sub-blocks Y0 when the ratio of the luminance signal to the color difference signal is 4: 1: 1 (corresponding to an image in the 4: 2: 0 format). It is composed of Y1, Y2, Y3 and two color difference sub-blocks Cr, Cb.

In the orthogonal transformation circuit block 5, the order of luminance sub-block / color difference sub-block Y0 → Y1 → Y2 → Y3 → C
An orthogonal transformation is performed on r → Cb, and each sub-block is separated for each frequency component. The orthogonal transformation method is DC
T (Dscreene Cine Transform)
m, discrete cosine transform).

In the frequency order rearranging circuit block 6, the data in each sub block are zigzag scanned in the order of the low frequencies in the order of the sub blocks subjected to the orthogonal transformation and rearranged. The scanning order within the sub-block after orthogonal transformation is
When the size of the sub-block is 8 × 8 in sample point units, the result is as shown in FIG.

At this time, the data string of Y0 is converted into y ₀ i (i =
1, 2, ..., 64), and the data sequence of Y1 is y ₁ i (i
1, 2, ..., 64), and the data sequence of Y2 is y ₂ i (i =
1, 2, ..., 64), and the data sequence of Y3 is y ₃ i (i =
1, 2, ..., 64), Cr data strings are converted into _cr i (i =
1, 2, ..., 64), and the data string of Cb is c _bi (i =
1, 2, ..., 64), the output data sequence of the frequency order rearrangement circuit block 6 is y ₀ i (i = 1, 2, ..., 64).
64), y ₁ i (i = 1, 2, ..., 64), y ₂ i (i
= 1, 2, ..., 64), y ₃ i (i = 1, 2, ..., 6)
4), _cr i (i = 1, 2, ..., 64), c _b i (i =
1, 2, ..., 64).

This data string is quantized by the quantizing circuit block 7, and is then subjected to coding processing such as run-length coding by the coding circuit block 28. The encoded data is input to the data storage circuit 10 via the data absorption delay circuit 9, and the data for one block is stored therein. The data of one block stored in the storage circuit 10 is scanned in parallel between the sub-blocks for each data, and {y ₀ i, y ₁ i, y ₂ i, y ₃ i, _cr i, c _It is sent to the code length measuring circuit block 13 in the order of _b i} (i = 1, 2, ..., 64). In the code length measuring circuit block 13, the code length of each data is measured, and this value and the cumulative value held in the register 15 are added by the adder 14, and the result is stored in the register 15
Is stored again in. As a result, the code lengths of encoded data are cumulatively added. In the comparator 16, the value of the register 15 is compared with the threshold value for each data, and the switch 11 is set to the storage circuit 10 side until the value of the register 15 exceeds the threshold value or the code length measurement of one block is completed. Is also not connected to the zero signal generation circuit 12 side. During this time, the data of the next block is output from the encoding circuit 8, and this data output is absorbed by the delay circuit 9.

When the value of the register 15 exceeds the threshold value or when the code length measurement of one block is completed, the data is sequentially read from the memory circuit 10 in the order of input to the memory circuit 10 and is again read through the switch 11. It is transferred to the encoding circuit block 18. In this case, since the code length measurement of one block is completed, the re-encoding circuit block 18
When the data transfer to (1) is started, all the data for one block is transferred to the re-encoding circuit block 18 through the switch 11 in the order input to the memory circuit 10. On the other hand, when the data transfer is started by the value of the register 15 exceeding the threshold value, the data having a higher frequency than the last data added at that time is replaced with the zero signal for any sub-block. As described above, the switch 11 is alternately switched between the storage circuit 10 side and the zero signal generation circuit 12 side. As a result, the zero signal and the data string continuously read from the storage circuit 10 are switched for each sub-block.

That is, when the last data whose code length is measured when the value of the register 15 exceeds the threshold value is c _b N, the data from N + 1th to 64th data in each sub-block is zero. , Y ₀ 1, y ₀ 2, ... y ₀ N, 0, ... y ₁ 1, y ₁ 2, ... y ₁ N, 0, ... y ₂ 1, y ₂ 2, ... y ₂ N, 0 , ... y ₃ 1, y ₃ 2, ... y ₃ N, 0, ... _cr 1, _cr 2, ... _cr N, 0, ... c _b 1, c _b 2, ... c _b N, 0, ... The data is transferred to the re-encoding circuit block 18 in this order. As a result, it is possible to make the code amount distribution to each sub-block uniform.

Thereafter, the re-encoding circuit block 18 performs variable-length encoding processing if necessary, and then sends it to the output buffer 19. Then, finally, the signal 39 obtained by compression-encoding the input image is sent to a recording device, a transmission device, or the like.

Further, in FIG. 1, y ₀ i (i = 1, 1
2, ..., 64), y ₁ i (i = 1, 2, ..., 64), y
₂ i (i = 1, 2, ..., 64), y ₃ i (i = 1, 2,
, 64), _cr i (i = 1, 2, ..., 64), c _b i
When the orthogonally transformed quantized data input to the memory circuit 10 in the order of (i = 1, 2, ..., 64) is scanned between sub-blocks to measure the code length for each data, the scanning ratio is If the parallel scanning order among the sub-blocks is defined so as to be different among the sub-blocks, it is possible to perform the code amount distribution according to the property of the sub-blocks forming one block.

For example, {y ₀ i, y ₁ i, y ₂ i, y ₃ i, y ₀ i + 1, y ₁
i + 1, y ₂ i + 1, y ₃ i + 1, _cr (i + 1) /
2, c _b (i + 1) / 2} (i = 1,3,5,7, ..., 63) (cr i, cb i) (i = 33,34, ..., 64) The signal can be prioritized over the color difference signal.

FIG. 2 shows a specific configuration for realizing the code amount control of FIG. Here, the luminance signal and the color difference signal are Y0 → Y1 → Y2 → Y3 for each sub-block.
The encoded data that has been orthogonally transformed in the order of → Cr → Cb is y
₀ i (i = 1, 2, ..., 64), y ₁ i (i = 1, 2,
, 64), y ₂ i (i = 1, 2, ..., 64), y ₃ i
(I = 1, 2, ..., 64), _cr i (i = 1, 2, ..., 64)
64), cb i (i = 1, 2, ..., 64) in this order, and written via the delay circuit 9 into the memory constituting the above-mentioned memory circuit 10 in block units. The data written in this memory is as follows: {y ₀ i, y ₁ i, y ₂ i, y ₃ i, _cr i, c _b i} (i = 1, 2, , 64), the memory is randomly accessed by the memory address generated by the address generating circuit 54. As a result, the code length of the read data is measured by the code length measuring circuit block 13 for each data. Then, the measured value and the cumulative value held in the register 15 are added by the adder 14, and the result is stored again in the register 15.
In this way, the code lengths of encoded data are cumulatively added. In the comparator 16, the value of the register 15 is compared with the threshold value for each data, and the switch 11 is set to the storage circuit 10 side until the value of the register 15 exceeds the threshold value or the code length measurement of one block is completed. Is also not connected to the zero signal generation circuit 12 side. During this period, the encoding circuit 8
The data of the next block is output from, but this data output is absorbed by the delay circuit 9.

When the value of the register 15 exceeds the threshold value or when the code length measurement of one block is completed, the control circuit 65 controls the switch 11 to send the data to the re-encoding circuit block 18. At this time, the memory is serially accessed in the address order by the memory address generated by the address generation circuit 54. Re-encoding circuit block 1
The order of data input to 8 is the same as the order of input data in the memory. That is, y ₀ i (i = 1, 2, ..., 6
4), y ₁ i (i = 1, 2, ..., 64), y ₂ i (i =
1, 2, ..., 64), y ₃ i (i = 1, 2, ..., 6)
4), _cr i (i = 1, 2, ..., 64), c _b i (i =
1, 2, ..., 64).

However, when the value of the register 15 exceeds the threshold value in the data of the Nth frequency, {y ₀ i, y ₁ i, y ₂ i, y ₃ i, _cr i, c _b i} (i = 1, 2, ..., 64), the switch 11 is intermittently switched from the memory 10 side to the zero signal generation circuit 12 side so that the N + 1th and subsequent data in each subblock are all 0.

FIG. 3 shows the data flow from the output of the delay circuit 9 to the input of the re-encoding circuit block 18. In this example, it is assumed that the threshold value is exceeded at the time when the scanning of the memory 10 is started when the cr 60 is input to the memory 10 and the code length of cb 16 is added. At this time, the switch 11 is set so that the data string after that, that is, {y0 i, y1 i, y2 i, y3 i, cr i, cb i} (i = 17, 18, ..., 64) becomes 0. Is controlled.

In FIG. 3, when the switch control signal is "1", it is connected to the memory 10 side, and when it is "0", it is connected to the zero signal generating circuit 12 side. In the encoder 18, the order of the input data sequence of the memory 10, that is, y ₀ i (i = 1, 2, ..., 6)
4), y ₁ i (i = 1, 2, ..., 64), y ₂ i (i =
1, 2, ..., 64), y ₃ i (i = 1, 2, ..., 6)
4), _cr i (i = 1, 2, ..., 64), c _b i (i =
1, 2, ..., 64), where the actual variable length coding is performed in the re-encoding circuit block 18 and then sent to the output buffer 19. Then, finally, the signal 20 obtained by compression-encoding the input image is sent to a recording device, a transmission device, or the like.

As described above, in this embodiment, when the code amount of one block is measured, the code amount is not measured in time series as in the conventional case, but the storage circuit 10 corresponding to one block is used. One block of quantized data is stored by using the data, and one block of data stored in the storage circuit 10 is scanned in parallel between sub-blocks in order from the data with the lowest frequency to measure the code amount and cumulative addition is performed. If the result exceeds a certain threshold value, the data of high frequency thereafter is replaced with zero data and the code amount is controlled. As a result, the distribution of the code amount to each sub-block is made uniform, and a large deterioration in image quality does not occur. Also,
It is not necessary to significantly increase the circuit scale.

[0034]

As described above, according to the present invention, even when the code amount of one block exceeds a certain amount, the code amount can be appropriately distributed to each sub-block, and the image quality is not deteriorated. It is possible to control the code amount.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an image encoding device according to an embodiment of the present invention.

2 is a circuit diagram showing a specific configuration for controlling the code amount in the device of FIG.

3 is a timing chart illustrating a code amount control operation in the circuit of FIG.

FIG. 4 is a block diagram showing a configuration of a conventional image encoding device.

FIG. 5 is a diagram showing a configuration of a normal macroblock.

6A and 6B are views for explaining the rearrangement order of data after orthogonal transformation of sub-blocks belonging to the macro block of FIG.

FIG. 7 is a timing chart illustrating a code amount control operation in a conventional image encoding device.

[Explanation of symbols]

1 ... Input image signal, 2 ... Y / C separation circuit block, 3 ...
Screen division circuit block, 4 ... Sub block division circuit block, 5 ... Orthogonal transformation circuit block, 6 ... Frequency rearrangement circuit block, 7 ... Quantization circuit block, 8 ... Encoding circuit block, 9 ... Delay circuit, 10 ... Memory circuit, 11 ...
Switch, 13 ... Code length measuring circuit block, 14 ... Adder, 15 ... Register, 16 ... Comparator, 17 ... Switch control signal, 18 ... Re-encoding circuit block, 19 ... Output buffer, 54 ... Address generating circuit, 65 ... control circuit.

Claims (4)

[Claims] 1. An image coding apparatus for coding an image signal, wherein an input image signal is separated into a luminance signal and a color difference signal, and an image provided by the input image signal is divided into a luminance sub-block and a color difference signal. Means for dividing into a plurality of blocks including sub-blocks, an orthogonal transformation means for orthogonally transforming the luminance signal and the color difference signals included in the blocks in each sub-block unit, and a signal orthogonally transformed by this orthogonal transformation means Rearranging means for rearranging each sub-block in frequency order, quantizing means for quantizing the signals rearranged in frequency order by this rearranging means, and one block of quantized data output from the quantizing means. And a quantized data for one block stored in the storage means are scanned in parallel between the sub blocks to Code amount measuring means for measuring the code amount by cumulatively adding the code lengths of data, and code amount controlling means for controlling the code amount for each block based on the code amount measured by the code amount measuring means. An image coding apparatus comprising: 2. The code amount measuring means scans one block of quantized data in parallel between sub-blocks in order from the data with the lowest frequency component, and cumulatively adds the code length of each data to obtain the code amount. 1) stored in the storage means when the measured code amount exceeds a certain threshold value.
The image coding apparatus according to claim 1, wherein the code of the remaining unscanned quantized data in the quantized data for the block is zero. 3. The code amount measuring means executes parallel scanning between sub-blocks in an order according to the type of sub-block so that the scanning rate varies among the sub-blocks. Image encoding device. 4. An image coding apparatus for coding an image signal, wherein an input image signal is separated into a luminance signal and a color difference signal, and an image provided by the input image signal is divided into a luminance sub-block and a color difference signal. Means for dividing into a plurality of blocks including sub-blocks, an orthogonal transformation means for orthogonally transforming the luminance signal and the color difference signals included in the blocks in each sub-block unit, and a signal orthogonally transformed by this orthogonal transformation means Rearranging means for rearranging each sub-block in ascending order of frequency, quantizing means for quantizing the signals rearranged in frequency order by this rearranging means, and one block of quantum output from the quantizing means. Storage means for storing the encoded data, and one block of quantized data stored in the storage means is scanned in parallel between the sub-blocks. Then, by cumulatively adding the code lengths of the respective data, the code amount measuring means for measuring the code amount, and when the code amount measured by the code amount measuring means exceeds a certain threshold, the storage means stores the code amount. The stored quantized data for one block is continuously read, and the frequency of the read quantized data is higher than that of the quantized data scanned when the threshold value or more is exceeded in the read data string of each sub-block. An image coding apparatus, comprising means for replacing the code of the quantized data with zero.