JP4404232B2 - Quantization method, quantization apparatus, quantization step determination method, and quantization step determination apparatus - Google Patents

Description

によつて算出される。
【００２７】
ここで、（Σ_k ｌｌ（ｋ、ｑ〔３〕）−ｔｇｔ）は、第３の量子化器ｊ（ｊ＝３）によるｋ番目のマクロブロツクまでの積算符号長からターゲツト（ｔｇｔ）の符号長を減算した符号長を意味し、ｌｌ（ｉ、ｑ〔４〕）は、第４の量子化器ｊ（ｊ＝４）によるｉ番目のマクロブロツクの符号長を意味し、（ｔｇｔ−Σ_k ｌｌ（ｋ、ｑ〔４〕）は、ターゲツト（ｔｇｔ）の符号長と第４の量子化器ｊ（ｊ＝４）によるｋ番目のマクロブロツクまでの積算符号長との減算結果を意味し、ｌｌ（ｉ、ｑ〔３〕）は、第３の量子化器ｊ（ｊ＝３）によるｉ番目のマクロブロツクの符号長を意味し、Σ_k （ｋ、ｑ〔３〕）は、第３の量子化器ｊ（ｊ＝３）によるｋ番目のマクロブロツクまでの符号長を意味し、Σ_k ｌｌ（ｋ、〔４〕）は、第４の量子化器ｊ（ｊ＝４）によるｋ番目のマクロブロツクまでの符号長を意味する。
【００２８】
かくして目標符号長決定回路５４において、上述の（１）式から、等長化単位の目標符号長ｔｇｔを満足するようなマクロブロツクｉの目標符号長データｌｌ（ｉ）が決定されると、当該目標符号長決定回路５４はこれを目標符号長決定データＤ５４Ａとして本線系に設けられた量子化ステツプ決定手段としての二分探索回路６０に送出する。また目標符号長決定回路５４は、ｍｉｎ_j （ｌｌ（ｉ、ｑ〔ｊ〕）≦ｌｌ（ｉ））を満足する量子化インデツクスｑ〔ｊ〕を上述の目標符号長データｌｌ（ｉ）とともに目標符号長決定データＤ５４Ａとして二分探索回路６０に送出する。
【００２９】
ここで二分探索回路６０が設けられた本線系には、ＤＣＴ処理部２５から出力される係数データＤ２５をＦＩＦＯ回路２２に入力し、目標符号長決定回路５４を有する予測系における処理時間分だけ当該係数データＤ２５を遅延させた後、これを二分探索回路６０に送出するとともに、当該二分探索回路６０の処理時間分だけ入力データを遅延させるＦＩＦＯ回路５３に送出する。
図４は二分探索回路６０における二分探索方法を示し、横軸に量子化インデツクスを表すとともに縦軸に符号長を表す当該グラフにおいて、ｑ０〜ｑ３１（ｑ〔ｊ〕＝０を量子化インデツクスｑ０、ｑ〔ｊ〕＝３１を量子化インデツクスｑ３１とする）までの３２個の量子化インデツクスによりマクロブロツクｉを量子化しさらにこれを可変長符号化したときの符号長をプロツトした状態を表す。
【００３０】
ここで目標符号長データｌｌ（ｉ）を満足する最小の量子化インデツクスデータｑ、すなわちｑｉ＝ｍｉｎ_j （ｌｌ（ｉ、ｑ〔ｊ〕）≦ｌｌ（ｉ））の解を二分探索法によつて求める。
まず第１の処理手順（ＳＴＥＰ１）として、図４のグラフにおいて解はｑ０からｑ３１までの中に存在することが分かり、その解の範囲を二分する点（ｑ１５）での符号量を求める。この結果、ｌｌ（ｉ、ｑ１５）＞ｌｌ（ｉ）であることにより、解はｑ１６からｑ３１までの範囲に存在することが分かる。
【００３１】
従つて第２の処理手順（ＳＴＥＰ２）として、第１の処理手順において求められた解の存在範囲（ｑ１６〜ｑ３１）を二分する点（ｑ２３）の符号量を求める。この結果、ｌｌ（ｉ、ｑ２３）≦ｌｌ（ｉ）であることにより、解はｑ１６からｑ２３までの範囲に存在することが分かる。
【００３２】
従つて第３の処理手順（ＳＴＥＰ３）として、第２の処理手順において求められた解の存在範囲（ｑ１６〜ｑ２３）を二分する点（ｑ１９）の符号量を求める。この結果、ｌｌ（ｉ、ｑ１９）≦ｌｌ（ｉ）（実際にはｌｌ（ｉ、ｑ１９）＝ｌｌ（ｉ））であることにより、解はｑ１６からｑ１９までの範囲に存在することが分かる。
【００３３】
従つて第４の処理手順（ＳＴＥＰ４）として、第３の処理手順において求められた解の存在範囲（ｑ１６〜ｑ１９）を二分する点（ｑ１７）の符号量を求める。この結果、ｌｌ（ｉ、ｑ１７）＞ｌｌ（ｉ）であることにより、解はｑ１８からｑ１９までの範囲に存在することが分かる。
【００３４】
従つて第５の処理手順（ＳＴＥＰ５）として、第４の処理手順において求められた解の存在範囲（ｑ１８〜ｑ１９）を二分する点（ｑ１８）の符号量を求める。この結果、ｌｌ（ｉ、ｑ１８）≦ｌｌ（ｉ）（実際にはｌｌ（ｉ、ｑ１８）＝ｌｌ（ｉ））であることにより、解はｑ１８からｑ１８までの範囲、すなわちｑ１８であることが分かる。
【００３５】
このように二分探索法では常に探索ステツプＳＴＥＰ（ｘ）の数ｘは、解の存在範囲をＡＲ（この実施例の場合ｑ０〜ｑ３１である）として、次式、
【数２】

となる。
【００３６】
かくして二分探索回路６０は、求められた量子化インデツクスｑ１８を量子化制御信号ＣＯＮＴ６０として量子化器６に送出し、ＦＩＦＯ回路５３を介して量子化器６に入力された係数データＤ２５をこの量子化インデツクスｑ１８を用いて量子化する。これにより量子化器６は、予測系の目標符号長決定回路５４によつて得られたマクロブロツクの目標符号長を満足する量子化レベルデータＤ６を続く可変長符号部７に送出する。
可変長符号部７は量子化レベルデータＤ６を可変長符号化することによつてビツトストリームＤ７を完成させ、これをバツフア回路８を介して所定の出力レートで出力端子Ｔ３に出力する。
【００３７】
因みに図５は３０個のＤＣＴブロツクからなる等長化単位を用いてビツトストリームＤ７を完成させる際のタイミングチヤートを示し、図５（Ａ）はアクテイビテイ検出回路５０の検出出力を示し、例えば（ｎ、０）は等長化単位「ｎ」の「０」番のＤＣＴブロツクのアクテイビテイ検出出力を示す。但しこの実施例においては６個のＤＣＴブロツクによつて形成されたマクロブロツク単位でアクテイビテイを検出している。
【００３８】
また図５（Ｂ）はＤＣＴ処理部２５のＤＣＴ出力（係数データＤ２５）を示し、例えば（ｎ、０）は等長化単位「ｎ」の「０」番のＤＣＴブロツクのＤＣＴ出力を示す。
また図５（Ｃ）は予測系に設けられた量子化器２６（２６Ａ、２６Ｂ、……、２６ｎ）の量子化出力（量子化レベルデータＤ２６Ａ、Ｄ２６Ｂ、……、Ｄ２６ｎ）を示し、例えば（ｎ、０）は等長化単位「ｎ」の「０」番のＤＣＴブロツクの量子化出力を示す。
また図５（Ｄ）は変換回路２７（２７Ａ、２７Ｂ、……、２７ｎ）の変換出力（符号長データＤ２７Ａ、Ｄ２７Ｂ、……、Ｄ２７ｎ）を示し、例えば（ｎ、０）は等長化単位「ｎ」の「０」番のＤＣＴブロツクの変換出力を示す。
【００３９】
また図５（Ｅ）は積算回路５１Ａ、５１Ｂ、……、５１ｎの１等長化単位ごとの積算出力を示す。
また図５（Ｆ）は各積算回路５１Ａ、５１Ｂ、……、５１ｎに対応して設けられているＦＩＦＯ回路５２Ａ、５２Ｂ、……、５２ｎの出力を示し、例えば（ｎ、０）は等長化単位「ｎ」の「０」番のＤＣＴブロツクのＦＩＦＯ出力を示す。また図５（Ｇ）は目標符号長決定回路５４の目標符号長決定データＤ５４Ａを示し、例えば（ｎ、０）は等長化単位「ｎ」の「０」番のＤＣＴブロツクに対した決定データを示す。
また図５（Ｈ）は本線系に設けられたＦＩＦＯ回路２２の出力を示し、例えば（ｎ、０）は等長化単位「ｎ」の「０」番のＤＣＴブロツクのＦＩＦＯ出力を示す。
【００４０】
また図５（Ｉ）は二分探索回路６０の探索出力、すなわちマクロブロツク単位で求められた量子化インデツクスを表す量子化制御信号ＣＯＮＴ６０を示し、例えば（ｎ−１、０）は等長化単位「ｎ−１」の「０」番のＤＣＴブロツクの量子化インデツクスを示す。但しこの実施例の場合、マクロブロツクごとに目標符号長を満足する量子化インデツクスを求めている。
また図５（Ｊ）は本線系に設けられた量子化器６の量子化出力（量子化レベルデータＤ６を示し、例えば（ｎ−１、０）は等長化単位「ｎ−１」の「０」番のＤＣＴブロツクの量子化出力を示す。
また図５（Ｋ）は可変長符号部７の可変長符号化出力（ビツトストリーム）Ｄ７を示し、例えば（ｎ−１、０）は等長化単位「ｎ−１」の「０」番のＤＣＴブロツクの可変長符号化出力を示す。
【００４１】
以上の構成において、画像信号符号化装置２０は、走査変換／シヤフリング回路２１において入力画像信号をマクロブロツク単位でシヤフリングすることにより、例えば１画面内に複雑な画像部分と平坦な画像部分が存在する場合でも、シヤフリングによつて平均的な画面が形成される。
【００４２】
このような画面を形成する複数のマクロブロツクのなかから所定数のマクロブロツクによつて等長化単位を形成することにより、この等長化単位ごとに積算して得られる符号長は１画面の符号長を均等に配分した符号長と見なすことができる。
【００４３】
従つてこの等長化単位を所定の目標符号長ｔｇｔとなるような量子化インデツクスを求め当該量子化インデツクスによつて量子化することにより、１画面（１フレーム）の符号量が目標量となるような量子化インデツクスで本線系の量子化が行われる。
【００４４】
このような符号量制御を等長化単位で行うことにより、例えば予測系に設けられたＦＩＦＯ回路５２Ａ〜５２ｎとしてそれぞれ１等長化単位分の容量のものを用意すれば良く、また積算回路５１Ａ〜５１ｎにおいても同様にして１等長化単位の処理をし得る回路規模で良く、１フレーム分で処理する場合に比べて一段と小規模な回路構成となる。
【００４５】
またアクテイビテイ検出回路５０において等長化単位内のマクロブロツクについてのアクテイビテイを検出し、これにより予測系の量子化器２６の量子化ステツプをマクロブロツク単位で局所的に切り換えることにより、１等長化単位内に含まれる局所的な画像の粗密に応じた量子化レベルによつてマクロブロツクごとの目標符号長が決定される。従つて本線系における復号画像の画質を一段と向上することができる。
【００４６】
因みにシヤフリングによつて形成された等長化単位には画面上のマクロブロツクが平均的に含まれており、これにより各等長化単位ごとにはアクテイビテイの偏りがなく、１画面内における各等長化単位の符号長は同じものとなる。従つて目標符号長決定回路５４においてマクロブロツクの目標符号長を決定する際のターゲツトとなる等長化単位ごとの積算値（ｔｇｔ）は、１画面（１フレーム）の符号量を単純に１画面内の等長化単位数に応じて配分すれば良く、このようなターゲツトに対して１画面内の各等長化単位の画像はそれぞれ同様の絵柄を持つた単位となり、１画面内のすべての等長化単位についてこのターゲツトに合わせたマクロブロツクごとの目標符号長を決定するだけで１画面内の局所的な粗密の変化に対応した復号画像を得ることができる。
【００４７】
以上の構成によれば、マクロブロツク単位でシヤフリングするとともに複数のマクロブロツクによつて等長化単位を形成することにより、一段と小規模な回路構成によつて画面の粗密の偏つた分布を考慮することなく高画質の復号画像を得ることができる。
【００４８】
なお上述の実施例においては、二分探索回路６０における探索方法として量子化インデツクスｑ０〜ｑ３１を二分する点（ｑ１５）の符号量を求める第１の処理手順（ＳＴＥＰ１）から探索を開始する場合について述べたが、本発明はこれに限らず、予測系の目標符号長決定回路５４において既に求められたデータを用いて二分探索の処理を簡略化することができる。
【００４９】
すなわち図１との対応部分に同一符号を付して示す図６において、目標符号長決定回路５４は、予測系の量子化器２６のうちの第３の量子化器ｊ（ｊ＝３）の持つ量子化インデツクスｑ１５と、第４の量子化器ｊ（ｊ＝４）の持つ量子化インデツクスｑ２３との間に目標符号長ｔｇｔを得ることができる量子化インデツクスが存在することが分かつている。
【００５０】
すなわち目標符号長決定回路５４においてマクロブロツクｉの目標符号長ｌｌ（ｉ）と、ｍｉｎ_j （ｌｌ（ｉ、ｑ〔ｊ〕）≦ｌｌ（ｉ））である量子化イデツクスｑ〔ｊ〕が求められているので、この情報を利用することにより、解の範囲がｑ〔ｊ−１〕からｑ〔ｊ〕であることが分かる。従つて目標符号長決定回路５４は、この量子化インデツクスｑ１５及びｑ２３を量子化インデツクスデータＤ５４Ｂとして二分探索回路７０に送出することにより、二分探索回路７０において、目標符号長ｔｇｔを得ることのできる量子化インデツクスが量子化インデツクスｑ１５とｑ２３との間にあるという情報を利用する。
【００５１】
例えば図２に示す量子化器と量子化インデツクスの関係から、解の範囲は図１について上述した二分探索回路６０における探索方法においてｑ０〜ｑ３１の３２個の範囲であつたものが、図６の二分探索回路７０においてはｑ１５〜ｑ２３の８個の範囲とすることができる。つまり解はｑ１５（＝ｑ〔３〕）より大きくｑ２３（＝ｑ〔４〕）以下の範囲にあることになる。
【００５２】
従つて二分探索回路７０においては、図１の二分探索回路６０における第３の処理手順（ＳＴＥＰ３）から処理を開始すれば良い。この結果二分探索回路７０においては、図１の二分探索回路６０について上述した第１の処理手順（ＳＴＥＰ１）及び第２の処理手順（ＳＴＥＰ２）を省略することができ、当該二分探索法では探索ステツプＳＴＥＰ（ｘ）の数ｘは、量子化器の量子化インデツクスの差分をＤＩＦとして、次式、
【数３】

となる。従つて二分探索回路７０に対応して設けられているＦＩＦＯ回路７３の回路規模を図１について上述したＦＩＦＯ回路５３に比べて一段と小さくすることができる。
【００５３】
因みに図７は３０個のＤＣＴブロツクからなる等長化単位を用いてビツトストリームＤ７を完成させる際のタイミングチヤートを示し、図７（Ａ）はアクテイビテイ検出回路５０の検出出力を示し、例えば（ｎ、０）は等長化単位「ｎ」の「０」番のＤＣＴブロツクのアクテイビテイ検出出力を示す。但しこの実施例においては６個のＤＣＴブロツクによつて形成されたマクロブロツク単位でアクテイビテイを検出している。
【００５４】
また図７（Ｂ）はＤＣＴ処理部２５のＤＣＴ出力（係数データＤ２５）を示し、例えば（ｎ、０）は等長化単位「ｎ」の「０」番のＤＣＴブロツクのＤＣＴ出力を示す。
また図７（Ｃ）は予測系に設けられた量子化器２６（２６Ａ、２６Ｂ、……、２６ｎ）の量子化出力（量子化レベルデータＤ２６Ａ、Ｄ２６Ｂ、……、Ｄ２６ｎ）を示し、例えば（ｎ、０）は等長化単位「ｎ」の「０」番のＤＣＴブロツクの量子化出力を示す。
また図７（Ｄ）は変換回路２７（２７Ａ、２７Ｂ、……、２７ｎ）の変換出力（符号長データＤ２７Ａ、Ｄ２７Ｂ、……、Ｄ２７ｎ）を示し、例えば（ｎ、０）は等長化単位「ｎ」の「０」番のＤＣＴブロツクの変換出力を示す。
【００５５】
また図７（Ｅ）は積算回路５１Ａ、５１Ｂ、……、５１ｎの１等長化単位ごとの積算出力を示す。
また図７（Ｆ）は各積算回路５１Ａ、５１Ｂ、……、５１ｎに対応して設けられているＦＩＦＯ回路５２Ａ、５２Ｂ、……、５２ｎの出力を示し、例えば（ｎ、０）は等長化単位「ｎ」の「０」番のＤＣＴブロツクのＦＩＦＯ出力を示す。また図７（Ｇ）は目標符号長決定回路５４の目標符号長決定データＤ５４Ａを示し、例えば（ｎ、０）は等長化単位「ｎ」の「０」番のＤＣＴブロツクに対した決定データを示す。
また図７（Ｈ）は本線系に設けられたＦＩＦＯ回路２２の出力を示し、例えば（ｎ、０）は等長化単位「ｎ」の「０」番のＤＣＴブロツクのＦＩＦＯ出力を示す。
【００５６】
また図７（Ｉ）は二分探索回路７０の探索出力、すなわちマクロブロツク単位で求められた量子化インデツクスを表す量子化制御信号ＣＯＮＴ７０を示し、例えば（ｎ−１、０）は等長化単位「ｎ−１」の「０」番のＤＣＴブロツクの量子化インデツクスを示す。但しこの実施例の場合、マクロブロツクごとに目標符号長を満足する量子化インデツクスを求めている。
また図７（Ｊ）は本線系に設けられた量子化器６の量子化出力（量子化レベルデータＤ６を示し、例えば（ｎ−１、０）は等長化単位「ｎ−１」の「０」番のＤＣＴブロツクの量子化出力を示す。
また図７（Ｋ）は可変長符号部７の可変長符号化出力（ビツトストリーム）Ｄ７を示し、例えば（ｎ−１、０）は等長化単位「ｎ−１」の「０」番のＤＣＴブロツクの可変長符号化出力を示す。
【００５７】
図７のタイミングチヤートによれば、二分探索回路７０における探索方法が図１について上述した二分探索方法に比べて処理手順（ＳＴＥＰ）が少ない分、図７（Ｉ）に示す二分探索出力の出力タイミングが早くなる。
【００５８】
また上述の実施例においては、変換符号化の手法としてＤＣＴを用いた場合について述べたが、本発明はこれに限らず、例えばウエーブレツト変換、Ｈａａｒ変換又はＫ−Ｌ変換等、他の種々の変換手法を用いることができる。
【００５９】
また上述の実施例においては、アクテイビテイ回路５０におけるアクテイビテイの検出方法として、色の飽和度をマクロブロツクごとに調べた場合について述べたが、本発明はこれに限らず、例えばＤＣＴ係数の低域成分及びその高域成分の分布を調べて、マクロブロツクの画像が細かいものか又は平坦なものかを検出したり、又はマクロブロツクの画像とチエツカーフラツグのパターンとのマツチングをとることによつて、当該マクロブロツクの画像の細かさを調べる等、他の種々の方法を用いることができる。
【００６０】
また上述の実施例においては、目標符号長決定回路５４における目標符号長の予測方法として、直線近似による方法を用いる場合について述べたが、本発明はこれに限らず、より多くの点を用いる高次関数による近似を用いても良い。
【００６１】
また上述の実施例においては、１画面（１フレーム）内でマクロブロツク単位のシヤフリングを行つた場合について述べたが、本発明はこれに限らず、異なる画面（フレーム）間でのシヤフリング（時間軸方向に対するシヤフリング）を行うようにしても良い。
【００６２】
また上述の実施例においては、１フレームでビツトレートを維持するように制御した場合について述べたが、本発明はこれに限らず、これよりも大きな単位又は小さな単位でビツトレートを維持するように制御しても良い。
【００６３】
また上述の実施例においては、４：２：０フオーマツトのマクロブロツク構造を用いた場合について述べたが、本発明はこれに限らず、例えば４：２：２フオーマツト、４：４：４フオーマツト又は４：１：１フオーマツト等、種々のフオーマツトのマクロブロツクを用いるようにしても良い。また、マクロブロツクを構成するＤＣＴブロツクの個数に制限はない。
【００６４】
また上述の実施例においては、ＤＣＴ処理を行う前のデータについてアクテイビテイの検出を行う場合について述べたが、本発明はこれに限らず、ＤＣＴ処理を施した後のデータに対してアクテイビテイ検出を行うようにしても良い。
【００６５】
また上述の実施例においては、ＶＴＲの画像信号符号化方法及び画像信号符号化装置に本発明を適用した場合について述べたが、本発明はこれに限らず、例えば光磁気記録デイスク又はハードデイスク等の記録媒体に記録する場合、さらには記録媒体を用いない通信系の画像信号符号化方法及び画像信号符号化装置においても本発明を適用し得る。
【００６６】
【発明の効果】
上述のように本発明によれば、画像信号をブロツク単位でシヤフリングし、平均的な画面を形成するブロツクを集めることによつて等長化単位を形成し、等長化単位を構成するブロツク単位のデータを複数の量子化ステツプでそれぞれ量子化することにより得られた複数の量子化出力の各符号長を等長化単位分にわたつてそれぞれ積算し、複数の積算値の中で等長化単位での目標符号長に最も近い２つの積算値の間を直線近似して、所望のビツトレートを満足するブロツク単位の目標符号長を割り当て、その割り当てたブロツク単位の目標符号長を満足する量子化ステツプを決定し、その量子化ステツプによつてブロツク単位のデータを量子化することにより、符号長に基づいて１画面分の発生符号量を予め決められたビツトレートに制御し、画面内に局所的に変化する絵柄の粗密が存在する場合でも復号画像の画質劣化を回避することができ、かくして画像の局所的性質に適応したフイードフオワード方式の符号量制御を一段と小規模な回路構成によつて実現することができる。
【図面の簡単な説明】
【図１】本発明による画像信号符号化装置の一実施例を示すブロツク図である。
【図２】量子化器の量子化インデツクスの割り当てを示す図表である。
【図３】量子化器及び１等長化単位分の積算値を示すグラフである。
【図４】二分探索法の説明に供するグラフである。
【図５】本発明による画像信号符号化処理を示すタイミングチヤートである。
【図６】他の実施例による画像信号符号化装置を示すブロツク図である。
【図７】他の実施例による画像信号符号化処理を示すタイミングチヤートである。
【図８】従来の画像信号符号化装置を示すブロツク図である。
【符号の説明】
２０……画像信号符号化装置、２１……走査変換／シヤフリング回路、２５……ＤＣＴ処理部、６、２６……量子化器、７……可変長符号部、８……バツフア回路、５０……アクテイビテイ検出回路、５１Ａ〜５１ｎ……積算回路、５４……目標符号長決定回路、６０、７０……二分探索回路。[0001]
【table of contents】
The present invention will be described in the following order.
TECHNICAL FIELD OF THE INVENTION
Conventional technology (Fig. 8)
Problems to be solved by the invention
Means for solving the problem
BEST MODE FOR CARRYING OUT THE INVENTION (FIGS. 1-7)
The invention's effect
[0002]
BACKGROUND OF THE INVENTION
The present invention relates to an image signal encoding method and an image signal encoding apparatus, and is suitable for application to an image signal encoding method and an image signal encoding apparatus used for recording an image signal on a VTR (video tape recorder), for example. It is a thing.
[0003]
[Prior art]
Conventionally, in an image compression method typified by the MPEG (Moving Pictures Expert Group) standard, code amount control is performed so that a bit stream sent to a transmission path has a desired rate. In the conventional code amount control, the quantization step is feedback-controlled based on the relationship between the previous quantization step and the code amount and the current average rate.
[0004]
That is, FIG. 8 shows an image signal encoding apparatus in a VTR, in which a digital input image signal is supplied to a scan conversion macroblocking circuit 1 via an input terminal T1, and an image of one frame is a plurality of DCT blocks consisting of several DCT blocks. It is divided into macroblocks. In MPEG, the luminance signal is divided into 16 × 16 blocks, and the color difference signal is C: 2 in the case of 4: 2: 2. _r , C _b Both are divided into blocks of 8 × 8 size, and these six DCT blocks are combined to form one macro block.
[0005]
The macroblocked data in the scan conversion macroblocking circuit 1 is subjected to DCT (Discrete Cosine Transform) processing for each DCT block in the subsequent DCT processing unit 5, and the coefficient data obtained as a result is quantized in the quantizer 6. .
The quantized data (hereinafter referred to as the quantization level) is subjected to variable length coding processing in the variable length coding unit 7 and sent to the buffer circuit 8. The buffer circuit 8 sends the data generation amount and the output bit rate to the quantization control circuit 9. The quantization control circuit 9 determines a quantization index representing a predetermined quantization step in consideration of the amount of data generated and the output bit rate, and controls the quantization step (quantization index) of the quantizer 6.
Thus, a bit stream is output from the buffer circuit 8 to the output terminal T2 at a predetermined bit rate.
[0006]
[Problems to be solved by the invention]
By the way, in the image signal encoding apparatus having such a configuration, first, by performing feedback control from the buffer circuit 8 to the quantizer 6, if the damping is reduced for the purpose of increasing the reaction speed, it becomes oscillating. Increasing it has the problem of slowing the reaction, despite the decrease in vibration.
Secondly, there is a problem that the rate is instantaneously increased at a location such as a scene change, causing an extreme deterioration of the image due to a failure of the reproduced image.
Third, it is difficult to control a predetermined number of frames so as to be held down to a predetermined bit rate. For example, when recording data on a tape-shaped recording medium, the length of each frame is long. Becomes indefinite, and it becomes difficult to specify the break of the image on the tape.
[0007]
As a method for solving these problems, a method of controlling the code amount by the feed forward method is considered. In this method, a code amount generated in a predetermined unit is calculated in advance for a plurality of quantization indexes, and an appropriate quantization index is determined within a range in which the generated code amount does not exceed a target code amount.
[0008]
As a predetermined unit in the code amount control of the feedforward method, a GOP (Group Of Picture), a frame, or the like can be considered. GOP is image data of one frame or more. In the case of MPEG2, it is conceivable to control the code amount in units of GOP.
When the code amount is controlled in this way, a plurality of quantization steps are fixed values different from each other, and one of the quantization steps is selected for the GOP. Therefore, the image quality of the decoded image for each macroblock is determined. There was a problem with different quality. For example, the image quality of a macro block with a fine pattern is degraded, and on the contrary, the image quality of a macro block with a flat pattern is good. Therefore, when such a difference in image quality is large between adjacent macro blocks, there is a problem that block distortion occurs.
[0009]
The present invention has been made in consideration of the above points, and an image that can improve the image quality of a decoded image by performing a control adapted to the local nature of the image signal in the code amount control of the feed forward method. A signal encoding method and an image signal encoding apparatus are proposed.
[0010]
[Means for Solving the Problems]
In order to solve such a problem, in the present invention, in a quantization method for predicting a quantization step in which an encoded image signal has a desired bit rate and quantizing the image signal based on the prediction result, the image signal is A predetermined equal length unit is formed from an image portion made up of a plurality of block units obtained as a result of being shuffled in a predetermined block unit, and the block unit data constituting the equal length unit is quantized by a plurality of quantization steps. The code lengths of the quantized outputs quantized by the quantizing steps are divided into equal length units. Respectively Accumulating, Multiple Integration of A linear approximation is made between the two integrated values closest to the target code length in the equal length unit among the values, Allocating a target code length of the block unit that satisfies the desired bit rate, determining a quantization step that satisfies the target code length of the allocated block unit, and using the determined quantization step, data in block unit Quantize.
[0011]
Further, in the present invention, in a quantization apparatus that predicts a quantization step in which an encoded image signal has a desired bit rate and quantizes the image signal based on the prediction result, the image signal is a predetermined block unit. The equal length unit forming means for forming a predetermined equal length unit from the image portion composed of a plurality of block units obtained as a result of the shuffling, and the data of the block unit constituting the equal length unit in a plurality of quantization steps. Predictive quantization means to quantize and code lengths of multiple quantized outputs quantized in multiple quantizing steps for equal length units Respectively Accumulating, Multiple Integration of A linear approximation is made between the two integrated values closest to the target code length in the equal length unit among the values, Target code length determining means for assigning a target code length in block units satisfying a desired bit rate, quantization step determining means for determining a quantization step satisfying the target code length in the allocated block units, and a quantization step Quantization means for quantizing data in block units according to the quantization step determined by the determination means is provided.
[0012]
In the present invention, the image signal is shuffled in units of blocks to form an average screen even when a complex pattern image portion and a flat pattern image portion exist in one screen. An equal length unit is formed by a predetermined number of blocks from a plurality of blocks forming a screen. Then, the code lengths of the plurality of quantized outputs obtained by quantizing the block unit data constituting the equalized unit by the plurality of quantization steps are respectively integrated over the equalized unit. , A linear approximation between the two integrated values closest to the target code length in the equal length unit among the plurality of integrated values, Allocating a target code length in block units that satisfies the desired bit rate, determining a quantization step that satisfies the target code length in the allocated block unit, and quantizing the data in block units by the quantization step Thus, it is possible to avoid degradation of the image quality of the decoded image even when there is a pattern density that changes locally in the screen.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.
[0014]
In FIG. 1, in which parts corresponding to those in FIG. 8 are denoted by the same reference numerals, the image signal encoding device 20 converts the image signal input to the input terminal T 1 into a frame after field-frame conversion in the scan conversion / shuffling circuit 21. The image signal of the shape is divided into macroblocks consisting of several DCT blocks. For example, in MPEG, the luminance signal is 16 × 16 and the color difference signal C _r , C _b Is C for (4: 2: 0) _r , C _b Both are divided into 8 × 8 blocks, and these 6 DCT blocks are combined to form a single block.
[0015]
In addition, the scan conversion / shuffling circuit 21 forms macroblocks, and then performs scanning in units of these macroblocks using a memory for scan conversion, thereby creating equal length units formed by a plurality of macroblocks. . As a result, equal length units are formed by a plurality of macroblocks collected evenly from the screen.
[0016]
The equalized unit data D21 output from the scan conversion / shuffling circuit 21 is output to the DCT processing unit 25 and the activity detection circuit 50, respectively. The DCT processing unit 25 obtains coefficient data D25 from a direct current component to a higher order alternating current component by performing DCT processing on the equalized unit data D21 for each DCT block, and obtains coefficient data D25 from a DC component to a higher-order AC component. , 26B,..., 26n, and output to a FIFO (First-In First-Out) circuit 22 provided as a delay means in the main line system.
[0017]
The activity detection circuit 50 detects the activity in units of macroblocks for a plurality of macroblocks forming the equal length unit output from the scan conversion / shuffling circuit 21. Here, the activity is the complexity of the image information of the macro block (that is, the visibility of image quality deterioration). For example, the saturation of the color is checked for each macro block, and if the saturation is high, the activity of the macro block is Judged to be high.
[0018]
The activity detection circuit 50 sends a quantizing step control signal CONT50 corresponding to the detected activity to each quantizer 26A, 26B,..., 26n, whereby each quantizer 26A, 26B,. The quantization step is switched in units of macroblocks. Here, the quantizers 26A, 26B,..., 26n are adapted to quantize the coefficient data D25 in different quantization steps, respectively, and when the activity detected by the activity detection circuit 50 is high (that is, image quality deterioration) ), The quantization step control signal CONT50 changes the quantization steps of the quantizers 26A, 26B,..., 26n in a direction that becomes finer. In some cases (that is, when deterioration in image quality is not conspicuous), the quantization steps 26A, 26B,..., 26n are changed in a coarse direction by the quantization step control signal CONT50.
[0019]
Data quantized by the quantizers 26A, 26B, ..., 26n (quantization levels) D26A, D26B, ..., D26n are sent to the subsequent conversion circuits 27A, 27B, ..., 27n, respectively. . The conversion circuits 27A, 27B,..., 27n obtain code lengths when the variable-level coding is performed for the respective quantization levels D26A, D26B,. To the subsequent integration circuits 51A, 51B,..., 51n. Incidentally, when obtaining the code length data D27A, D27B,..., D27n in the conversion circuits 27A, 27B,. It ’s fine.
[0020]
The integration circuits 51A, 51B,..., 51n integrate the code length data D27A, D27B,..., D27n by equal length units, and then send them to the target code length determination circuit 54. The code length data D27A, D27B,..., D27n output from the conversion circuits 27A, 27B,..., 27n are FIFOs provided corresponding to the integrating circuits 51A, 51B,. , 52n, and is sent to the target code length determination circuit 54 after being delayed by the integration time in the integration circuit.
[0021]
The target code length determination circuit 54 determines a target code length for each macro block based on the result of integration in each of the integration circuits 51A, 51B,. In this embodiment, a method of assigning a target code length by linear approximation is used. For example, the total number of quantization steps of the quantizers 26A, 26B,..., 26n of the image signal encoding device 20 is 32 from 0 to 31, and the number (n) of quantizers is 5. .
[0022]
At this time, if the quantization index representing the quantization step of each quantizer j (a predetermined quantizer among the five quantizers 26A to 26n (n = E)) is q [j], five quantizers are used. Assume that each quantization index of the device j (j = 1, 2, 3, 4, 5) is assigned as shown in FIG.
[0023]
Assuming that the code length of the i-th macroblock by the quantizer j is 11 (i, q [j]), a unit of equal length units by the quantizer j (j = 1, 2, 3, 4, 5) Integrated value Σ _i As shown in FIG. 3, ll (i, q [j]) is a different integrated value because the quantization index is different in each quantizer j. In FIG. 3, the vertical axis indicates the code length, and the horizontal axis indicates the quantizer j. Further, tgt represents a target code length, and is input from the outside via the input terminal 54A. The target code length tgt in the unit of equal length is set so that the target code length in one screen (one frame) unit can be satisfied if the code length tgt is satisfied.
[0024]
In FIG. 3, the code lengths of the equal length units obtained as a result of quantization in each quantizer j (j = 1, 2, 3, 4, 5) are respectively Σ _i ll (i, q [1]) to Σ _i ll (i, q [5]), and the target code length tgt is the code length Σ when quantized by the third quantizer j (j = 3). _i code length Σ when quantized by ll (i, q [3]) and the fourth quantizer j (j = 4) _i ll (i, q [4]).
[0025]
Therefore, the quantization index q [j] capable of obtaining the target code length tgt is the quantization index q [3] = 15 assigned to the third quantizer j (j = 3) and the fourth quantization. It can be seen that the quantization index q [4] = 23 assigned to the unit j (j = 4). Therefore, the code length Σ in FIG. _i ll (i, q [3]) and code length Σ _i By performing linear approximation with ll (i, q [4]), the target code length for each macroblock that satisfies the target code length tgt can be obtained.
[0026]
Therefore, if the target code length of the macroblock i is ll (i), this target code length ll (i) is given by
[Expression 1]

It is calculated by.
[0027]
Where (Σ _k ll (k, q [3])-tgt) is a code length obtained by subtracting the code length of the target (tgt) from the accumulated code length up to the k-th macroblock by the third quantizer j (j = 3). Ll (i, q [4]) means the code length of the i-th macroblock by the fourth quantizer j (j = 4), and (tgt−Σ _k ll (k, q [4]) means a subtraction result between the code length of the target (tgt) and the accumulated code length up to the k-th macroblock by the fourth quantizer j (j = 4), ll (i, q [3]) means the code length of the i-th macroblock by the third quantizer j (j = 3), and Σ _k (K, q [3]) means the code length up to the k-th macroblock by the third quantizer j (j = 3), and Σ _k ll (k, [4]) means the code length up to the k-th macroblock by the fourth quantizer j (j = 4).
[0028]
Thus, when the target code length determination circuit 54 determines the target code length data ll (i) of the macroblock i that satisfies the target code length tgt of the equal length unit from the above-described equation (1), The target code length determination circuit 54 sends this as target code length determination data D54A to a binary search circuit 60 as quantization step determination means provided in the main line system. The target code length determination circuit 54 _j The quantization index q [j] satisfying (ll (i, q [j]) ≦ ll (i)) is input to the binary search circuit 60 as the target code length determination data D54A together with the target code length data ll (i). Send it out.
[0029]
Here, in the main line system in which the binary search circuit 60 is provided, the coefficient data D25 output from the DCT processing unit 25 is input to the FIFO circuit 22, and the processing corresponding to the processing time in the prediction system having the target code length determination circuit 54 is included. After the coefficient data D25 is delayed, the coefficient data D25 is sent to the binary search circuit 60 and also sent to the FIFO circuit 53 that delays the input data by the processing time of the binary search circuit 60.
FIG. 4 shows a binary search method in the binary search circuit 60. In the graph in which the horizontal axis represents the quantization index and the vertical axis represents the code length, q0 to q31 (q [j] = 0 is the quantization index q0, This represents a state in which the code length is plotted when the macroblock i is quantized by 32 quantized indexes up to q [j] = 31 (quantized index q31) and further variable-length coded.
[0030]
Here, the minimum quantization index data q satisfying the target code length data ll (i), that is, qi = min _j A solution of (ll (i, q [j]) ≦ ll (i)) is obtained by a binary search method.
First, as a first processing procedure (STEP 1), it is found that the solution exists in q0 to q31 in the graph of FIG. 4, and the code amount at the point (q15) that bisects the range of the solution is obtained. As a result, since ll (i, q15)> ll (i), it can be seen that the solution exists in the range from q16 to q31.
[0031]
Therefore, as the second processing procedure (STEP 2), the code amount of the point (q23) that bisects the existence range (q16 to q31) of the solution obtained in the first processing procedure is obtained. As a result, it is found that the solution exists in the range from q16 to q23 by ll (i, q23) ≦ ll (i).
[0032]
Accordingly, as the third processing procedure (STEP 3), the code amount of the point (q19) that bisects the existence range (q16 to q23) of the solution obtained in the second processing procedure is obtained. As a result, ll (i, q19) ≦ ll (i) (actually ll (i, q19) = ll (i)) indicates that the solution exists in the range from q16 to q19.
[0033]
Therefore, as the fourth processing procedure (STEP 4), the code amount of the point (q17) that bisects the existence range (q16 to q19) of the solution obtained in the third processing procedure is obtained. As a result, since ll (i, q17)> ll (i), it can be seen that the solution exists in the range from q18 to q19.
[0034]
Therefore, as the fifth processing procedure (STEP 5), the code amount of the point (q18) that bisects the existence range (q18 to q19) of the solution obtained in the fourth processing procedure is obtained. As a result, ll (i, q18) ≦ ll (i) (actually ll (i, q18) = ll (i)), so that the solution is in the range from q18 to q18, that is, q18. I understand.
[0035]
Thus, in the binary search method, the number x of the search steps STEP (x) is always expressed by the following equation, where AR is the solution existence range (in this embodiment, q0 to q31):
[Expression 2]

It becomes.
[0036]
Thus, the binary search circuit 60 sends the obtained quantization index q18 to the quantizer 6 as the quantization control signal CONT60, and the coefficient data D25 input to the quantizer 6 via the FIFO circuit 53 is quantized. Quantization is performed using the index q18. As a result, the quantizer 6 sends the quantization level data D6 that satisfies the target code length of the macroblock obtained by the target code length determination circuit 54 of the prediction system to the subsequent variable length code unit 7.
The variable length coding unit 7 completes the bit stream D7 by performing variable length coding on the quantization level data D6, and outputs it to the output terminal T3 via the buffer circuit 8 at a predetermined output rate.
[0037]
Incidentally, FIG. 5 shows a timing chart when the bit stream D7 is completed using an equal length unit composed of 30 DCT blocks. FIG. 5A shows a detection output of the activity detection circuit 50, for example (n , 0) indicates the activity detection output of the DCT block of number “0” in the equalization unit “n”. However, in this embodiment, the activity is detected in units of macro blocks formed by six DCT blocks.
[0038]
FIG. 5B shows the DCT output (coefficient data D25) of the DCT processing unit 25. For example, (n, 0) shows the DCT output of the DCT block of “0” in the equal length unit “n”.
FIG. 5C shows the quantized output (quantized level data D26A, D26B,..., D26n) of the quantizer 26 (26A, 26B,..., 26n) provided in the prediction system. n, 0) indicates the quantized output of the DCT block of “0” in the equalization unit “n”.
5D shows the conversion output (code length data D27A, D27B,..., D27n) of the conversion circuit 27 (27A, 27B,..., 27n), for example, (n, 0) is an equal length unit. The conversion output of the DCT block of “n” “0” is shown.
[0039]
FIG. 5E shows an integrated output for each equal length unit of the integrating circuits 51A, 51B,..., 51n.
5F shows the outputs of the FIFO circuits 52A, 52B,..., 52n provided corresponding to the integrating circuits 51A, 51B,..., 51n, for example, (n, 0) is the same length. The FIFO output of the DCT block of “0” in the conversion unit “n” is shown. FIG. 5G shows the target code length determination data D54A of the target code length determination circuit 54. For example, (n, 0) is the determination data for the DCT block “0” in the equalization unit “n”. Indicates.
FIG. 5H shows the output of the FIFO circuit 22 provided in the main line system. For example, (n, 0) shows the FIFO output of the DCT block of “0” in the equalization unit “n”.
[0040]
FIG. 5I shows a search output of the binary search circuit 60, that is, a quantization control signal CONT60 representing a quantization index obtained in units of macroblocks. For example, (n−1, 0) is an equalization unit “ The quantization index of the DCT block “0” of “n−1” is shown. However, in this embodiment, a quantization index that satisfies the target code length is obtained for each macroblock.
FIG. 5J shows the quantized output (quantized level data D6) of the quantizer 6 provided in the main line system. For example, (n−1, 0) represents “n−1” of the equal length unit “n−1”. The quantized output of the DCT block of No. 0 is shown.
FIG. 5K shows the variable-length encoded output (bit stream) D7 of the variable-length encoder 7. For example, (n−1, 0) is the number “0” of the equal-length unit “n−1”. The variable length encoded output of the DCT block is shown.
[0041]
In the above configuration, the image signal encoding device 20 has a complex image portion and a flat image portion in one screen, for example, by scanning the input image signal in units of macroblocks in the scan conversion / shuffling circuit 21. Even in this case, an average screen is formed by shuffling.
[0042]
By forming an equal length unit by a predetermined number of macro blocks from among a plurality of macro blocks forming such a screen, the code length obtained by integrating each equal length unit is equal to one screen. It can be regarded as a code length in which the code length is equally distributed.
[0043]
Accordingly, by obtaining a quantization index for the equal length unit to be a predetermined target code length tgt and quantizing with the quantization index, the code amount of one screen (one frame) becomes the target amount. The main system is quantized with such a quantization index.
[0044]
By performing such code amount control in equal length units, for example, the FIFO circuits 52A to 52n provided in the prediction system may be prepared with a capacity corresponding to one equal length unit, and the integration circuit 51A. Similarly, the circuit scale can be processed in the same isometric unit in .about.51n, and the circuit configuration is much smaller than in the case of processing in one frame.
[0045]
Further, the activity detection circuit 50 detects the activity of the macroblock in the equal length unit, and by this, the quantization step of the quantizer 26 of the prediction system is locally switched in units of the macro block, so that the equal length is obtained. The target code length for each macroblock is determined by the quantization level corresponding to the density of the local image included in the unit. Therefore, the image quality of the decoded image in the main line system can be further improved.
[0046]
Incidentally, the equal length units formed by shuffling include on the screen macroblocks on average, so there is no activity bias for each equal length unit, and so on. The code length of the lengthening unit is the same. Therefore, the integrated value (tgt) for each equal length unit which is a target when the target code length of the macro block is determined by the target code length determination circuit 54 is simply the code amount of one screen (one frame). The image of each equal length unit in one screen becomes a unit having the same pattern for such a target, and all the images in one screen are all allocated. Only by determining the target code length for each macroblock corresponding to the target for the equal length unit, a decoded image corresponding to a local coarse / fine change in one screen can be obtained.
[0047]
According to the above configuration, the uneven distribution of the screen density is taken into account with a smaller circuit configuration by shuffling in units of macroblocks and forming equal length units by a plurality of macroblocks. A high-quality decoded image can be obtained without any problem.
[0048]
In the above-described embodiment, a case is described in which the search is started from the first processing procedure (STEP 1) for obtaining the code amount of the point (q15) that bisects the quantization indexes q0 to q31 as the search method in the binary search circuit 60. However, the present invention is not limited to this, and the binary search process can be simplified using data already obtained by the target code length determination circuit 54 of the prediction system.
[0049]
That is, in FIG. 6 in which the same reference numerals are assigned to the parts corresponding to those in FIG. 1, the target code length determination circuit 54 includes the third quantizer j (j = 3) of the prediction system quantizer 26. It has been found that there is a quantization index capable of obtaining the target code length tgt between the quantization index q15 possessed by and the quantization index q23 possessed by the fourth quantizer j (j = 4).
[0050]
That is, in the target code length determination circuit 54, the target code length ll (i) of the macroblock i and min _j Since the quantization index q [j] satisfying (ll (i, q [j]) ≦ ll (i)) is obtained, by using this information, the range of the solution is q [j−1]. It can be seen that q [j]. Therefore, the target code length determination circuit 54 can obtain the target code length tgt in the binary search circuit 70 by sending the quantization indexes q15 and q23 to the binary search circuit 70 as the quantization index data D54B. The information that the quantization index is between the quantization indexes q15 and q23 is used.
[0051]
For example, from the relationship between the quantizer and the quantization index shown in FIG. 2, the solution range is 32 ranges from q0 to q31 in the search method in the binary search circuit 60 described above with reference to FIG. In the binary search circuit 70, eight ranges of q15 to q23 can be set. That is, the solution is in the range greater than q15 (= q [3]) and less than q23 (= q [4]).
[0052]
Therefore, the binary search circuit 70 may start processing from the third processing procedure (STEP 3) in the binary search circuit 60 of FIG. As a result, in the binary search circuit 70, the first processing procedure (STEP 1) and the second processing procedure (STEP 2) described above for the binary search circuit 60 in FIG. 1 can be omitted. The number x of STEP (x) is expressed by the following equation, where the difference in quantization index of the quantizer is DIF.
[Equation 3]

It becomes. Accordingly, the circuit scale of the FIFO circuit 73 provided corresponding to the binary search circuit 70 can be further reduced as compared with the FIFO circuit 53 described above with reference to FIG.
[0053]
Incidentally, FIG. 7 shows a timing chart when the bit stream D7 is completed using an equal length unit composed of 30 DCT blocks. FIG. 7A shows a detection output of the activity detection circuit 50, for example (n , 0) indicates the activity detection output of the DCT block of number “0” in the equalization unit “n”. However, in this embodiment, the activity is detected in units of macro blocks formed by six DCT blocks.
[0054]
FIG. 7B shows the DCT output (coefficient data D25) of the DCT processing unit 25. For example, (n, 0) shows the DCT output of the DCT block of “0” in the equal length unit “n”.
FIG. 7C shows the quantized output (quantized level data D26A, D26B,..., D26n) of the quantizer 26 (26A, 26B,..., 26n) provided in the prediction system. n, 0) indicates the quantized output of the DCT block of “0” in the equalization unit “n”.
7D shows the conversion output (code length data D27A, D27B,..., D27n) of the conversion circuit 27 (27A, 27B,..., 27n), for example, (n, 0) is an equal length unit. The conversion output of the DCT block of “n” “0” is shown.
[0055]
FIG. 7E shows the integrated output for each equal length unit of the integrating circuits 51A, 51B,..., 51n.
7F shows the outputs of the FIFO circuits 52A, 52B,..., 52n provided corresponding to the integrating circuits 51A, 51B,..., 51n, for example, (n, 0) is the same length. The FIFO output of the DCT block of “0” in the conversion unit “n” is shown. FIG. 7G shows target code length determination data D54A of the target code length determination circuit 54. For example, (n, 0) is determination data for the DCT block of “0” in the equalization unit “n”. Indicates.
FIG. 7H shows the output of the FIFO circuit 22 provided in the main line system. For example, (n, 0) shows the FIFO output of the DCT block of “0” in the equal length unit “n”.
[0056]
FIG. 7I shows a search output of the binary search circuit 70, that is, a quantization control signal CONT70 representing a quantization index obtained in units of macroblocks. For example, (n−1, 0) is an equalization unit “ The quantization index of the DCT block “0” of “n−1” is shown. However, in this embodiment, a quantization index that satisfies the target code length is obtained for each macroblock.
FIG. 7J shows the quantized output (quantized level data D6) of the quantizer 6 provided in the main line system. For example, (n−1, 0) is “ The quantized output of the DCT block of No. 0 is shown.
FIG. 7K shows the variable-length encoded output (bit stream) D7 of the variable-length encoder 7. For example, (n−1, 0) is the number “0” of the equal-length unit “n−1”. The variable length encoded output of the DCT block is shown.
[0057]
According to the timing chart of FIG. 7, the search method in the binary search circuit 70 requires fewer processing steps (STEP) than the binary search method described above with reference to FIG. 1, and therefore the output timing of the binary search output shown in FIG. Becomes faster.
[0058]
In the above-described embodiments, the case where DCT is used as a transform coding method has been described. However, the present invention is not limited to this, and various other types such as a wavelet transform, a Haar transform, or a KL transform can be used. A conversion technique can be used.
[0059]
In the above-described embodiments, the activity detection method in the activity circuit 50 has been described with respect to the case where the color saturation is examined for each macroblock. However, the present invention is not limited to this. For example, the low-frequency component of the DCT coefficient is used. And the distribution of its high-frequency components to detect whether the macroblock image is fine or flat, or by matching the macroblock image with the checker flag pattern. Various other methods such as checking the fineness of the image of the macroblock can be used.
[0060]
In the above-described embodiment, the case where the method by the linear approximation is used as the target code length prediction method in the target code length determination circuit 54 has been described. You may use approximation by the following function.
[0061]
In the above-described embodiment, the case where the shuffling is performed in units of macroblocks within one screen (one frame) is described. However, the present invention is not limited to this, and the shuffling (time axis) between different screens (frames) is described. (Shuffling in the direction) may be performed.
[0062]
In the above-described embodiments, the case where the bit rate is controlled to be maintained in one frame has been described. However, the present invention is not limited to this, and control is performed so as to maintain the bit rate in units larger or smaller than this. May be.
[0063]
In the above-described embodiment, the case where the 4: 2: 0 format macroblock structure is used has been described. However, the present invention is not limited to this. For example, the 4: 2: 2 format, 4: 4: 4 format, or Various format macroblocks such as 4: 1: 1 format may be used. Further, there is no limit on the number of DCT blocks constituting the macro block.
[0064]
In the above-described embodiment, the case where the activity is detected for the data before the DCT processing is described. However, the present invention is not limited to this, and the activity detection is performed for the data after the DCT processing. You may do it.
[0065]
In the above embodiment, the case where the present invention is applied to the VTR image signal encoding method and image signal encoding apparatus has been described. However, the present invention is not limited to this. For example, a magneto-optical recording disk or a hard disk When recording on a recording medium, the present invention can also be applied to an image signal encoding method and an image signal encoding apparatus of a communication system that does not use a recording medium.
[0066]
【The invention's effect】
As described above, according to the present invention, the equalization unit is formed by shuffling the image signal in units of blocks and collecting the blocks forming the average screen. Each code length of a plurality of quantized outputs obtained by quantizing block unit data constituting an equal length unit in each of a plurality of quantization steps is integrated for each equal length unit. Among the integrated values of, linear approximation between the two integrated values closest to the target code length in the equal length unit, Allocating a target code length in block units that satisfies the desired bit rate, determining a quantization step that satisfies the target code length in the allocated block unit, and quantizing the data in block units by the quantization step Controls the amount of generated code for one screen to a predetermined bit rate based on the code length However, even when there is a pattern density that varies locally in the screen, the image quality of the decoded image can be avoided, and thus The code amount control of the feed forward method adapted to the local nature of the image can be realized with a smaller circuit configuration.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of an image signal encoding apparatus according to the present invention.
FIG. 2 is a chart showing quantization index assignment of a quantizer.
FIG. 3 is a graph showing integrated values for a quantizer and one equal length unit;
FIG. 4 is a graph for explaining a binary search method;
FIG. 5 is a timing chart showing an image signal encoding process according to the present invention.
FIG. 6 is a block diagram showing an image signal encoding apparatus according to another embodiment.
FIG. 7 is a timing chart showing an image signal encoding process according to another embodiment.
FIG. 8 is a block diagram showing a conventional image signal encoding apparatus.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 20 ... Image signal encoding device, 21 ... Scan conversion / shuffling circuit, 25 ... DCT processing part, 6, 26 ... Quantizer, 7 ... Variable length coding part, 8 ... Buffer circuit, 50 ... ... activity detection circuit, 51A to 51n ... integration circuit, 54 ... target code length determination circuit, 60, 70 ... binary search circuit.

Claims (6)

In a quantization method for predicting a quantization step in which an encoded image signal has a desired bit rate, and quantizing the image signal based on the prediction result,
Forming a predetermined equalization unit from an image portion composed of a plurality of the block units obtained as a result of the image signal being shuffled in a predetermined block unit;
The block unit data constituting the isometric unit is quantized by a plurality of quantization steps,
The respective code lengths of the plurality of quantized outputs quantized in the plurality of quantization steps are respectively integrated over the equal length unit, and the target in the equal length unit among the plurality of integrated values. A linear approximation is performed between the two integrated values closest to the code length, and a target code length in units of blocks that satisfies the desired bit rate is assigned,
Determining a quantization step satisfying the allocated target code length of the block unit;
The quantization method characterized in that the block unit data is quantized by the determined quantization step. The quantization method is
The complexity of image information is detected for the above-mentioned block unit data,
The quantization method according to claim 1, wherein the quantization step is switched in accordance with the complexity of the image information. In a quantization apparatus that predicts a quantization step in which an encoded image signal has a desired bit rate and quantizes the image signal based on the prediction result,
An equal length unit forming means for forming a predetermined equal length unit from a plurality of image portions composed of a plurality of block units obtained as a result of the image signal being shuffled in a predetermined block unit;
Prediction system quantization means for quantizing the block unit data constituting the equalization unit by a plurality of quantization steps;
The respective code lengths of the plurality of quantized outputs quantized in the plurality of quantization steps are respectively integrated over the equal length unit, and the target in the equal length unit among the plurality of integrated values. A target code length determining means for linearly approximating between the two integrated values closest to the code length and allocating the target code length in units of blocks satisfying a desired bit rate;
Quantization step determining means for determining a quantization step that satisfies the allocated target code length of the block unit;
And a quantization means for quantizing the block unit data by the quantization step determined by the quantization step determining means. The quantizer is
Detecting means for detecting the complexity of the image information for the block-unit data;
The quantization apparatus according to claim 3 , wherein the quantization step by the quantization means is switched in accordance with the complexity of the image information which is a detection result of the detection means. In a quantization step determining method for predicting a quantization step in which an encoded image signal has a desired bit rate and determining a quantization step for quantizing the image signal based on the prediction result,
Forming a predetermined equalization unit from an image portion composed of a plurality of the block units obtained as a result of the image signal being shuffled in a predetermined block unit;
The block unit data constituting the isometric unit is quantized by a plurality of quantization steps,
The respective code lengths of the plurality of quantized outputs quantized in the plurality of quantization steps are respectively integrated over the equal length unit, and the target in the equal length unit among the plurality of integrated values. A linear approximation is performed between the two integrated values closest to the code length, and a target code length in units of blocks that satisfies the desired bit rate is assigned,
A method for determining a quantization step, comprising: determining a quantization step that satisfies a target code length of the allocated block unit. In a quantization step determining apparatus that predicts a quantization step in which an encoded image signal has a desired bit rate and determines a quantization step to quantize the image signal based on the prediction result.
An equal length unit forming means for forming a predetermined equal length unit from a plurality of image portions composed of a plurality of block units obtained as a result of the image signal being shuffled in a predetermined block unit;
Prediction system quantization means for quantizing the block unit data constituting the equalization unit by a plurality of quantization steps;
The respective code lengths of the plurality of quantized outputs quantized in the plurality of quantization steps are respectively integrated over the equal length unit, and the target in the equal length unit among the plurality of integrated values. A target code length determining means for linearly approximating between the two integrated values closest to the code length and allocating the target code length in units of blocks satisfying a desired bit rate;
A quantization step determining means for determining a quantization step satisfying the allocated target code length of the block unit;

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