JPH09252430A - Flicker reduction circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the flicker on a character display area and to improve the resolution of other area where flicker is less eminent than the character display area. SOLUTION: A data processing section 10 generates data used to decode received data, to overlap character data and graphic data and to display the resulting data onto a display screen and detects a character area on which the character data are displayed. A vertical direction low-pass filter 14 passes a low frequency component of a spatial frequency of noninterlace system data outputted from a display processing section 13 in the vertical direction of the screen. A character area discrimination section '18 discriminates the character area based on character area information detected by the data processing section 10 and allows a changeover switch 16 to select output data of the vertical direction low pass filter 14 for the data of the area discriminated to be the character area and to select output data of a delay device 15 for the data of the area discriminated to be other than the character area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flicker reduction circuit, and more particularly to a flicker reduction circuit for a terminal device that superimposes character data and graphic data on a display unit.

[0002]

2. Description of the Related Art FIG. 11 is a block diagram showing an example of a terminal device to which an example of a conventional flicker reduction circuit is applied. In the figure, the line control unit 62 sends character data and graphic data which are transmitted from a higher-level device (not shown) in an interactive manner with the interactive device 61 and which are encoded by a predetermined encoding method.
The data is supplied to the data processing unit 60 via and is decoded here, and then supplied to the display processing unit 63. The display processing unit 63 performs processing for displaying the input decoded data, and inputs the decoded data to the interlace conversion unit 65 via the vertical low-pass filter 64 in a non-interlaced manner. The vertical low-pass filter 64 is a filter that passes low-frequency components of the spatial frequency in the vertical direction of the screen.

The interlace converter 65 converts the non-interlaced decoded data into data displayed in 2: 1 interlace and supplies the data to the NTSC encoder 66. The NTSC encoder 66 balance-modulates the color signal of the input character data and the decoded data of the graphic data, performs band sharing multiplexing on the high frequency region of the luminance signal, and performs N-band multiplexing.
It is converted into a composite signal conforming to the TSC system and supplied to the display unit 67 to display in color on the screen.

As is well known, in the display section 67 for displaying in the 2: 1 interlaced display system, each scanning line is refreshed every frame period (for example, 30 seconds), so that each scanning line is refreshed. Bright spots are flicker
Is generated. However, adjacent scanning lines actually overlap each other, and in the NTSC television system, when the luminance of the scanning line of one of the two adjacent scanning lines becomes the lowest, the scanning of the other field is performed. Since the frequency relationship is set so that the luminance of the line is the highest, the mutual luminance is interpolated, and the occurrence of flicker is not so noticeable. However, in the case of a single horizontal line, there is no bright spot on an adjacent scanning line, so that flicker is noticeable. The horizontal single line is particularly large in the character, and the character often has little correlation with the adjacent scanning line, so that the character is noticeably flickered.
Therefore, in the terminal device of FIG. 11, in order to reduce flicker that occurs when displaying characters, a vertical low-pass filter 64 is provided to remove high-frequency components in the vertical direction.

[0005]

In the above conventional circuit,
All data to be displayed such as graphic data other than character data is input to the vertical low-pass filter 64, and the high frequency component of the vertical spatial frequency is removed. But,
Since graphic data other than characters generally have a correlation with adjacent scanning lines, the brightness of the bright spots of the adjacent scanning lines are interpolated with each other as described above, and the occurrence of flicker is not so noticeable. Rather, in the case of graphic data other than characters, the vertical low-pass filter 64 removes the high-frequency component in the vertical direction, so that the resolution of the image in the vertical direction deteriorates.

[0006] The present invention has been made in view of the above points,
An object of the present invention is to provide a flicker reduction circuit that can reduce flicker in the character display area and improve the resolution in areas other than the character display area.

[0007]

In order to achieve the above-mentioned object, the present invention decodes input data, generates character data and graphic data, and generates data for displaying on a display surface of a display. , A data processing unit that detects a character area in which character data is displayed, a display processing unit that outputs the output data of the data processing unit as non-interlaced display format data, and a space in the screen vertical direction of the output data of the display processing unit A vertical low-pass filter that passes the low-frequency component of the frequency, and the character area is determined based on the character area information detected by the data processing unit, and the data in the area determined to be the character area is output from the vertical low-pass filter. Selecting means for selecting the output data of the display processing unit, and selecting the data of the area determined to be an area other than the character area. The data selected by the step 2: 1
The configuration has an interlace conversion unit for converting the data to the interlaced display system and an encoder for converting the output data of the interlace conversion unit to a video signal of a predetermined television system.

According to the present invention, when the input character data and graphic data are displayed in an overlapping manner, the output data of the vertical low-pass filter is selected in the character data area and the vertical low-pass filter is selected in the area other than the character data. Since the output data of the display processing unit, which is the input data of, is selected, the data that has not passed the vertical low-pass filter in the area other than the character area is converted into the video signal and then displayed by the display unit. .

[0009]

Next, an embodiment of the present invention will be described. FIG. 1 is a block diagram showing the configuration of a terminal device provided with an embodiment of a flicker reduction circuit according to the present invention. As shown in the figure, the data processing unit 10, the dialogue device 11, the line control unit 12, the display processing unit 13, the vertical direction low-pass filter 14, the delay device 15, the changeover switch 16, the descriptor 17, the character area determination unit 18, the interlace. It is composed of a conversion unit 19, an NTSC decoder 20, and a display unit 21.

The line control unit 12 is connected to an information center (not shown) via a telephone line 22, and performs interactive data communication with the interactive device 11. Display unit 21 of this device
Then, as shown in FIG. 2, the character information frame 30 and the graphic information frame 31 are overlapped with each other to display the display surface 3
2 is displayed.

Next, the operation of this embodiment will be described. In the figure, received data such as character data and graphic data encoded by different encoding systems and input to the data processing unit 10 through the telephone line 22 and the line control unit 12 are decoded here, It is input to the display processing unit 13 as data displayed on the display surface of the display after being superimposed as shown in FIG.

As shown in FIG. 3, the display processing unit 13 supplies the input data to the vertical low-pass filter 14 and the delay unit 15 as non-interlaced data which is sequentially scanned from the upper part to the lower part of the screen.

The vertical low-pass filter 14 is shown in FIG.
Similarly to the vertical low-pass filter 64, it is a known filter that passes low-frequency components of a predetermined frequency or less among spatial frequency components in the vertical direction of the screen. The delay device 15 delays the input data by the same time as the delay time due to the processing operation by the vertical low-pass filter 14 and adjusts the time with the output data of the vertical low-pass filter 14.

On the other hand, in parallel with the above decoding of the input data, the data processing unit 10 detects a rectangular area 40 in which character data is displayed in one screen, as shown in FIG. Information on the start point 41 and the end point 42 is obtained. As shown in FIG. 5, the data processing unit 10 considers the display surface of the display in a coordinate system in which the horizontal direction is the X axis and the vertical direction is the Y axis.
1 coordinate (X _s , Y _s ), start point 42 coordinate (X _e , Y
_e ) are collectively output (X _s , Y _s , X _e , Y _e ) to the descriptor 17 in the ascending order of X _s . Descriptor 1
7 stores the input coordinate data and supplies it to the character area determination unit 18.

FIG. 6 is a block diagram showing an example of the character area determining section 18. The character area determination unit 18 is used by the sequencer 5
0, a selector 51, line memories 52, 53 and 54, and a selector 55. The coordinate data input via the input terminal I is supplied to the sequencer 50. The sequencer 50 controls the selectors 51 and 55 based on the input coordinate data according to the flowchart shown in FIG.

That is, first, the input top coordinate data (X _s , Y _s , X _e , Y _e ) is read (step 6).
1) Among them, it is judged whether or not the Y coordinate value Y _{s of the} starting point is larger than the screen size (step 62), and if it is within the screen size, the current line (scan line) is the Y coordinate value Y of the starting point of the rectangular area. It is determined whether the line is between _s and the Y coordinate value Y _e of the end point (step 63).

When the current line is a line between Y _s and Y _e , that is, a line in a rectangular area, a flag is set between the X coordinate value X _{s at the} start point and the X coordinate value X _e at the end point. (Step 64). Then, the next coordinate data (X _s , Y _s , X _e , Y _e ) is read (step 65),
The process returns to step 62. If it is determined in step 62 that it is larger than the screen size, it cannot be displayed on the display screen, and if it is determined in step 63 that the current line is not within the rectangular area, data other than characters is displayed. Immediately end the processing.

Further, the sequencer 5 of the character area determination unit 18
0 is the selectors 51 and 52 based on the above processing result.
And controls the first line memory 52 as shown in FIG.
Is cleared, the above flag is written to the second line memory 53 through the selector 51, and the third line memory 5
The flag already written in 4 is read out and output via the selector 55 (step 71).

Next, the flag is written to the first line memory 52 through the selector 51, and the second line memory 5
The previously written flag is read from 3 and output through the selector 55 to clear the third line memory 54 (step 72). Subsequently, the sequencer 50 reads the previously written flag from the first line memory 52, outputs it through the selector 55, clears the second line memory 53, and causes the third line memory 54 to read the next line. Write the flag (step 73). Then, the process returns to step 71 again. In this way, the above operation is cyclically repeated for each line. The output flag of the selector 55 is applied to the changeover switch 16 of FIG. 1 as a changeover signal.

Referring back to FIG. 1 again, the changeover switch 16 selects the output data of the vertical low-pass filter 14 during the period when the flag is output from the character area determination unit 18, and during the period when the flag is not output. The output data of the delay device 15 is selected. That is, the change-over switch 16 selects the character data output from the vertical low-pass filter 14 in the character area, and selects the output data of the delay device 15 that has not passed through the vertical low-pass filter 14 in the area other than the character area.

The interlace conversion unit 19 is the data in which the character data or the graphic data input from the changeover switch is displayed by the non-interlaced display system shown in FIG. 3, and the display system of the display screen of the display unit is shown in FIG.
Since the 2: 1 interlace display system in which the scan of the first field shown in FIG. 10 and the scan of the second field shown in FIG. 10 are alternately repeated, the input data is converted into the data of the 2: 1 interlace display system.

The output data of the interlace conversion unit 19 is supplied to the NTSC encoder 20. Among the decoded data of the character data and the graphic data input here, the color signal is balanced-modulated and banded in the high frequency region of the luminance signal. It is shared and multiplexed, converted into a composite signal conforming to the NTSC system, supplied to the display unit 21, and displayed in color on the screen. In this display image, the character image in the character area has flicker reduced by removing the high frequency component of the vertical spatial frequency by the vertical low-pass filter 14, and the image other than the character area has the above vertical spatial frequency. Since the high frequency component of is displayed without being removed, the resolution is improved as compared with the conventional case.

The present invention is not limited to the above-mentioned embodiment, and is encoded into a television system for displaying in another 2: 1 interlace display system such as PAL system other than NTSC system. Of course, it may be displayed on a display unit adapted to it.

[0024]

As described above, according to the present invention,
When superimposing the input character data and graphic data, etc., select the output data of the vertical low-pass filter in the character data area, and display processing that is the input data of the vertical low-pass filter in the area other than the character data. By selecting the output data of the unit, the data that has not passed the vertical low-pass filter in the area other than the character area is converted to the video signal and then displayed on the display unit. A character image with reduced flicker can be displayed by passing through the filter, and a graphic image with improved resolution can be displayed by not passing through the vertical low-pass filter in an area other than the character area.

[Brief description of drawings]

FIG. 1 is a block diagram when an embodiment of the present invention is applied to a terminal device.

FIG. 2 is a diagram illustrating a display method of character information and graphic information.

FIG. 3 is an explanatory diagram of a non-interlaced display method.

FIG. 4 is an explanatory diagram of a character area.

FIG. 5 is a diagram illustrating a coordinate system on a display screen.

6 is a block diagram of an example of a character area determination unit in FIG.

7 is a flowchart for explaining the operation of FIG.

FIG. 8 is an operation explanatory diagram of FIG. 6;

FIG. 9 is a diagram for explaining scanning of the first field in the 2: 1 interlace system.

FIG. 10 is an explanatory diagram of scanning of a second field in the 2: 1 interlace system.

FIG. 11 is a block diagram in which a conventional example is applied to a terminal device.

[Explanation of symbols]

 10 data processing unit 11 interactive device 12 line control unit 13 display processing unit 14 vertical low-pass filter 15 delay device 16 changeover switch 17 descriptor 18 character area determination unit 19 interlace conversion unit 20 NTSC encoder 21 display unit 22 telephone line

Claims (3)

[Claims] 1. A data processing unit for decoding input data to generate data for displaying on a display surface of a display by superimposing character data and graphic data, and detecting a character area in which the character data is displayed. A display processing unit that outputs the output data of the data processing unit as data of a non-interlaced display system; and a vertical low-pass filter that passes the low-frequency component of the spatial frequency in the screen vertical direction of the output data of the display processing unit. The character area is determined based on the character area information detected by the data processing unit, and the data of the area determined to be the character area is selected from the output data of the vertical low-pass filter, and the area other than the character area is selected. The data of the area determined to be selected is selected by the selecting unit that selects the output data of the display processing unit and the selecting unit. Data 2: 1 interlaced converter for converting the data of the interlaced display mode, the flicker reduction circuit and having an encoder for converting the output data of the interlace converting unit into a video signal of a predetermined television system. 2. The selecting means includes a descriptor for storing character area information detected by the data processing section, a character area determining section for determining a character area from output character area information of the descriptor, and the character area determining section. 2. The flicker reduction circuit according to claim 1, comprising a changeover switch for selecting one of the output data of the vertical low-pass filter and the output data of the display processing unit based on an output flag of the unit. 3. The character area determination unit determines whether the character area can be displayed on the screen based on the output character area information of the descriptor, and outputs a flag according to the presence or absence of the character area, and the first to third sections. Line memory and the first
To the third line memory are provided on the input side and the output side, respectively, and the first to third line memories are respectively cleared, the flag is written, and the written flag is read in a cyclic manner. The flicker reduction circuit according to claim 2, comprising first and second selectors that select based on the output of the sequencer.