JPH09252225A - Bias circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a simple and general-purpose bias circuit having a current compensation function. SOLUTION: This circuit is provided with a source follower circuit 20 driven by 1st and 2nd power supplies Vd, Vss and receiving a reference potential Vref at its input terminal, a monitor transistor(TR) 2 whose source connects to an output terminal of the source follower circuit 20, a 1st level shift element 30 whose one terminal connects to the 1st power supply Vd and whose other terminal. connects to a drain of the monitor TR 2, and a level conversion circuit 40 provided between th drain and the gate of the monitor TR 2. In this case, the current flowing to the monitor TR 2 is configured to be smaller than the current flowing to the source follower circuit 20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bias circuit, and particularly to a high frequency amplifier.

[0002]

Bias circuits for supplying a gate bias to the gate electrodes of transistors are widely used in semiconductor integrated circuits and analog circuits. A first example of a conventional bias circuit is shown in FIG. The bias circuit shown in FIG. 8 is composed of resistors 81 and 82 connected in series, and supplies a voltage obtained by dividing the power supply voltage V _d by the resistors 81 and 82 to the gate of the transistor 65.

However, when a gate bias is supplied to a constant current source or an amplifier, the drain current I _d is generally (V
Proportional to the square of the _GS -V _th), against a threshold variation △ V _th arising from manufacturing variations of the transistor,
The current variation ΔI _d is proportional to | ΔV _th | ² . For this reason, when the bias circuit shown in FIG. 8 is used, there is a problem in that variations in current are extremely large due to variations in manufacturing of transistors, and yield is deteriorated.

From such a background, a bias circuit having a current compensation function has been required. The bias circuit having the current compensation function described here is a circuit for maintaining (V _GS −V _th ) closer to a constant value, that is, for maintaining the drain current of the transistor 65 at a desired value, and therefore, the threshold value. It is a circuit having a function of automatically adjusting the output potential V _GS so as to cancel the value variation.

FIG. 9 shows an example of a conventional bias circuit having a current compensation function. The bias circuit shown in FIG. 9 is
Resistors 91, 93, 94, 95, 97 and transistor 9
2, 96, which is suitable when the source of the target transistor 65 is connected to the power supply V _ss via the resistor 67, for example, ECL (Emitter Coupled Logic)
It is widely used in digital circuits such as and SCFL (Source Coupled FET Logic).

However, since the bias circuit shown in FIG. 9 generates a bias based on the resistors 91, 93, 95 and 97, a predetermined drain current can be obtained when the resistance values of the resistors vary. There is a problem of not having.
Further, it is not suitable for application to a source-grounded transistor such as an amplifier that does not use the source resistor 67.

Another example of a conventional bias circuit having a current compensation function is shown in FIG. The bias circuit shown in FIG. 10 has a resistor 101, and an F connected directly between a gate and a drain.
It has a current mirror configuration including an ET transistor 102 and is suitable for a gate bias circuit of a source-grounded transistor 65 such as an amplifier. As an example of using the bias circuit of the current mirror configuration shown in FIG. 10 in a high frequency amplifier, E. Heaney et al; GaAs IC Symposium, pp49
~ 51, 1993 and Y. Murakami et al; 1994 Asia Pasitic M
It is disclosed in icrowave Conf.WS5-1. The former is EFE
A bias circuit is configured using a T (Enhancement type Field Effect Transistor), and this bias circuit is used for a low noise amplifier. The latter is a JFET (Junction).
A bias circuit is configured using a type field effect transistor), and this bias circuit is used for a low noise amplifier.

However, a drawback of such a bias circuit having a current mirror structure is that the transistor is EFE.
It is a necessary condition to be T, and DFET (Depletion
cannot be used in typeField Effect Transistor), and therefore the applications that can be used are extremely limited. Because in high frequency amplifiers, especially power amplifiers, D
This is because the FET is widely used.

[0009]

As described above, since a simple and versatile bias circuit that can be used for a source-grounded DFET has not been available, the problem of current variation in a power amplifier is high. Was the most serious problem in improving. Conventionally, hand trimming has been used as a countermeasure against this problem. The problem of current variation will be specifically described. For example, a power FET (0.6 μm G
In the case where a prototype is made with aas MESFET) as the center of design, variations in threshold value actually occur in the wafer surface,
For example, when the threshold value becomes 0.1 V deeper than the design center, the drain current becomes 380 mA under the same bias condition, and the current value becomes 1.5 times or more the design value, which is a very large variation.

Trimming has been conventionally performed as a countermeasure against such a problem. What is current trimming?
The purpose is to adjust the above-mentioned current variation to a desired current value in the module process (process before packaging) after the wafer process. As a specific example of trimming, a method of providing a gate bias generation circuit of an FET by resistance division on a module and changing a resistance value by laser trimming to adjust to a desired bias potential, or
Prepare a dummy pattern of the resistor inside or outside the chip so that several kinds of bias are given in advance,
There is a method of changing a resistance division ratio by changing a bonding position to adjust a desired bias potential, or a method of replacing a chip component such as a resistor. However, since each of them is a manual work while monitoring the current value of each IC, there is a problem that it is time-consuming and labor-intensive, and the cost performance thereof is poor and it is not suitable for mass production.

The present invention has been made in consideration of the above circumstances, and has a current compensation function capable of keeping the drain current constant even when the characteristics of the target transistor are changed, and the DFET or EFET is also provided. It is an object of the present invention to provide a bias circuit that is simple and versatile without depending on it.

[0012]

[Means for Solving the Problems]

[Outline] A first aspect of a bias circuit according to the present invention is a source follower circuit driven by first and second power supplies and receiving a reference potential at an input end, and a source end connected to an output end of the source follower circuit. Provided between a monitoring transistor, a first level shift element having one end connected to the first power source and the other end connected to the drain of the monitoring transistor, and the drain and gate of the monitoring transistor. And a level conversion circuit
The current flowing through the monitoring transistor is smaller than the current flowing through the source follower circuit.

A second aspect of the bias circuit according to the present invention is the bias circuit of the first aspect, wherein a second level shift element having one end connected to the first power supply and an anode having the second level shift element are provided. A diode connected to the other end of the level shift element and having a cathode connected to a third power supply;
Voltage dividing means for dividing the voltage between the anode and the cathode of the diode, and further comprising a reference voltage generating circuit whose output is the reference potential.

A third aspect of the bias circuit according to the present invention is the bias circuit according to the first or second aspect, further comprising: a first capacitor for coupling an input terminal of the source follower circuit and a ground power source; A second capacitor for coupling the source of the transistor and the ground power supply, and a resistor provided between the gate of the monitoring transistor and the other end of the level conversion circuit are further provided. And

A fourth aspect of the bias circuit according to the present invention is characterized in that, in the bias circuit of the first aspect, the impedance value on the output side of the source follower circuit is set higher than the impedance value of the source follower circuit. And

[Operation] In the bias circuit of the present invention configured as described above, a transistor to which a gate bias is applied (hereinafter, simply referred to as a transistor) is denoted by D.
Consider a case where the FET is used and the threshold voltage shifts to the plus side of the design value due to manufacturing variations. Then, the threshold voltage of the monitor transistor also shifts to the positive side. Since a constant output voltage is applied from the source follower circuit to the source of the monitor transistor, the threshold voltage of the monitor transistor shifts to the plus side of the design value, and thus the gate voltage V that is the design value. _B
Even if is applied, the current I _db flowing through the monitor transistor becomes smaller than the design value I _dbo . Then, the voltage drop due to the level shift element becomes small, and the potential at the drain end of the monitoring transistor rises, which also raises the potential applied to the gate of the monitoring transistor via the level conversion circuit, and Current I
_db also rises. And this rise continues until it reaches the design value I _dbo . As a result, the gate potential of the transistor also rises, and a predetermined current (design value) flows through the transistor.

Further, when the threshold voltage of the transistor shifts to the negative side from the design value, the threshold voltage of the monitor transistor also shifts to the negative side. At this time, if the gate voltage V _B , which is the design value, is applied, the design value I
_A larger current than _dbo flows through the monitor transistor,
As a result, the potential at the drain end of the monitor transistor drops. Then, the gate potential of the monitor transistor drops, and the current I _db flowing through the monitor transistor also drops. Then, the decrease of the current continues until the design value I _dbo is reached. As a result, the current flowing through the transistor also becomes the design value.

As described above, the bias circuit according to the present invention has a current compensation function.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a bias circuit according to the present invention will be described with reference to the drawings. In the following embodiments, a transistor to which a gate bias is supplied is a depletion type GaAs MESFET (Metal).
Semiconductor Field Effect Transistor).

The configuration of the first embodiment of the bias circuit according to the present invention is shown in FIG. The bias circuit 1 of this embodiment includes a monitoring transistor 2, a source follower circuit 20, a level shift element 30 for shifting the drain potential of the monitoring transistor, and a level for converting the gate potential of the monitoring transistor to a predetermined level. Conversion circuit 4
0, and the drain is connected to the power source V via the load 60.
_The gate bias is supplied to the transistor 65 of the main body circuit portion 61 which is connected to _d and whose source is grounded.

The transistor 2 has the same structure as the transistor 65 to which the gate bias is supplied and is manufactured by the same process. Therefore, the transistor 65
When the threshold characteristic of 1 changes, the characteristic of the transistor 2 also changes. That is, the transistor 2 serves as a monitor element for the transistor 65. However, the total gate width of the transistor 2 is generally set smaller than that of the transistor 65.

The source follower circuit 20 is driven by the high power source V _d and the low power source V _ss , the reference potential is applied to the input terminal, and the output terminal of the source follower circuit is the transistor 2.
Connected to the source terminal of.

The level shift element 30 has a high power source V at one end.
_It is connected to _d and the other end is connected to the drain of the transistor 2 to adjust the potential of the drain terminal of the transistor 2. The level conversion circuit 40 has one end connected to the drain terminal of the transistor 2 and the other end connected to the gate terminal of the transistor 2, and changes the potential level of the gate terminal of the transistor 2 according to the potential of the drain terminal of the transistor 2. Is.

The gate terminal of the transistor 2 is connected to the gate terminal of the transistor 65 of the main body circuit section in a direct current manner. Then, in the bias circuit of the present embodiment, the current flowing through the level shift element 30, that is, the drain current I _db flowing through the transistor 2 is smaller than the current I _da flowing through the source follower circuit 20 than the impedance value of the source follower circuit. The impedance value on the output side as seen from the output end of the source follower circuit is set high.

The operation of the bias circuit of this embodiment set as described above will be described. Now the transistor 65 is D
Consider a case where the FET is used and the threshold voltage shifts to the plus side of the design value due to manufacturing variations. Then, the threshold voltages of the monitoring element transistor 2 also shifts to the plus side, thereby characteristic graph also changes from a characteristic graph g _o the design values shown in FIG. 2 to the characteristic graph g _1. Since a constant output voltage is applied to the source of the transistor 2 from the source follower circuit 20, the characteristic of the transistor 2 has become g ₁ , so that even if the gate voltage V _B that is the design value is applied, The electric current I _db flowing through is smaller than the design value I _dbo . Then, the voltage drop due to the level shift element 30 becomes small, and the potential at the drain end of the transistor 2 rises, so that the potential applied to the gate of the transistor 2 via the level conversion circuit 40 also rises and flows through the transistor 2. The current I _db also rises. And this rise continues until it reaches the design value I _dbo . As a result, the gate potential of the transistor 65 also rises, and a predetermined current (design value) flows through the transistor 65. At this time, the gate-source voltage of the transistor 2 becomes V _A.

Further, if the threshold voltage of the transistor 65 is shifted to the negative side than the design value, the characteristics of the transistor 2 changes from the characteristic graph g _o the characteristic graph g _2. At this time, when the gate voltage V _B , which is the designed value, is applied, a current larger than the designed value I _dbo flows through the transistor 2 and the potential at the drain end of the transistor 2 drops. Then, the gate potential of the transistor 2 drops, and the current I _db flowing through the transistor 2 also drops. Then, this decrease of the current continues until it reaches the design value I _dbo, and ends when the gate potential reaches V _c . As a result, the current flowing through the transistor 65 also becomes the design value.

As described above, the bias circuit of the above embodiment has a current compensation function. In addition,
In the bias circuit of the above embodiment, the current flowing through the transistor 2 is set to be smaller than the current flowing through the source follower circuit 20, but if this condition is not satisfied, the transistor 2 and the source follower circuit 20 are configured. Therefore, the above-mentioned current compensation function is not provided.

Further, in the bias circuit of the above-mentioned embodiment, since the drain end and the gate of the transistor 2 are connected through the level conversion circuit 40, the transistor 65 can be used even if it is an EFET or DFET. It will be possible and versatile.

Next, the configuration of the second embodiment of the bias circuit according to the present invention is shown in FIG. The bias circuit of the second embodiment is the same as the bias circuit of the first embodiment shown in FIG. 1, _except that the reference voltage V _vef input to the input terminal of the source follower circuit 20 is generated from the reference voltage generation circuit 10. It is a thing. The reference voltage generating circuit 10 includes resistors 12 and 1 connected in series between a power source V _d and a ground power source.
4 and 15 and resistors 14 and 15 connected in series, and a diode 13 connected in parallel. The reference voltage to the source follower circuit 20 is taken out from the common connection point of the resistors 14 and 15.

In the bias circuit of the second embodiment, since the reference voltage V _vef input to the input end of the source follower circuit 20 is based on the cathode-anode voltage of the diode 13, the power supply voltage V _d It is less affected by variations in resistance and resistance. It goes without saying that the bias circuit of the second embodiment also has the same effect as the bias circuit of the first embodiment.

In the bias circuit of the above embodiment, since the drain end of the transistor 2 and the gate are connected via the level conversion circuit 40, the transistor 65 can be used even if it is an EFET or DFET. It will be possible and versatile.

The configuration of the third embodiment of the bias circuit according to the present invention is shown in FIG. The bias circuit of this embodiment is the same as the bias circuit of the first embodiment shown in FIG. 1, except that decoupling capacitors 4 and 5 and a resistor 6 are used.
And are newly provided.

One end of the capacitor 4 is connected to the input terminal of the source follower circuit 20 to which the reference potential V _ref is input,
The other end is grounded. Further, one end of the capacitor 5 is connected to the output terminal of the source follower circuit 20, that is, the source end of the transistor 2, and the other end is grounded. The resistor 6 is provided between the connection point between the level conversion circuit 40 and the gate of the transistor 65 and the gate of the transistor 2.

These capacitors 4, 5 and resistor 6 are
When the transistor 65 is a high frequency amplifier, especially a power amplifier, a high frequency signal leaks to the bias circuit,
When AC-like noise is generated, it is used for attenuating the amplitude of this noise and for terminating high frequency components.
As a result, it is possible to prevent the bias circuit from malfunctioning due to AC noise, and stable operation can be performed.

Needless to say, the bias circuit of this embodiment also has the same effect as that of the first embodiment.

In the bias circuit of the above embodiment, since the drain end and the gate of the transistor 2 are connected through the level conversion circuit 40, the transistor 65 can be used even if it is an EFET or DFET. It will be possible and versatile.

FIG. 5 shows the configuration of the fourth embodiment of the bias circuit according to the present invention. The bias circuit of this embodiment is the same as the bias circuit of the second embodiment shown in FIG. 3, except that the source follower circuit 20 is composed of a diode 21 and transistors 22 and 23 connected in series, and a level conversion circuit 40. 41, diode 42 and transistor 4 connected in series
3 decoupling capacitors 4, 5, 5
2 and resistors 6 and 55 are newly provided. The level shift element 30 is composed of a resistor 30.

The capacitor 4 couples the output terminal of the reference voltage generating circuit 10 (the input terminal of the source follower circuit) with the ground power source, and the capacitor 5 couples the output terminal of the source follower circuit 20 with the ground power source, and the capacitor 52. Couples the output terminal of the level conversion circuit 40 and the ground power supply. The resistor 6 is provided between the gate of the monitoring transistor 2 and the output end of the level conversion circuit 40, and the resistor 55 is the output end of the level conversion circuit 40 and the transistor 65.
Between the gates.

These resistors 6 and 55 and the capacitor are
As described in the third embodiment, it is used to attenuate or terminate the amplitude of AC noise.

The reference potential V _ref which is the output of the reference voltage generating circuit 10 is applied to the gate of the transistor 22 of the source follower circuit 20. The output of the source follower circuit 20 is taken out from the source of the transistor 22. The gate and the source of the transistor 23 of the source follower circuit 20 are commonly connected and connected to the power supply V _ss .

The gate of the transistor 41, which is the input terminal of the level conversion circuit 40, is connected to the drain of the monitoring transistor 2, and the output is taken out from the cathode of the diode 42. The gate and the source of the transistor 43 are commonly connected and connected to the power supply V _ss .

The bias circuit of the fourth embodiment is
The same effect as the bias circuit of the second embodiment can be obtained, and AC noise can be attenuated or terminated, so that the bias circuit can be prevented from malfunctioning.

In the bias circuit of the above embodiment, since the drain end of the transistor 2 and the gate are connected via the level conversion circuit 40, the transistor 65 can be used even if it is an EFET or DFET. It will be possible and versatile.

The results of simulating the bias circuit of the fourth embodiment shown in FIG. 5 with the circuit simulator SPICE are shown in FIGS. 6 and 7. Here V
_{d = 3V, V ss = -2V} , is set to GND = 0V. FIG. 6 shows the relationship between the output voltage of the bias circuit and the threshold voltage V _th of the transistor 65. From FIG. 6, even if the threshold voltage V _{th of the} transistor 65 changes, V _GS −V
It can be seen that _th is kept constant.

FIG. 7 shows the drain current of the transistor 65 when the threshold voltage V _{th of the} transistor (power FET) 65 is shifted ± 0.1 V from the design value with and without the bias circuit. Is. As can be seen from FIG. 7, the power F is better when there is a bias circuit.
It is possible to suppress variations in the drain current of the ET65.

In the bias circuit of the fourth embodiment shown in FIG. 5, the transistors 22 and 23 of the source follower circuit 20 may be replaced with a plurality of cascode-connected transistors. In this case, the diode 42 of the level conversion circuit 40 is replaced by a plurality of stages connected in series, and the transistor 43 is also replaced by a plurality of stages connected in cascode. By using the cascode-connected transistor in this manner, the source follower circuit 2
The current flowing through 0 can be stabilized.

In the bias circuits of the first to fourth embodiments, by increasing the impedance of the level shift element 30, the current flowing through the monitor transistor 2 is made smaller than the current flowing through the source follower circuit 20. However, the means for reducing the current flowing through the transistor 2 may be another means. For example, in the fourth embodiment shown in FIG. 5, the thresholds of the transistors 22 and 23 of the source follower circuit 20 may be changed with respect to the transistor 2.

In the above-described embodiments, the case where the transistor is a GaAs MESFET has been described, but a MOSFET, a bipolar transistor, and a transistor using a compound semiconductor heterojunction, such as HEMT or HBT, may be used.

Further, in the bias circuit of the above-mentioned embodiment, since the negative power source V _ss can be used, it can be used also in the digital circuit.

Further, in the bias circuit of the above-mentioned embodiment, the positive power supply and the negative power supply are assumed, but V _ss is GND.
Can be used in the case of a single power source with a positive power source.

[0051]

As described above, according to the present invention, it is possible to obtain a simple and versatile bias circuit which has a current guarantee function capable of keeping the drain current constant even when the characteristics of the transistor are changed. .

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a bias circuit according to the present invention.

FIG. 2 is a graph illustrating characteristics when a threshold voltage of a transistor shifts.

FIG. 3 is a block diagram showing a configuration of a second embodiment of a bias circuit according to the present invention.

FIG. 4 is a block diagram showing a configuration of a third embodiment of a bias circuit according to the present invention.

FIG. 5 is a circuit diagram showing a configuration of a bias circuit according to a fourth embodiment of the present invention.

6 is a graph showing a simulation result of the relationship between the threshold voltage and the output of the bias circuit in the bias circuit of the embodiment shown in FIG.

FIG. 7 is a graph showing changes in drain current when the threshold value is shifted in the embodiment shown in FIG. 5 with and without a bias circuit.

FIG. 8 is a circuit diagram showing a configuration of a conventional bias circuit.

FIG. 9 is a circuit diagram showing the configuration of another example of a conventional bias circuit.

FIG. 10 is a circuit diagram showing the configuration of still another example of the conventional bias circuit.

[Explanation of symbols]

 1 Bias Circuit 2 Transistor 4 Capacitor 5 Capacitor 6 Resistor 10 Reference Voltage Generating Circuit 12 Resistor 13 Diode 14 Resistor 15 Resistor 20 Source Follower Circuit 21 Diode 22 Transistor 23 Transistor 30 Level Shift Element 40 Level Converting Circuit 41 Transistor 42 Diode 43 Transistor 52 Capacitor 55 Resistance 60 Load 61 Body circuit 65 Transistor

Claims (4)

[Claims] 1. A source follower circuit driven by first and second power supplies and receiving a reference potential at an input terminal, a monitor transistor having a source terminal connected to an output terminal of the source follower circuit, and one end of the first follower circuit. And a level conversion circuit provided between the drain and the gate of the monitor transistor, the first level shift element having the other end connected to the power supply of the monitor transistor and the other end connected to the drain of the monitor transistor. The bias circuit is configured such that the current flowing through the monitor transistor is smaller than the current flowing through the source follower circuit. 2. A second level shift element having one end connected to the first power supply, an anode connected to the other end of the second level shift element, and a cathode connected to a third power supply. 7. A diode, and a voltage dividing means for dividing the voltage between the anode and the cathode of the diode, and a reference voltage generating circuit for providing an output of the voltage dividing means as the reference potential. 1. The bias circuit according to 1. 3. A first capacitor provided between an input terminal of the source follower circuit and a ground power source, and a second capacitor provided between a source of the monitoring transistor and the ground power source. 3. The bias circuit according to claim 1, further comprising: a resistor provided between the gate of the monitoring transistor and the other end of the level conversion circuit. 4. The bias circuit according to claim 1, wherein the impedance value on the output side from the source follower circuit is set higher than the impedance value of the source follower circuit.