JPH09252101A - Semiconductor light-receiving element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To precisely prevent the malfunction of a circuit owing to incident light even if light-shileindg layers are divided in a semiconductor light-receiving element. SOLUTION: The semiconductor light-receiving element having a light- receiving area for converting incident light into a corresponding electric signal and areas except for the pertinent light-receiving area is provided with the light-shielding layers 29a and 29b formed on the areas except for the light- receiving area. The light-shileding layers 29a and 29b are divided into plural areas and the respective areas cover at least well areas 15a and 15b provided for a semiconductor substrate. The light-shielding layers 29a and 29b can be constituted of plural light-shielding layers which are partially overlapped. Thus, the fluctuation of the well potential by the changes generated by light can be suppressed and the malfunction of the circuit can be prevented by fixing the potential of the semiconductor substrate or the wells 17 and 19.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light receiving element, and in particular, it is possible to appropriately prevent the adverse effect of incident light on a circuit element even when a light shielding layer covering a region other than the light receiving region is divided. Technology.

[0002]

2. Description of the Related Art FIG. 8 shows a schematic structure of a solid-state image pickup device as a typical example of a semiconductor light receiving device. The solid-state image sensor of the same figure is composed of a light receiving section 1 formed by arranging photoelectric conversion pixels in a two-dimensional plane, and a circuit provided around the light receiving section 1 other than the light receiving section. The circuits other than the light receiving section are composed of, for example, a vertical scanning circuit 3, a horizontal scanning circuit 5, a reset circuit 7, and the like.

The vertical scanning circuit 3 is for sequentially selecting pixels in a horizontal pixel column, that is, pixels in each row, and supplying a drive pulse having a required voltage level to each pixel. Horizontal scanning circuit 5
Is a circuit for sequentially outputting the signals of the pixels of each row selected by the vertical scanning circuit 3 to the outside of the element. Reset circuit 7
Is a vertical signal line of the light receiving unit 1, that is, a column line,
Is a circuit for resetting every time the pixels in each row are read out to return to the initial state. The structure and operation of such a solid-state image sensor are well known and will not be described further here.

In the solid-state image pickup device shown in FIG.
In order to prevent malfunction due to incident light in each peripheral circuit in the area other than the light receiving portion 1, and for the pixels on the outer peripheral portion of the light receiving portion 1 to serve as a reference for the black level, light shielding formed of metal such as aluminum is used. It is shielded by the layer 9. FIG.
In FIG. 4, such a light shielding layer 9 is shown as a region drawn by a dotted line.

The vertical scanning circuit 3 and the horizontal scanning circuit 5, etc. are usually constructed by using CMOS circuits in order to suppress power consumption. Although the configuration changes depending on the size of the circuit scale, as an example of the scanning circuit formed on the semiconductor substrate,
A schematic plan view of the vertical scanning circuit 3 is shown in FIG. Also,
A cross-sectional view taken along the line AA of FIG. 9 is shown in FIG.

In the structure shown in these figures, for example, an N ⁺ type buried layer 13 is formed on a P type semiconductor substrate 11, and an N type well 15 and a P type well 17 are formed inside the N ⁺ type buried layer 13. And 19 are formed respectively. The clock lines 23a and 23b are formed on the wells 15, 17 and 19 and the upper part of the semiconductor substrate 11 via the insulating layer 21 with the first aluminum layer and the same clock lines 23a and 23b.
The power supply lines 25a and 25b are formed of the aluminum layer as the second layer. In addition, the light shielding layer 29 is the second aluminum layer.
Or a power supply line (not shown) having a relatively wide line width is formed. Although the insulating layer 21 is illustrated as being formed as a single layer in the figure, in practice, for example, the first layer interlayer insulating film formed on the substrate 11 and each well 15, 17, 19 is illustrated. A second-layer interlayer insulating film formed on the first-layer aluminum insulating film formed on the first-layer interlayer insulating film; and a second-layer aluminum insulating film formed on the second-layer interlayer insulating film. And a passivation layer formed on the top surface.

In the conventional solid-state image pickup device, the vertical scanning circuit is formed in one N well 15, and the N well 15 and the peripheral portion of the semiconductor substrate 11 are covered with the light shielding layer 29. As a result, the portion of the PN junction formed between the semiconductor region forming each well and the substrate is covered with the light shielding layer 29, and the strong incident light from the outside does not adversely affect the operation of the circuit.
Reference numeral 27 indicates a drive line provided for each row for supplying a drive pulse to each pixel row arranged in each horizontal direction.

[0008]

In the above solid-state image pickup device, the light shielding layer 29 is formed by the second aluminum layer. This is because the second aluminum layer usually has a higher height than the first aluminum layer and has more undulations, resulting in poor line width controllability. Therefore, the second aluminum layer is not normally used for signal lines and clock lines that require high processing accuracy.

However, when the circuit configuration of the scanning circuit or the like becomes complicated, it may be necessary to use the second aluminum layer for the signal line and the clock line. FIG. 10B shows a state where some sort of signal line 31 is formed by using a part of the light shielding layer 29 formed of such a second aluminum layer. In such a case, the light shielding layer 29 is partially divided, and the semiconductor substrate 11 and the N well 1 are separated from the gap as shown by the arrow.
5, the PN junction composed of the N well 15 and the P wells 17 and 19 is irradiated with light. In such a situation, particularly when strong light is incident, unnecessary charges are photogenerated in these PN junctions, which may cause a malfunction of the drive scanning circuit or a latch-up phenomenon. Behavior cannot be guaranteed.

Therefore, in view of the problems in the structure of the conventional example described above, an object of the present invention is to cover a region other than the light receiving region in a semiconductor light receiving device having a light receiving region and a region other than the light receiving region. Even when the light-shielding layer is divided into a plurality of regions, it is possible to accurately prevent the adverse effect of incident light on the circuit operation.

[0011]

In order to achieve the above object, according to a first aspect of the present invention, a light receiving area for converting incident light into a corresponding electric signal and an area other than the light receiving area. A light-receiving layer having a light-shielding layer formed on a region other than the light-receiving region, the light-shielding layer being divided into a plurality of regions, each region covering at least a well region provided on the semiconductor substrate. Configure. In this case, the light shielding layer is composed of, for example, the second aluminum layer.

In such a structure, when the light-shielding layer formed of, for example, the second aluminum layer is divided into a plurality of regions by using a part of the light-shielding layer for a signal line or a clock line. Also, since each region covers at least the well region provided in the semiconductor substrate, there is no PN junction which is not shielded from light. Therefore, even when the light shielding layer is divided, the circuit does not malfunction or the latch-up phenomenon does not occur due to the incident light from the outside. That is, when a part of the light-shielding layer is used for a signal line or a clock line to divide the light-shielding layer to form a PN junction region that is not shielded from light, the well is also divided, and the divided well is covered with the light-shielding layer. By eliminating the PN junction region that is not shielded from light, the adverse effect of incident light is eliminated.

In the second aspect of the present invention, the light shielding layer is composed of a plurality of light shielding layers, each light shielding layer partially overlapping at least one other light shielding layer, and the plurality of light shielding layers form a well. It can also be configured to cover the area. In this case, the plurality of light shielding layers are composed of, for example, first and second aluminum layers.

That is, when a part of the light-shielding layer is used as a signal line or a clock line to divide the light-shielding layer to form a non-light-shielded PN junction region, a plurality of partially overlapping light-shielding layers are used to form a well. The region is shielded from light so that no PN junction region which is not shielded is generated.
For example, when a part of the second aluminum layer is used as a signal line or a clock line to divide the second aluminum layer, the first aluminum layer may be partially removed. Used as a light shielding layer. In this case, the connecting portion of the second aluminum layer and the first aluminum layer is partially overlapped so that the incident light from the outside is appropriately shielded. As a result, even when the light shielding layer is divided, it is possible to accurately prevent the influence of incident light from the outside and enhance the reliability of the semiconductor light receiving element.

Further, in each of the above-mentioned configurations, it is convenient to fix the potentials of the semiconductor substrate and the outer peripheral portion of each well to a predetermined potential at a plurality of points, for example, using aluminum wiring. As a result, the potentials of the outer periphery of the well and the semiconductor substrate can be reliably fixed to a predetermined potential, and when particularly strong light is irradiated, the charges generated by the light blocking incident from the unshielded region are reliably absorbed. Therefore, the reliability of the semiconductor light receiving element with respect to incident light can be further improved.

According to a third aspect of the present invention, in a semiconductor light receiving element having a light receiving region for converting incident light into a corresponding electric signal and a region other than the light receiving region, the semiconductor light receiving device other than the light receiving region is provided. The light-shielding layer is formed on the region, and the light-shielding layer is divided into a plurality of portions, and when the division results in a portion not shielded from light on the semiconductor substrate or the well region formed in the semiconductor substrate, the light-shielding layer is formed. The potential of the semiconductor substrate or the well region is fixed to a predetermined potential at the portion not covered. In this case, it is convenient to fix the semiconductor substrate and / or the outer peripheral portion of each well to a predetermined potential at a plurality of locations.

In such a structure, when the light-shielding layer is divided into a plurality of portions, so that a portion which is not shielded from light is generated on the semiconductor substrate or the well region, the potential of the semiconductor substrate or the well region is controlled at the portion not shielded from light. By fixing at the predetermined potential, it is possible to reliably absorb the photo-generated charges in the PN junction region which is not shielded from light to the predetermined potential. That is, even when incident light from the outside is applied to the PN junction region that is not shielded to generate charges, the charges are absorbed by the semiconductor substrate or the well region fixed to a predetermined potential, and the potential of the potential due to light irradiation is increased. There is no fluctuation, and it is prevented that the circuit operation is adversely affected.

By fixing the semiconductor substrate and / or the outer peripheral portion of each well to a predetermined potential at a plurality of points by aluminum wiring having a low resistance value, for example, fluctuations in the potential due to light irradiation can be surely suppressed. Therefore, the reliability of the circuit can be improved.

[0019]

DETAILED DESCRIPTION OF THE INVENTION A semiconductor light receiving element according to the present invention will be described below with reference to the drawings. FIG. 1 is a plan view showing a schematic configuration of a vertical scanning circuit portion of a semiconductor light receiving element according to an embodiment of the present invention. FIG. 2 is similar to FIG.
3 is a partial cross-sectional view taken along line AA of FIG. In the structures shown in these figures, N ⁺ type buried layers 13a and 13b are formed on the P type semiconductor substrate 11 separately from each other. Further, N wells 15a and 15b are formed in the respective N ⁺ type buried layers 13a and 13b, and P wells 17 and 19 are formed in these N wells 15a and 15b, respectively. Since the vertical scanning circuit is constructed using the CMOS circuit, a P channel MOS transistor and an N channel MOS transistor are formed in N wells 15a and 15b and P wells 17 and 19, respectively.

Thereafter, the clock lines 23a, 23b and the power supply lines 25a, 2b are formed on the semiconductor substrate 11 and the respective wells with the insulating film 21 interposed therebetween by the first aluminum layer.
5b, the drive line 27, etc. are formed. afterwards,
Further, for example, the clock line 31 and the light shielding layers 29a and 29b are formed of the second aluminum layer via the insulating layer 21. Note that the insulating layer 21 is actually formed of a plurality of insulating layers, as described in the description of FIG.

In the structure shown in FIGS. 1 and 2, N ⁺
The buried layers 13a and 13b and the N wells 15a and 15b are separated from each other so that the N wells 15a and 15b are completely covered by the light shielding layers 29a and 29b, respectively. That is, the interfaces between the P-type substrate 11 and the N wells 15a and 15b are all covered with the light shielding layers 29a and 29b. As a result, even if the light-shielding layer is divided by the wiring interposed between them, the PN junction between the substrate and the well is completely shielded from light, and the influence of malfunction or latch-up phenomenon due to unnecessary photo-generated charges. Can be avoided exactly.

Next, FIG. 3 is a schematic plan view showing the structure in the vicinity of the vertical scanning circuit of the semiconductor light receiving element according to the second embodiment of the present invention. In the configuration shown in FIG.
As in the case of the above embodiment, the N ⁺ buried layer and the N well are divided into N ⁺ buried layers 13a and 13b and N wells 15a and 15b, respectively. The second aluminum layer forms the light shielding layers 33a and 33b to shield the N wells 15a and 15b from light. However, in the configuration of FIG. 3, the light shielding layer 3 formed of the second aluminum layer is used.
When 3a and 33b cannot shield the whole of each N well 15a and 15b, or when it does not shield the whole, well, another light shielding layers 35a and 35b are formed by the first aluminum layer. However, in this case, the light shielding layers 35a and 35b made of aluminum of the first layer and the light shielding layers 33a and 33b made of the second layer of aluminum are partially overlapped, and the incident light leaks from the gap between the both light shielding layers. I try not to get involved. The overlapping amount of the two light-shielding layers to be overlapped should be such that incident light from an oblique direction can be shielded.

That is, in the configuration of FIG. 3, the N well 15a is shielded from light by the light shielding layer 35a made of the first aluminum layer and the light shielding layer 33a made of the second aluminum layer.
The light shielding layer 5b is shielded by a light shielding layer 35b composed of a first aluminum layer and a light shielding layer 33b composed of a second aluminum layer. With this configuration, when the entire well cannot be shielded by the second layer aluminum alone, the entire well can be shielded safely by partially arranging the first layer aluminum and using it as a light shielding layer. It will be possible.
This allows the second layer aluminum to be connected to the clock line 3 for example.
7 and the like, the first layer aluminum can also be used as the clock or power supply lines 39a, 39b, etc., and proper wiring can be performed.

Next, FIG. 4 is a plan view showing a schematic structure in the vicinity of a vertical scanning circuit of a semiconductor light receiving element according to the third embodiment of the present invention. Further, FIG. 5 is a cross-sectional view taken along the line AA of FIG. In the configurations shown in these figures, the N ⁺ buried layers 13 and N formed in the semiconductor substrate 11 are
The structures of the well 15 and the P wells 17 and 19 are the same as those shown in FIG. 9 and FIG. 10A, and the same reference numerals are used for the same portions. In the configuration of FIG. 4, when it is desired to use the second aluminum layer as the clock line 41, the light shielding layer composed of the second aluminum layer is necessarily divided into 29a and 29b. In such a case, the PN junctions in the regions indicated by B, C, D, and E in FIG. 4 are not shielded from light, and when irradiated with light, photocharges are generated, which may cause malfunction of the device.

However, in the configuration of FIG. 4, the power line indicated by the reference numeral 43 is passed through the non-light-shielded region, and the potential of the N well 15 is fixed to a predetermined potential by the contacts 45 provided at a plurality of locations. In this case, the power supply line 43 is made of the second layer aluminum in FIG. However, the first layer may be made of aluminum or the like.
Since the resistance value of the power supply line 43 formed of aluminum wiring is smaller than that of the semiconductor substrate or the well, the potential of the well or each part of the substrate can be accurately fixed to a predetermined potential. By fixing the potential of the well or the substrate as described above, unnecessary photo-generated charges generated by the incident light can be absorbed in the power supply line of a predetermined potential, and the potential fluctuation of the PN junction can be suppressed to prevent malfunction or latch-up phenomenon. It can be avoided. Note that in the embodiment of FIG. 4, it is desirable not to provide an active region for forming a transistor or the like in a region that is not shielded or a portion where stray light easily reaches.

The fixation of the well potential described above is not limited to the configuration shown in FIG. 4, but is effective when applied to the configurations of the first and second embodiments, and the influence of incident light is further increased. It can be reduced. A method of fixing the electric potential that can be commonly used in the respective embodiments will be described with reference to FIGS. 6 and 7. 6 is a plan view showing a schematic configuration in the vicinity of one N well, and FIG. 7 is a sectional view taken along the line AA of FIG. In the configurations shown in these figures, P
Type semiconductor substrate 47 are formed an N ⁺ type buried layer 49, N-well 51 on the said N ⁺ buried layer 49 is formed. A P well 53 is formed in the N well 51.

In the structure shown in FIGS. 6 and 7, aluminum wiring 57a is formed along the peripheral portion of P well 53, that is, the portion near the boundary with N well 51. Further, a P ⁺ type diffusion region 57b is formed in the P well 53 along the aluminum wiring 57a, and is connected to the aluminum wiring 57a at a plurality of places through contact holes. Further, an aluminum wiring 55a is provided in the peripheral portion of the N well 51, that is, the boundary portion with the P well 53 and the outer peripheral portion thereof, and N ⁺ formed on the N well 51 side
It is connected to the mold diffusion region 55b at a plurality of places through contact holes. The potential of the P well 54, which is the isolation region outside the N well 51, is P ⁺ formed on the P well 54 side by providing the aluminum wiring 59a in the portion surrounding the N well 51.
Connection is made with the mold diffusion region 59b at a plurality of locations through contact holes. The diffusion regions 55b, 57b, 59b
May be formed continuously or may be scattered along the corresponding aluminum wiring.

With this configuration, each aluminum wiring 5
By fixing 5a, 57a, and 59a to predetermined potentials respectively, even if there are photo-generated charges due to stray light from the region without the light-shielding layer, fluctuations in the well potential are suppressed, so that a latch-up phenomenon or the like occurs. There is no inconvenience. The potential of the P well 54 may be fixed to the substrate potential in the P ⁺ diffusion region 59b.

[0029]

As described above, according to the present invention, even when the light-shielding aluminum layer is divided due to a complicated circuit configuration and a large circuit scale, it is formed between the substrate and the well. The PN junction portion can be completely shielded from light, and it is possible to appropriately prevent unnecessary photo-generated electric charges from being generated by light irradiation and causing a malfunction of the circuit or a latch-up phenomenon. Therefore, even if the semiconductor light receiving element is irradiated with strong light, stable operation is performed and high reliability can be maintained.

Further, according to the present invention, even if there is a region where light cannot be completely shielded as a result of the circuit structure becoming complicated and the circuit scale becoming large and the light shielding layer being divided, the photo-generated charge is fixed by fixing the well potential. Fluctuation of the well potential due to can be suppressed. Therefore, even if the photo-generated electric charges are generated by the strong incident light, it is possible to prevent the circuit malfunction and the latch-up phenomenon.

[Brief description of drawings]

FIG. 1 is a schematic plan view showing a semiconductor substrate structure and a wiring configuration of a semiconductor light receiving element according to a first embodiment of the present invention.

FIG. 2 is a sectional view taken along line AA of FIG.

FIG. 3 is a schematic plan view showing a semiconductor substrate structure and a wiring configuration of a semiconductor light receiving element according to a second embodiment of the present invention.

FIG. 4 is a schematic plan view showing a semiconductor substrate structure and a wiring configuration of a semiconductor light receiving element according to a third embodiment of the present invention.

FIG. 5 is a sectional view taken along line AA of FIG. 4;

FIG. 6 is a schematic plan view for explaining a method of fixing a well potential.

FIG. 7 is a sectional view taken along line AA of FIG. 6;

FIG. 8 is an explanatory block diagram showing a schematic configuration of a general solid-state imaging device.

FIG. 9 is a schematic plan view for explaining a semiconductor substrate structure and a wiring configuration of a conventional semiconductor light receiving element.

10 is a cross-sectional view taken along the line AA of FIG.
(A) shows the structure when the light shielding layer is not divided,
(B) shows the structure when the light shielding layer is divided.

[Explanation of symbols]

11 semiconductor substrate 13, 13a, 13b N ⁺ buried layer 15, 15a, 15b N well 17, 19 P well 21 insulating layer 23a, 23b clock line 25a, 25b power line 27 drive line 29, 29a, 29b light shielding layer 31, 41 Clock line 33a, 33b Light shielding layer made of second layer aluminum 35a, 35b Light shielding layer made of first layer aluminum 37 Clock line 39a, 39b Power supply line 43 Potential fixing power supply line 45 contacts

Claims (7)

[Claims] 1. A semiconductor light-receiving element having a light-receiving portion region for converting incident light into a corresponding electric signal and a region other than the light-receiving portion region, the semiconductor light-receiving element being formed on a region other than the light-receiving portion region. And a light-blocking layer, the light-blocking layer being divided into a plurality of regions, each region covering at least a well region provided in the semiconductor substrate. 2. The semiconductor light receiving element according to claim 1, wherein the light shielding layer is made of a second aluminum layer. 3. The light-shielding layer comprises a plurality of light-shielding layers, each light-shielding layer partially overlapping at least one other light-shielding layer, and the plurality of light-shielding layers cover the well region. The semiconductor light receiving element according to claim 1. 4. The semiconductor light receiving element according to claim 3, wherein the plurality of light shielding layers are composed of a first layer and a second layer of aluminum layers. 5. The semiconductor light receiving element according to claim 1, wherein the potentials of the semiconductor substrate and the outer peripheral portion of each well are fixed at a predetermined potential at a plurality of points. 6. A semiconductor light-receiving element having a light-receiving portion region for converting incident light into a corresponding electric signal and a region other than the light-receiving portion region, the semiconductor light-receiving element being formed on a region other than the light-receiving portion region. A light-shielding layer, the light-shielding layer is divided into a plurality of portions, and when a light-shielding portion is formed on a semiconductor substrate or a well region formed on the semiconductor substrate due to this division, the semiconductor is protected by the light-shielding portion. A semiconductor light receiving element characterized in that the potential of a substrate or a well region is fixed to a predetermined potential. 7. The semiconductor light receiving element according to claim 6, wherein the semiconductor substrate and / or the outer peripheral portion of each well is fixed to a predetermined potential at a plurality of positions.