JPH09251527A - Picture synthesizing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a picture synthesizing system which works with a small mounting area, has plural picture processing ICs and a high extendability are provided. SOLUTION: The plural picture processings IC 11 -1n are connected to a shared picture data bus 7 and a control signal bus 6 with respective picture synthesization ICs. Therefore, the pattern of picture data can be min. compared with a conventional device using an exclusive picture data bus at every picture processing IC. In the picture processings IC 11 -1n , ID data indicating priority order which is inputted from the picture synthesization ICs 3 with the control signal bus 6 is compared with ID which is set to itself from an outside. Unless a colorless and transparent data signal is active at the time of coincidence, a reply is returned to the picture synthesization ICs 3 with the control signal bus 6 and, then, picture data is transmitted to the picture data bus 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image synthesizing system, and more particularly to an image synthesizing system for synthesizing images formed by a plurality of image processing integrated circuits (ICs) such as personal computers and TV game machines.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing an example of a conventional image synthesizing method. This image synthesizing method uses a plurality of independent image processing integrated circuits (image processing I) having a memory for image data.
In a device for synthesizing and displaying the images created in C), image data memories 52 _{1 to} 52 _n are provided in a one-to-one correspondence with the _n image processing ICs 51 _{1 to} 51 _n, and the image processing is performed. The ICs 51 _{1 to} 51 _n are commonly connected to an image synthesizing integrated circuit (image synthesizing IC) 54 via individual image data buses 53 _{1 to} 53 _n . This image synthesis IC
The output of 54 is an image display integrated circuit (image display IC) 55.
It is connected to the.

To explain the operation of this image synthesizing method, the display synchronization signal from the image display IC 55 is the image processing IC.
51 _1-51 when supplied to _n, each of the image processing IC 51 ₁ ~
51 _n supplies the color data of the pixels in synchronism with the display synchronization signals, to the image synthesizer IC54 via the respective image processing IC 51 ₁ to 51 _n dedicated image data bus 53 ₁ to 53 _n of.

[0004] Image Synthesis IC54 in advance to each image is registered in the internal priority table processing IC 51 ₁ to 5
Based on the priority of 1 _n , each of the image processing ICs 51 _{1 to} 51
The image data from _n is confirmed in order from the IC with the highest priority. In this confirmation, the image processing ICs 51 _{1 to} 5
It is determined whether or not the color data of the pixel from 1 _n indicates colorless and transparent, and if it is colorless and transparent, the color data from the image processing IC whose priority is one lower is colorless and transparent. Repeat to check whether or not.

In this way, the image synthesizing IC 54 outputs the first found color data other than the colorless and transparent to the image display integrated circuit (display IC) 55. The image display IC 55 displays the color data sent from the image composition IC 54.

As another conventional image synthesizing method,
The image data buses 53 _{1 to} 53 _n between the image processing ICs 51 _{1 to} 51 _n and the image combining IC 54 are shared by one bus,
The image synthesizing IC 54 and the image processing ICs 51 _{1 to} 51 _n are connected by a dedicated selection signal, and the image synthesizing IC 54 controls the selection signal in order from the highest priority to the lowest priority based on the priority order data to transfer data. There is also known a configuration in which image synthesis is performed by controlling the output of data from the image processing ICs 51 _{1 to} 51 _n so that the data is output and when data other than colorless and transparent is output, the data is transferred to the image display IC 55. ing.

[0007]

However, the former one of the conventional image synthesizing methods is the image processing IC 51 ₁
There is a problem that it is more difficult to make an image combining method as the number n of ~ 51 _n increases. This Each image processing IC 51 ₁ to 5
It is necessary to have an image data bus 53 ₁ to 53 _n dedicated for each 1 _n, (the bit width of the image data) × (image processing I
Number of Cs: Here, n) image data patterns are required, the signal pattern area on the substrate is large, and the number of input signal pins for image data on the image combining IC side is also large. Therefore, an image compositing IC capable of connecting a large number of image processing ICs 51 _{1 to} 51 _n due to the restrictions of the IC package.
This is because 54 is difficult to make.

In the latter one of the conventional image synthesizing methods, since the selection signal of the image processing IC is one to one, the number of image processing ICs to be connected to the image synthesizing IC has a selection signal in advance. Since it is necessary to install the image processing IC, it is difficult to construct an image synthesizing method capable of adding / changing the image processing IC.

[0009] The present invention has been made in view of the above points,
An object of the present invention is to provide an image synthesizing method having a plurality of image processing ICs, which can be realized with a small mounting area and is highly expandable.

[0010]

In order to achieve the above object, the present invention has priorities set in advance from the outside, and when the priorities are specified from the outside via the control signal bus, the priorities are respectively set. A plurality of image processing integrated circuits outputting image data to a common image data bus connected to each other, a plurality of memories storing image data output by the plurality of image processing integrated circuits, and a plurality of image processings Connected to the image data bus and the common control signal bus, respectively, and outputs the ID data indicating the priority of the image processing integrated circuit requesting the image data to the control signal bus to output a plurality of image processing signals. From an image synthesizing integrated circuit that supplies image data to the integrated circuit and synthesizes image data input from the corresponding image processing integrated circuit via the image data bus. It is obtained by a configuration having a display means for displaying a force image data.

In the present invention, since the plurality of image processing integrated circuits are connected to the image data bus and the control signal bus which are common to the image synthesizing integrated circuits, a dedicated image processing integrated circuit is provided for each image processing integrated circuit. The pattern of the image data can be minimized as compared with the conventional device using the image data bus.

Further, according to the present invention, the selection of the image processing integrated circuit for outputting the data to the image data bus is performed by selecting the ID data from the image synthesizing integrated circuit and the image processing integrated circuit via the control signal bus. This can be done by comparing with the set priority.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an image synthesizing system according to the present invention. In the figure, image data memories 2 ₁ to 2 _n are provided in a one-to-one correspondence with _n image processing integrated circuits (image processing ICs) 1 ₁ to 1 _n each having a priority determination unit, The image processing ICs _{1 1} to 1 _n are connected to an image synthesizing integrated circuit (image synthesizing IC) 3 via a common control signal bus 6 and a common image data bus 7.

Further, the display integrated circuit (display IC) 4 is
The display synchronization signal is sent via the signal line 8 to the image processing ICs _{1 1} to 1 _n.
And the image synthesizing IC 3 and the image synthesizing IC
The image data supplied from 3 is D / A converted and output to the cathode ray tube (CRT) 5 for image display. The image processing ICs _{1 1} to 1 _n are connected to the CPU bus 9, respectively.

Memory 2₁~ 2_nImage processing IC1₁~ 1_n
The image data used in is stored. Image processing IC
1₁~ 1_nHave the same configuration and are shown in the block diagram of FIG.
Configuration. As shown in the figure, the image processing IC
1₁~ 1_nArbitrary k-th image processing IC_kIs a note
Re-control unit 21, image data output buffer 22, output permission
It is composed of a judgment unit 23 and an ID data storage unit 24.
Memory 2_kManage. Image data output buffer 2
2 is connected to the image data bus 7. ID data
The storage unit 24 writes ID data from the CPU bus 9 in advance.
It is stuffed.

Now, when the display synchronization signal is input to the memory control unit 21 in the image processing IC _{1 k} via the signal line 8,
The memory controller 21 reads the data stored in the memory 2 _k and transfers it to the image data output buffer 22. When the data input from the image data output buffer 22 is data indicating colorless and transparent, the output permission determination unit 23 does not perform the priority determination operation on the control signal bus 6.
The priority order determination operation is performed when the color data is not colorless and transparent.

That is, the output permission judging section 23 compares the ID data stored in the ID data storing section 24 with the ID data input from the image synthesizing IC 3 via the control signal bus 6, and based on the comparison result, the priority order is obtained. The determination operation of is performed. When it is confirmed by this priority order determination operation that the data can be output, the output permission determination unit 23 sends an output permission signal to the image data output buffer 22 and outputs the stored image data to the image data bus 7. Let The image data output from the image data output buffer 22 at this time is color data of the image displayed at the timing of the display synchronization signal of the signal line 8.

FIG. 3 is a block diagram showing a schematic structure of an example of the image synthesizing IC 3 shown in FIG. As shown in the figure, the image synthesis IC 3 includes a priority data register 31 having a capacity capable of storing m pieces (m ≧ n) of ID data, a signal line 8,
Data for displaying when there is no color data output from the determination control unit 32 connected to the control signal bus 6 and all the image processing ICs _{1 1} to 1 _n shown in FIG.
The background color data storage unit 33 is registered via the background color data storage unit 33, and the data switching unit 34 for selecting one of the background color data and the image data from the image data bus 7.

The priority data register 31 stores ID data indicating the priority via the CPU bus 9. Here, a register having a younger address (lower address) of the priority order data register 31 has a higher priority order, and data subsequent to a register having no data (when 0) is not used for determining the priority order.

When the display synchronization signal is input to the determination control unit 32, the determination control unit 32 reads out the highest priority ID data recorded in the register of the lowest address of the priority data register 31, and outputs the control signal bus. If there is no response from the image processing IC of the ID data specified in the priority determination on the control signal bus 6, the priority determination is performed via Second priority I recorded
The D data is read and the priority order is determined again via the control signal bus 6.

The determination control unit 32 repeats the above determination operation in the priority determination on the control signal bus 6 until there is a response from the image processing IC having the corresponding ID, and the image processing I
When there is a response from C, the data switching unit 34 controls to select the image data input from the image data bus 7, and the data recorded in the highest address register of the priority order data register 31 is controlled. When there is no determination in the determination operation with ID data having a low priority, and when the value read from the priority determination data register 31 is 0, the determination operation is stopped and the data switching unit 34 causes the background color data. Switching control is performed so that the background color data from the storage unit 33 is selected.

FIG. 4 shows a timing chart of the priority determination operation on the control signal bus 6. The control signal bus 6 is shown in FIG.
The ID data shown in (A), the SEL signal shown in (B), the ACK signal shown in (C), and the OE signal shown in (D) are transmitted. The ID data is output from the image combining IC3. In the case of this embodiment, assuming that there are seven image processing ICs of n, it is necessary to have at least three signal lines. The SEL signal is a signal indicating that the ID data is valid and is output from the image synthesizing IC 3. The ACK signal is a signal output by the image processing IC having the corresponding ID for a reply. The OE signal is a signal that permits the image processing IC that has output the ACK signal to output the image data to the image data bus 7, and is output by the image combining IC 3.

Next, the operation of this embodiment will be described. First, the image synthesizing IC 3 of FIG. 1 determines the timing of taking in the image data of the display pixel from the display synchronization signal input from the display IC 4 via the signal line 8, and the determination control unit 32 shown in FIG. After the ID data registered in the highest priority register in the priority data register 31 is output to the control signal bus 6, the SEL signal 42 is asserted to start the priority determination operation.

Each of the image processing ICs _{1 1} to 1 _n commonly connected to the control signal bus 6 is input via the control signal bus 6 when the SEL signal input via the control signal bus 6 is asserted. The value of the generated ID data is taken into the output permission judging unit 23 shown in FIG.
The value is compared with the value registered in the ID data storage unit 22 therein. As a result of comparison, even when the data value of the ID data storage unit 22 and the value of the input ID data are the same, when the colorless and transparent data from the image data output buffer 22 is active, When the data value and the input ID data are different, the output permission determination unit 23 does not assert the ACK signal output to the control signal bus 6.

The determination control unit 32 of the image synthesis IC 3 receives no response from the image processing IC of the ID data designated in the priority determination on the control signal bus 6, that is, AC.
If the K signal is not asserted, the ID data of the second priority recorded in the register of the address next to the priority data register 31 is read out and output through the control signal bus 6, and then the SEL signal. Assert.

Thus, each of the image processing ICs _{1 1} to 1 _n receives the value of the ID data input via the control signal bus 6 again when the SEL signal input via the control signal bus 6 is asserted. Is taken into the output permission determination unit 23 shown in FIG. 2 and compared with the value registered in the ID data storage unit 22 in the image processing IC. At this time, ID
When one image processing IC having the same data value in the data storage unit 22 and the input ID data value has no colorless transparent data signal from the image data output buffer 24, the image processing IC The output permission determination unit 23 outputs the ACK signal output to the control signal bus 6 as shown in FIG.
Assert as indicated by c1 in (C).

When the image synthesizing IC 3 detects that the ACK signal has been asserted by the judgment control section 32 shown in FIG. 3, the OE signal to be output to the control signal bus 6 is changed as shown by d1 in FIG. 4 (D). Image processing I that asserted and returned a reply
Data output to the image data bus 7 is permitted for C. That is, the image processing IC that asserts the ACK signal
Of the image processing I that asserts the ACK signal in order to output the output permission to the image data output buffer 22 after the output permission determination unit 23 of the above confirms that the OE signal is asserted.
The image data is output from the image data output buffer 22 of C to the image data bus 7.

The image composition IC 3 outputs the image data input via the image data bus 7 to the display IC 4 of FIG. 1 via the data switching section 34 of FIG. As a result, the pixels based on the above image data are displayed on the CRT 5 via the display IC 4. Further, the image synthesizing IC3 judges the timing when the data fetching of the display IC4 is completed from the display synchronizing signal, and negates the OE signal as indicated by d2 in FIG. 4 (D). When the OE signal is negated, the image processing IC that asserted the ACK signal stops outputting the image data to the image data bus 7, and negates the ACK signal as indicated by c2 in FIG. 4C. Image synthesis IC3 is AC
After confirming that the K signal has been negated, b in FIG.
The SEL signal is negated as indicated by.

Thereafter, the above operation is repeated pixel by pixel, and the image data stored in the memories 2 ₁ to 2 _n is converted into CRT5.
Will be displayed. As described above, in this embodiment, since the image data bus 7 is shared by the image processing ICs _{1 1} to 1 _n , the signal pattern area on the substrate can be reduced and the image data input from the image synthesis IC 3 can be performed. The number of signal pins is minimum, and many image processing ICs can be connected. Further, the selection of the image processing IC that outputs the data to the image data bus 7 is performed by the output permission determination unit 23 in the image processing IC and the ID data stored in the ID data storage unit 24 and the image synthesis IC
The ID data recorded in the priority order data register 31 in FIG.
Since it can be set via the bus 9, the system can be easily expanded or changed.

[0031]

As described above, according to the present invention,
By connecting a plurality of image processing integrated circuits to a common image data bus and control signal bus with the image synthesizing integrated circuit respectively, a conventional device using a dedicated image data bus for each image processing integrated circuit is realized. In comparison, the pattern of image data can be minimized, thus reducing the board area required for the image data bus and the number of input pins required for the integrated circuit for image synthesis, and also for performing multiple image processing. IC
It is easy to reduce the number of selection signals required for connection of the above even if the number of image processing ICs increases.

Further, according to the present invention, the selection of the image processing integrated circuit for outputting the data to the image data bus is performed through the control signal bus to the ID data from the image synthesizing integrated circuit and the image processing integrated circuit. Since it is possible to compare with the set priority, it is possible to connect as many image processing integrated circuits as the number capable of being combined by the image combining integrated circuit to the image data bus and selectively use them as required.

Further, according to the present invention, by determining the ID to be set in the image processing integrated circuit which is not used,
Even if the image processing integrated circuits having the number of IDs or more are connected to the image data bus and the control signal bus, (the number of IDs-1) image processing integrated circuits can be used at the same time. When adding an image processing integrated circuit, it is not necessary to care about the number of image processing integrated circuits already inside the apparatus, and the system can be easily expanded.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an embodiment of the present invention.

FIG. 2 is a block diagram of an example of the image processing IC in FIG.

3 is a block diagram of an example of an image combining IC in FIG.

4 is a timing chart for explaining a priority order determination operation in the control signal bus of FIG.

FIG. 5 is a block diagram showing an example of the related art.

[Explanation of symbols]

1 ₁ to 1 _n , 1 _k image processing integrated circuit (image processing IC) 2 ₁ to 2 _n , 2 _k image data storage memory 3 image synthesizing integrated circuit (image synthesizing IC) 4 display integrated circuit (display IC ) 5 cathode ray tube (CRT) 6 control signal bus 7 image data bus 8 signal line for display synchronization signal 9 CPU bus 21 memory control unit 22 image data output buffer 23 output permission determination unit 24 ID data storage unit 31 priority data register 32 Judgment control unit 33 Background color data storage unit 34 Data switching unit

Claims (3)

[Claims] 1. A priority is set in advance from the outside, and when the priority is designated from the outside via a control signal bus, image data is output to a common image data bus connected to each other. A plurality of image processing integrated circuits, a plurality of memories storing image data output by the plurality of image processing integrated circuits, a plurality of image processing integrated circuits, the image data bus and common control ID data indicating the priority order of the image processing integrated circuits that are connected to the signal bus and request image data to the control signal bus are supplied to the plurality of image processing integrated circuits for corresponding image processing. Image synthesis integrated circuit for synthesizing image data input from the image synthesis integrated circuit via the image data bus, and image data output from the image synthesis integrated circuit. An image synthesizing method, comprising: 2. Each of the plurality of image processing integrated circuits includes a memory control unit that reads image data from a corresponding memory of the plurality of memories, and image data to which the image data read by the memory control unit is written. An output buffer, a data storage unit in which first ID data indicating the priority order assigned to the image processing integrated circuit is externally written, and priority input from the image synthesizing integrated circuit via the control signal bus. When the second ID data indicating the order and the first ID data from the data storage unit are compared and both are equal and the image data from the image data output buffer is not colorless and transparent color data,
2. The image synthesizing method according to claim 1, further comprising an output permission determining unit that outputs image data from the image data output buffer to the image data bus. 3. The image synthesizing integrated circuit comprises: a recording unit that externally records ID data indicating a priority at sequential addresses; a storage unit that stores background color data; and the image data bus. A data switching unit that selects and outputs one of the image data input via the storage unit and the background color data from the storage unit, and the ID data having a high priority from the recording unit is output to the control signal bus to correspond to the data. When there is no response from the image processing integrated circuit, outputting the ID data of the next priority from the recording means to the control signal bus is repeated until a response from the corresponding image processing integrated circuit is received. If there is, the data switching unit selects the image data input via the image data bus, and if there is no response from all the image processing integrated circuits, the background color data 3. The image synthesizing method according to claim 1 or 2, further comprising: a determination control unit for selecting.