JPH09251395A - System recognition system for duplex device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a system from being erroneously recognized by the erroneous of a switch. SOLUTION: Thin system is composed of an operation system logical card 1, a standby system logical card 2, a board 3 to which the cards 1 and 2 are connected, and a power supply part 104 which supplies the electric power to both cards 1 and 2 via the connection parts 15 and 16 of the board 3. Then a terminal P5 of the part 15 corresponding to a system recognition signal input terminal P1 of the card 1 is grounded via a short-circuit line 30, and a terminal P6 of the part 16 corresponding to a system recognition signal input terminal P2 of the card 2 is kept open. Thus the card 1 recognizes its own computer as an operation system by detecting the ground voltage, and the card 2 where the ground voltage is not detected recognizes its own computer as a standby system respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system recognition system for a duplex device.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram of a conventional system recognition system for a duplex device. A conventional system recognition system for a duplex device includes an operational computer 101,
The operating system logic card 102 for duplex control of the operating system computer 101 and the standby computer 11
1 and a standby logical card 112 for controlling the duplex of the standby computer 111, and these cards 1
Board 103 to which 02 and 112 are connected, and board 10
Power to cards 102, 112 via 3 (eg +
The power supply unit 104 supplies 5 V and 0 V (GND).

A signal line 107 for communication between the cards 102 and 112 is connected to the cards 102 and 112 via a board 103.

In this duplex device, an operating computer 101 is currently in operation, and a standby computer 111 is currently on standby.

In order to recognize whether the system is currently in operation or in standby, each card 102, 112 is conventionally provided with a DIP switch 108, 109. For example, the DIP switch 108 of the active system logical card 102 is currently in operation. “1111” indicating that the standby is in progress is set, and “2222” indicating that the standby is currently in progress is set in the DIP switch 109 of the standby system logical card 112. Further, the settings of the dip switches 108 and 109 are made manually.

The system recognition is performed by reading the numbers set on the DIP switches 108 and 109. That is, the DIP switch 108 is set to "1.
Since it is "111", it is determined that it is currently the active system, and because the DIP switch 109 is "2222", it is currently the standby system.

Further, Japanese Utility Model Laid-Open No. 37537/1993 discloses a master / slave recognition device for recognizing a system based on information set by a manual changeover switch.
Japanese Patent No. 81433 discloses an access designation device for another system which recognizes a system using a system identification signal of a transmission source and a reception destination and an own system number set by a switch or the like.

[0008]

However, in these conventional examples, system recognition is manually performed by a switch or the like. Therefore, there is a drawback in that the system may be erroneously recognized due to a setting error of a switch or the like.

Therefore, an object of the present invention is to provide a system recognition system for a duplex device, which can prevent erroneous recognition of the system.

[0010]

In order to solve the above problems, the present invention is a system recognition system for system recognition of a duplex device, and system recognition signal output means for outputting a signal for recognizing two systems. , System recognition means provided in each system for recognizing the system based on the system recognition signal output from the system recognition signal output means.

[0011]

According to the present invention, a signal for recognizing two systems is output from the system recognition signal output means, and this signal is input to the system recognition means provided in each system. The system recognizing means determines whether its own system is an operating system or a standby system based on the input recognition signal.

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram of an embodiment of a system recognition system for a duplex device according to the present invention.
The same components as those of the conventional example are denoted by the same reference numerals, and the description thereof will be omitted.

A system recognition system for a duplex device according to the present invention comprises an active computer 101, an active logical card 1 for controlling the duplex of the active computer 101, a standby computer 111, and the standby computer 111. Standby logic card 2 for duplex control, board 3 to which these cards 1 and 2 are connected, and power supply for supplying power (for example, + 5V and 0V (GND)) to cards 1 and 2 via board 3. It is composed of a section 104.

In addition, the card 1 and the card 2 are the card 1,
A signal line 107 for communication between the two is connected via the board 3.

Further, the internal configurations of the card 1 and the card 2 are completely the same, and the cards 1 and 2 have system recognition signal input terminals P1 and P2, respectively. Then, the system recognition signal input terminal P1 of the operational system logic card 1 is supplied with O from the power supply unit 104.
The ground voltage of V (GND) is supplied via the board 3 and the signal line 11, but the system recognition signal input terminal P2 of the standby logic card 2 is not supplied with the ground voltage of OV (GND) from the power supply unit 104. As described above, the boat 3 is subjected to the treatment described below. That is, the other end of the signal line 12 connected to the input terminal P2 is open.

FIG. 2 is a schematic explanatory view showing a connection state of the logic card, the board and the power supply section.

The board 3 has connectors (connectors) 15, 1
6 is provided, the active logical card 1 is connected to the connecting portion 15, and the standby logical card 2 is connected to the connecting portion 16.

Further, the signal lines 105, 1 from the power supply unit 104
A positive voltage (+ 5V in the present embodiment is not limited to this) is supplied to the active logic card 1 and the standby logic card 2 via 7, and the signal lines 106 and 11 are supplied.
Via the active logical card 1 and the standby logical card 2
The ground voltage (0V; GND) is supplied to the. With these voltages, the active logic card 1 and the standby logic card 2
Is driven.

Further, the signal line 107 is the operational logic card 1
And a signal line for communication between the standby logic card 2 and
For convenience, the number is one, but a plurality may be provided between the connecting portions 15 and 16.

By the way, the terminal P5 of the connecting portion 15 corresponding to the system recognition signal input terminal P1 of the operational system logic card 1 is short-circuited to the ground signal line 11 by the short-circuit line 30. On the other hand, the terminal P6 of the connecting portion 15 corresponding to the system recognition signal input terminal P2 of the standby logic card 2 is not short-circuited to the ground signal line 11.

Therefore, in the state in which the operational logic card 1 is connected to the board 3, the system recognition signal input terminal P1 of the operational logic card 1 is at the ground level. On the other hand, in the state where the standby logic card 2 is connected to the board 3,
The system recognition signal input terminal P2 of the standby system logic card 2 does not become the ground level but becomes open (high impedance).

The active logical card 1 has a parallel I / O 4 described later inside, and the standby logical card 2 has a parallel I / O 5 described later inside. The system recognition signal input from the system recognition signal input terminal P1 of the active system logic card 1 is input to the parallel I / O4, and the system recognition signal input from the system recognition signal input terminal P2 of the standby system logic card 2 is Each of the cards 1 and 2 is configured to be input to the parallel I / O 5.

FIG. 3 is a block diagram of a logic card. The configuration of the logical card is the same for both the active system and the standby system. Since then
The logical card 1 will be described, but the same applies to the logical card 2. The numbers in parentheses are the numbers for the logic card 2. For the signal line, the same numbers are attached to the logic cards 1 and 2 for convenience.

The logic card 1 (2) has a system recognition signal input terminal P1 (P2) and a parallel I / O4 () to which the system recognition signal is input via the system recognition signal input terminal P1 (P2) and the signal line 20. 5) and the address decoding unit 7 (7 ')
And a CPU (central processing unit) 8 (8 ').

A positive voltage (+ 5V) is applied to the signal line 20 from the power supply unit 104 via the pull-up resistor 9 (9 ').
Is supplied.

An address signal line 21 is provided between the CPU 8 (8 ') and the address decoding unit 7 (7').
(8 ') and the parallel I / O4 (5), the register select signal lines 22 and 23 are connected to the address decoding unit 7 (7).
′) And the parallel I / O 4 (5) between the chip select signal line 24, the read signal line (READ) 25, the write signal line (WRITE) 26, and the data signal line (DATA).
27 are connected to each.

In this structure, the signal line 20 is pulled up to a positive voltage via the pull-up resistor 9 (9 '), and in the case of the operational logic card 1, the ground voltage is applied to the connecting portion P1. Therefore, the ground voltage, that is, a low (LOW) level signal is input to the parallel I / O 4.

On the other hand, in the case of the standby logic card 2, the connection portion P2 is opened (high impedance), so that a positive voltage, that is, a high (HIGH) level signal is input to the parallel I / O5.

Next, the operation of this logic card will be described. FIG. 4 is a flow chart showing the operation of the logic card,
FIG. 5 is a flowchart for accessing the parallel I / O.

The logic card 1 (2) has a control program for system recognition, and the CPU 8 (8 ') accesses the parallel I / O 4 (5) according to this program.

In FIG. 4, when the logic card 1 (2) is powered on (S1), the CPU 8 (8 ') receives the data in the parallel I / O 4 (5) to which the system recognition signal is input. Is read out via the data signal line 27 (S2). Then, of the read data, the bit to which the system recognition signal is input is checked to see if the system recognition signal is at a high level (S3).

In the case of the active logic card 1, the level of the signal input to the parallel I / O 4 is low, so in this case the CPU 8 determines that the computer 101 is active (S4).

On the other hand, in the case of the standby logical card 2, the level of the signal input to the parallel I / O 5 is high, and in this case, the CPU 8'determines that the computer 111 is the standby system (S5).

CPU8 (8 ') is parallel I / O4
The operation of accessing (5) is as follows.

In FIG. 5, first, the CPU 8 (8 ') outputs the address of the parallel I / O 4 (5) to the address decoding unit 7 (7') via the signal line 21 (S1).
1). The address decoding unit 7 (7 ') inputs this address (S12).

Next, the chip select signal to the parallel I / O 4 (5) is output via the signal line 24 according to the address input to the address decoding unit 7 (7 ') (S13). Then, the chip select signal from the address decoding unit 7 (7 ') is input to the parallel I / O 4 (5), and the parallel I / O 4 (5) can be accessed (S14).

[0037]

According to the present invention, the system recognition signal output means outputs different signals to the system recognition means provided in each of the two systems, so that the system recognition means can accurately perform system recognition. You can

That is, since it is not necessary to use human hands when setting the system, and the system is determined by the system recognition signal output means, it is possible to prevent erroneous recognition of the system due to setting error.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of a system recognition system for a duplex device according to the present invention.

FIG. 2 is a schematic explanatory diagram showing a connection state of a logic card, a board, and a power supply unit.

FIG. 3 is a configuration diagram of a logical card.

FIG. 4 is a flowchart showing the operation of a logical card.

FIG. 5 is a flow chart for accessing parallel I / O.

FIG. 6 is a block diagram of a conventional system recognition system for a duplex device.

[Explanation of symbols]

 1 Operational logic card 2 Standby logic card 3 Board 4,5 Parallel I / O 8,8 'CPU 9,9' Pull-up resistor 30 Short-circuit line 101 Operational computer 104 Power supply unit 111 Standby computer

Claims (4)

[Claims] 1. A system recognition system for system recognition of a duplexer, comprising system recognition signal output means for outputting a signal for recognizing two systems, and system recognition signal output means provided in each system. System recognizing system for recognizing the system based on the system recognizing signal. 2. The system recognition signal output means includes a signal generator and a board to which an output of the signal generator is input, and the system recognition means includes a card to which a signal from the board is input. 2. The system recognizing system for a duplex device according to claim 1, wherein the board outputs the output of the signal generator only to the card of one system. 3. The card includes conversion means for converting a signal for recognizing the two systems, which is input from the system recognition signal output means, into a binary signal, and a conversion means for outputting the binary signal.
3. The system recognition system for a duplex device according to claim 2, further comprising storage means for storing the value signal and processing means for performing system recognition processing based on the binary signal stored in the storage means. 4. The duplex apparatus according to claim 3, wherein the processing means reads out a binary signal stored in the storage means upon power-on and performs system recognition processing based on the binary signal. System recognition system.