JPH09247495A - Clamp circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the response characteristic of a clamp level in an analog signal as against the steep level fluctuation of an analog input signal by controlling the clamp level by means of the value of difference data being a prescribed arithmetic result. SOLUTION: A digital arithmetic processing circuit 10 is constituted of a latch circuit 11, a noise shaping circuit 12, an arithmetic circuit 13, a limitter circuit 14, an integrating circuit 15 and an input encoder circuit 16. Prescribed clamp data is inputted to the arithmetic circuit 13, the clamp data is subtracted from digital data where noise is removed by the noise shaping circuit 12 and difference data being the subtraction result is outputted. A current output-type D/A converter 20 is constituted so as to supply charging/discharging current to a capacitor C1 by current IOUT corresponding to a control signal (pO-PN, NO-NN) from the input encoder circuit 16 and to permit the desired clamp voltage to be impressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clamp circuit, and is particularly suitable for application to an analog / digital converter.

[0002]

2. Description of the Related Art Conventionally, in a television receiver or the like, for example, when an analog video signal is converted into a digital video signal, a stable digital video signal is taken out.
A clamp circuit that clamps an analog video signal input to an analog / digital converter (hereinafter referred to as “A / D converter”) is provided.

FIG. 6 shows an example of a block diagram of a conventional clamp circuit for clamping an analog video signal in a television receiver or the like. In this figure, an analog clamp circuit 100 shown by a one-dot chain line includes capacitors C ₁ and C ₂ , a comparator 101, and a switch circuit 10.
2. The current control circuit 103.

The capacitor C ₁ is a coupling capacitor for removing a DC component from the input analog input signal S ₁ , and the comparator 101 is an analog signal S ₂ whose DC component is cut by the capacitor C ₁ and a reference voltage V 1.
_ref is input and the reference voltage V _ref is compared with the analog signal S ₂ to output a comparison signal A ₁ . The reference voltage V _ref is set to a voltage for clamping the analog signal S ₂ at a predetermined level.

A clamp pulse signal is input to the switch circuit 102 surrounded by a broken line, and ON / OFF of the switch SW is controlled in the timing cycle of the clamp pulse signal. During the period in which the switch SW is ON, the comparator 101 operates. The comparison signal A ₁ is output to the capacitor C ₂ . The cycle of the clamp pulse signal is set according to the timing at which the level of the analog signal S ₂ is constant, for example, the pedestal level. The capacitor C ₂ is a hold capacitor that holds the level of the comparison signal A ₁ input via the switch circuit 102 and outputs the voltage V ₁ .

The current control circuit 103 shown by a broken line is composed of, for example, a CMOS type P-type transistor T _P and an N-type transistor T _N , and the drain terminal of the P-type transistor T _P is connected to the power supply voltage. The drain terminal of the N-type transistor T _N is connected to the ground terminal. Further, the voltage V ₁ held by the capacitor C ₂ is input to each gate terminal, and the P-type transistor T
_P charges the capacitor C ₁ with a current corresponding to the voltage V ₁ , and at the N-type transistor T _N releases the charge of the capacitor C ₁ with a current corresponding to the voltage V ₁ . The A / D converter 1 is configured to A / D convert the analog signal S ₂ output from the analog clamp circuit 100 and output a predetermined digital output signal D.

That is, in the analog clamp circuit 100 thus constructed, for example, the analog signal S
_When the voltage at the clamp point of ₂ is lower than the reference voltage V _ref, the potential of the hold capacitor C ₂ decreases, and the terminal voltage of the coupling capacitor C ₁ increases due to the current supplied via the P-type transistor T _P. At the same time, when the voltage at the clamp point of the analog signal S ₂ is higher than the reference voltage V _ref , the potential of the hold capacitor C ₂ rises, and the current released through the N-type transistor T _N causes the coupling capacitor C ₁ to have a current. The terminal voltage drops and a predetermined clamp voltage is applied to the analog signal S ₂ . Therefore, the analog signal S ₂ clamped by such a clamp circuit is converted to A by the A / D converter 1.
If the D / D conversion is performed, a stable digital output signal D can be obtained by effectively utilizing the dynamic range.

[0008]

In [0007] the analog clamp circuit 100 as described above, when the input signals S ₁ level of the analog fluctuates, clamp the analog signal S ₂ according to the level variation of the input signals S ₁ I am trying to change the clamp level. However,
For example, as shown in FIG. 7, if the level fluctuation range of the analog input signal S ₁ is small, the clamp level of the analog signal S ₂ can be quickly converged to the level corresponding to the input signal S ₁ , but the analog input signal S 1 _For a sharp change of _1, it takes time to converge the clamp level of the analog signal S ₂ to the level corresponding to the analog input signal S ₁ . That is, there is a problem that the response characteristic until the analog signal S ₂ converges to a predetermined clamp level greatly varies depending on the level fluctuation range of the analog input signal S ₁ .

The present invention has been made in order to solve such a problem, and shows the response characteristic of the clamp level of the analog signal input to the A / D converter with respect to the sharp level fluctuation of the analog input signal. It is intended to provide an improved clamp circuit.

[0010]

To achieve the above object, a capacitor for removing a DC component of an input analog input signal, and an analog / digital converter for converting an analog signal supplied via the capacitor into a digital signal. And the difference between the digital data latched with the digital signal at a predetermined timing cycle and the predetermined clamp data is calculated, and the operation of the integration processing of the difference data is controlled by the difference data which is the calculation result, and the n-bit control is performed. The digital arithmetic processing means for outputting a signal and the current output type digital / analog converter for feeding back the current corresponding to the n-bit control signal to the analog signal are provided.

Further, the digital arithmetic processing means calculates a difference between the latch circuit for latching the digital data from the digital signal at the timing cycle of the clamp pulse signal, and the difference between the digital data latched by the latch circuit and the predetermined clamp data, An operation circuit that outputs difference data that is the operation result, a limiter circuit that outputs a clear pulse signal by this difference data, an integration circuit that controls the operation of integration processing of the difference data by the clear pulse signal, and its An input encoder circuit for converting the differential data output from the integrating circuit to an n-bit control signal corresponding to the input form of the current output type digital / analog converter and outputting the n-bit control signal is configured.

According to the present invention, the difference between the digital data and the predetermined clamp data is calculated by the digital calculation processing means, and the integration process is performed depending on whether the difference data as the calculation result is equal to or more than a predetermined value or less than a predetermined value. Since the control is performed, the response characteristic of the clamp level of the analog signal can be improved even when the clamp data is rapidly changed corresponding to the level change of the analog input signal.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below. FIG. 1 shows an example of a block diagram of a digital clamp circuit according to an embodiment of the present invention.
In this figure, a capacitor C ₁ is a capacitor that removes a DC component from the input analog input signal S ₁ . The A / D converter 1 is adapted to A / D convert the analog signal S ₂ from which the DC component has been removed by the capacitor C ₁ and output a predetermined digital output signal D.

The digital arithmetic processing circuit 10 comprises a latch circuit 11, a noise shaping circuit 12, an arithmetic circuit 13, a limiter circuit 14, an integrating circuit 15 and an input encoder circuit 16. The latch circuit 11 receives a clamp pulse signal at a predetermined timing cycle, and latches digital data at a timing cycle when the clamp pulse signal is input from the digital output signal D.

The noise shaping circuit 12 performs noise shaping processing of the digital data latched by the latch circuit 11 in order to remove the influence of noise, and averages the color subcarrier signals existing in this portion, and The quantization noise is pushed to the high frequency side to reduce the noise of digital data. The arithmetic circuit 13 is supplied with predetermined clamp data, subtracts the clamp data from the digital data from which noise has been removed by the noise shaping circuit 12, and outputs difference data that is the subtraction result.

The limiter circuit 14 outputs the input difference data to the integrating circuit 15 and has a predetermined limit value set. When the input difference data is larger than the limit value, the clear pulse signal a is integrated. Output to the circuit 15. The integrating circuit 15 normally integrates the difference data input via the limiter circuit 14 and outputs it to the input encoder circuit 16, and when the clear pulse signal a is input from the limiter circuit 14, the integration circuit 15 stores the integrated data. It is designed to clear data.

The input encoder circuit 16 converts the input difference data into a current output type digital / analog converter (hereinafter referred to as "current output type D / A converter") 20.
Control signals (P _{0 to} P _N ,
N _{0 to NN} ) and output. The current output D / A converter 20 has a current I corresponding to the control signals (P _{0 to} P _N , N _{0 to} N _N ) from the input encoder circuit 16.
A charging / discharging current is supplied to the capacitor C ₁ at OUT, and a desired clamp voltage is applied.

The operation when an analog video signal is input as the analog input signal S _{1 will be described} below with reference to FIGS.
This will be described with reference to FIG. First, when the analog video signal as shown in FIG. 2 (a) is input as the input signal S _1, the DC component is removed by the capacitor C _1. The analog video signal S ₂ from which the DC component is removed is input to the A / D converter 1, where it is A / D converted and output as a digital video signal D.

The digital video signal D is supplied to a subsequent block (not shown) and is also output to the latch circuit 11 of the digital arithmetic processing circuit 10 so that the latch circuit 1
In No. 1, the digital data from the digital video signal D is latched during the period when the clamp pulse signal is turned on. At this time, the clamp pulse signal input to the latch circuit 11 has a cycle t _CL corresponding to the pedestal level of the video signal as shown in FIG. 2B. For example, the clamp pulse signal is a digital signal at a cycle of 4 f _SC. The data is latched and, for example, the data of 8 samples latched by the latch circuit 11 is set to the pedestal level.
The digital data corresponding to the pedestal level may be captured and latched several times during the period when the clamp pulse signal is turned on.

The digital data latched by the latch circuit 11 is input to the noise shaping circuit 12. For example, if the latch circuit 11 latches the digital data several times, the digital data is averaged and then the noise component is obtained. Noise shaping processing for removing the noise is output to the arithmetic circuit 13.

The arithmetic circuit 13 uses the clamp data as clamp data.
Pedestal clamp data for clamping the analog video signal S ₂ at a predetermined pedestal level is input, the difference between the digital data output from the noise shaping circuit 12 and the pedestal clamp data is calculated, and the difference data is the limiter. It is output to the circuit 14.

This difference data is output to the integration circuit 15 via the limiter circuit 14 and compared with the set limiter level. When this difference data is larger than the limiter level, a clear pulse signal is sent to the integration circuit 15. a will be output.

The integrating circuit 15 includes an adder 15a and a D flip-flop circuit (delayed flip-flop circuit) as shown in FIG.
flop) 15b or the like to form an integration loop, and when the difference data is input from the limiter circuit 14, the adder 15a causes the D flip-flop circuit 15b.
The previous output data stored as the integrated data is added and output. That is, in the limiter circuit 14, when the value of the difference data is smaller than the set limiter level V _L , the difference data is integrated by the integrating circuit 15 to eliminate the steady deviation of the clamp level and to output the output data. Output to the input encoder circuit 16.

On the other hand, when the value of the difference data in the limiter circuit 14 is higher than the set limiter level V _{L, the} clear pulse signal a is input from the limiter circuit 14 to the D flip-flop circuit 15b of the integrating circuit 15. The integrated data stored in the D flip-flop circuit 15b is cleared. Therefore, the difference data is not integrated by the integrating circuit 15 and is directly input to the input encoder circuit 1.
6 will be output.

Then, in the input encoder circuit 16, this difference data is converted into predetermined control signals (P _{0 to} P _n , N _{0 to} N _n ) corresponding to the input form of the current output type digital-analog converter circuit 20. For example, when the difference data output from the arithmetic circuit 13 has a positive value, a control signal (P _{0 to} P _n , for lowering the pedestal level of the analog video signal S ₂ by the difference data).
N _{0 to} N _n ) is output to the current output type D / A converter 20.

On the contrary, when the difference data has a negative value, the control signals (P _{0 to} P _n , for increasing the pedestal level of the analog video signal S ₂ by the difference data).
N _{0 to} N _n ) is output to the current output type D / A converter 20.

This control signal (P _{0 to} P _n , N ₀
~ N _n ) based on the current output type D / A converter 20
Current IOU supplied from the analog video signal S _{2 to} the line
As T is controlled and this current IOUT is converted into a current / voltage by the capacitor C ₁ , the analog video signal S ₂ is clamped at a desired clamp level corresponding to the clamp data.

That is, in the digital clamp circuit according to the present embodiment configured as described above, the difference between the digital data of the digital video signal D output from the A / D converter 1 in the digital arithmetic processing circuit 10 and the clamp data. Is calculated, and when the difference data as the calculation result becomes larger than the limiter level V _L set in the limiter circuit 14, the integrating circuit 15 does not perform integration processing,
The difference data is output to the input encoder circuit 16 as it is.

Then, by controlling the current output type D / A converter 20 based on the difference data, the level of the analog video signal S ₁ is largely changed as shown in FIG. 4, so that it corresponds to this level. Even when the reference clamp data is largely changed, the clamp level of the analog video signal S ₂ can be quickly converged to a level corresponding to the analog input signal S ₁ as in the case where the level fluctuation of the analog video signal S ₁ is small. it can.

The limiter level V _L of the limiter circuit 14 includes the capacitor C ₁ , the current output type D / A converter 20, the cycle of the clamp pulse signal, the integration constant of the integrating circuit 15, the resolution of the A / D converter 1 and the like. Considering this, the optimum value may be set.

Next, FIG. 5 shows an example of a 4-bit current output type D / A converter circuit as an example of the current output type D / A converter 20. The 4-bit current output type D / A converter 20 shown in this figure includes a first current generating circuit 21, a second current generating circuit 22, a third current generating circuit 23, and a fourth current generating circuit which are surrounded by broken lines. 24 and a bias control circuit 25. In this case, the control signal from the input encoder circuit 14 of the digital arithmetic processing circuit 10 shown in FIG. 1 is the 4-bit current output type D / A.
A control signal (P _{0 to} P) corresponding to the converter 20.
₃ , N _{0 to} N ₃ ) will be input.

The first current generating circuit 21 is composed of P-type transistors T _P1 and T _P2 and N-type transistors T _N1 and T _N2 . The drain terminal of the P-type transistor T _P1 has a power supply voltage (VDD). A bias voltage is applied to each gate terminal, and a source terminal is connected to a drain terminal of the P-type transistor T _P2 . The input encoder circuit 1 is connected to the gate terminal of the P-type transistor T _P2.
4, the control signal P ₀ corresponding to the first bit of the difference data is input.

On the other hand, the drain terminal of the N-type transistor T _N1 is connected to the ground (VSS), and a bias voltage is applied to the gate terminal. The source terminal is connected to the drain terminal of the N-type transistor T _N2 . In addition, the gate terminal of the N-type transistor T _N2 is
The control signal N ₀ corresponding to the first bit of the difference data is input from the input encoder circuit 14.

The second current generating circuit 22 has the above-described first
Two current generating circuits 21 are connected in parallel, and the gate terminal of each P-type transistor T _P2 is
With control signals P ₁ corresponding from the input encoder circuitry 14 to the second bit of the differential data is input to the gate terminal of each N-type transistor T _N2 is control signal N ₁ corresponding to the second bit of the difference data Has been entered.

The third current generating circuit 23 has the above-mentioned first structure.
4 are connected in parallel, and the gate terminal of each P-type transistor T _P2 has a control signal P ₂ corresponding to the third bit of the difference data.
However, the control signal N ₂ corresponding to the third bit of the difference data is input to the gate terminal of each N-type transistor T _N2 .

The fourth current generating circuit 24 has the above-mentioned first
In the same manner as above, the control signal P ₃ corresponding to the fourth bit of the difference data is transferred to the gate terminal of each P-type transistor T _P2 by the N-type transistor. The control signal N ₃ corresponding to the fourth bit of the difference data is input to the gate terminal of T _N2 . That is, each current generation circuit 21-
24 will be configured to output positive and negative currents weighted by a 4-bit binary code.

The bias controller 25 is adapted to apply a bias voltage to the gate of each P-type transistor T _P1 and the gate terminal of each N-type transistor T _N1.
The bias voltage is set so that the current I _P flowing through the P-type transistors T _P1 is equal to the current I _N flowing through the N-type transistor T _N1 .

A current output type D / having such a configuration
In the A converter 20, for example, the control signal P ₀ of “Low” level is applied to the gate of the P-type transistor T _P2.
When ~ P ₃ is input, the P-type transistor T _P2 is turned on, and the current IOUT is supplied by the transistor T _P1 . At this time, the control signals N _{0 to} N ₃ input to the gate of the N-type transistor T _N2 are
The "Low" level is reached and the N-type transistor T _N2 is turned off.

Further, the N-type transistor T control signal N ₀ to N ₄ gate on the "High" level of _N2 is inputted, the N-type transistor T _N2 is turned on, a current IOUT is extracted by the transistor T _N1 Will be.
At this time, the control signal P ₀ to P ₄ that is input to the gate of the P-type transistor T _P2 becomes "High" level, P-type transistor T _P2 is turned off.

That is, the P-type transistor T _P2 functions as a switch controlled by the control signals P _{0 to} P ₃ and the N-type transistor T _N2 is controlled by the control signals N _{0 to} N ₃ , and each of the P-type transistors T _P1 and N _P1 and N _P2. The type transistor T _N1 weights the amount of current to be output, and outputs a current IOUT according to the control signal.

In the embodiment of the present invention, the case where a 4-bit current output type D / A converter is applied as an example of the current output type D / A converter 20 has been described, but the present invention is not limited to this. Instead, it is naturally possible to use an 8-bit current output type D / A converter or the like. Further, the transistors forming each of the current generating circuits 21 to 24 may be formed of transistors having different current amounts.

[0042]

As described above, according to the clamp circuit of the present invention, the digital arithmetic processing means calculates the difference between the digital data latched with the digital signal at a predetermined timing cycle and the clamp data, and the operation result. Since the clamp level is controlled by the value of the difference data, the clamp action without steady deviation can be provided. Further, since the limiter circuit controls the operation of the integration processing of the difference data, it is possible to improve the response characteristic of the clamp level with respect to the steep level fluctuation of the input signal.

[Brief description of drawings]

FIG. 1 is a diagram showing a block diagram of a clamp circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing waveforms of signals input to the clamp circuit according to the present embodiment.

FIG. 3 is a diagram showing an example of a configuration of an integrating circuit.

FIG. 4 is a diagram showing a response characteristic of the clamp circuit according to the embodiment of the present invention.

FIG. 5 is a diagram showing an example of a current output type D / A converter.

FIG. 6 is a diagram showing an example of a conventional analog clamp circuit.

FIG. 7 is a diagram showing a response characteristic of a conventional analog clamp circuit.

[Explanation of symbols]

1 A / D converter, 10 digital arithmetic processing circuit,
11 latch circuits, 12 noise shaping circuits, 1
3 arithmetic circuit, 14 limiter circuit, 15 integrating circuit,
16 input encoder circuit, 20 current output type D / A converter, 21 to 24 current generating circuit, 25 bias control circuit

Claims (4)

[Claims] 1. A capacitor for removing a DC component of an input analog input signal, an analog / digital converter for converting an analog signal supplied via the capacitor into a digital signal, and a digital signal of a predetermined timing. The difference between the digital data latched in a cycle and a predetermined clamp data is calculated, and the operation of the integration process of the difference data is controlled by the value of the difference data which is the calculation result, and a digital signal that outputs an n-bit control signal is calculated. A clamp circuit comprising: an arithmetic processing unit; and a current output type digital / analog converter for feeding back a current corresponding to the n-bit control signal to an analog signal. 2. The digital arithmetic processing means arithmetically operates a latch circuit for latching digital data from a digital signal at a timing cycle of a clamp pulse signal, and a difference between the digital data latched by the latch circuit and a predetermined clamp data. An operation circuit that outputs difference data that is the operation result, a limiter circuit that outputs a clear pulse signal according to the value of the difference data, and an operation of integration processing of the difference data by the clear pulse signal. And an input encoder circuit for converting the differential data from the integrating circuit into an n-bit control signal corresponding to the input form of the current output type digital / analog converter and outputting the n-bit control signal. The clamp circuit according to claim 1, which is characterized in that 3. The clamp circuit according to claim 2, wherein the digital arithmetic processing means includes a noise shaping circuit for removing a noise component of the digital data. 4. The current output type digital / analog converter has n current generating means, and generates different currents corresponding to respective bits of the n-bit control signal inputted from the respective current generating means. It is constituted so that it may be constituted.
Clamp circuit described in.