JPH09247237A - Protocol processing unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain the protocol processing unit provided with high speed performance being a requirement of a prescribed protocol and flexibility having easiness of provision for revision or the like to the prescribed protocol by allowing the processing unit to conduct stream input and output processing in parallel so as to eliminate the need for undesired transfer from an input side to an output side. SOLUTION: The protocol processing unit PD1 has a buffer memory 1, a write control section 2, a read control section 3, a data memory 4, a syntax processing control section 5, plural input ports 7 and plural output ports 8. Then the high performance is realized by adopting an exclusive use hardware for the write control section 2 and the read control section 3. Moreover, the buffer memory 1 is used in common for both input and output streams to eliminate the need for transfer of the input stream in the buffer memory 1 for the processing of generating the output stream to the buffer memory 1. That is, the protocol processing unit PD1 has flexibility to easily cope with even revision of the syntax.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a protocol processing device having a high speed required for a predetermined protocol and flexibility capable of easily dealing with a change in a predetermined protocol, and more particularly, MPEG2
The present invention relates to a protocol processing device that realizes protocol processing specified by a compliant system part.

[0002]

2. Description of the Related Art Conventionally, data in a plurality of input streams (time-series data) input from a plurality of input ports are assembled, disassembled, inserted, deleted, processed, and rearranged according to a predetermined syntax. And the like (hereinafter, referred to as “syntax processing”), and outputs a plurality of output streams to a plurality of output ports as a complex protocol processing device is configured by the following references (1) and (2). Etc. As the above-mentioned complicated protocol processing device, an implementation method using dedicated hardware and an implementation method using software are known.・ Reference (1) Ichimori et al., "STM-0 / 1 Interface LSI Configuration", IEICE, 1991 Spring National Convention Proceedings, B-769, March, 1991. ・ Reference (2) Douglas Comer, "Internetworking with T
CP / IP: Principales, Protocols, and Architecture ", P
rentice-Hall, Inc, 1988. FIG. 6 is a diagram showing an implementation method of protocol processing by conventional dedicated hardware.

As shown in FIG. 6, the conventional method of implementing protocol processing by dedicated hardware is as follows: m input FIFOs (first in firs) corresponding to a plurality of (m) input ports.
t out control memory), n output FIFOs corresponding to a plurality of (n) output ports, a memory for storing work data for realizing syntax processing, and a syntax processing control unit, It uses a dedicated hardware configuration that faithfully reflects the protocol processing to be realized. Depending on the required performance, it is possible to combine a plurality of inputs into one input FIFO and a plurality of outputs into one output FIFO.

FIG. 7 is a diagram showing a conventional method for implementing protocol processing by software.

In the conventional method of implementing protocol processing by software, the main hardware is only a CPU and a memory. Streams corresponding to a plurality of input ports and a plurality of output ports are expanded in different address spaces on one memory. The protocol processing program on the workstation corresponds to the protocol processor.

In the conventional protocol processing devices such as the "implementation method by dedicated hardware" and the "implementation method by software", when a complicated and still fluid protocol like the MPEG2 system part is realized, When realizing a high-speed protocol that requires real-time processing, there are the following problems.

The MPEG2 system part, MPE
The G2 video stream and the MPEG2 audio stream are specified in the following documents (3), (4) and (5), respectively.・ Reference (3) Systems-Generic Coding of Moving Pictu
res and Associated Audio-ISO / IEC 13818-1 Internati
onal Standard, November 11, 1994. ・ Reference (4) Video-Generic Coding of Moving Picture
s and Associated Audio-ISO / IEC 13818-2 Internation
al Standard, November 11, 1994. -I Reference (5) Audio-Generic Coding of Moving Picture
s and Associated Audio-ISO / IEC 13818-3 Internation
al Standard, November 11, 1994. Most relevant to this patent relates to the MPEG2 system part of document (3).

[0008]

FIG. 8 is a diagram showing the concept of the hierarchical packet structure in the system part of MPEG2. FIG. 8 shows the transport stream and the program stream data, and the video / audio / user stream defined by the MPEG2 system part is referred to as Multiplexer (MUX) and demultiplexer:
It is a figure which shows the concept of (DMUX).

The MPEG2 system part is referred to as a transport stream used for communication media and a program stream for storage media, among the regulated streams. The syntax of these streams specified by the MPEG2 system part is shown in FIG.
As shown in, the hierarchical packet structure is used, and the processing is complicated because the stream syntax is data-dependent. In order to realize real-time processing, syntax one path analysis is indispensable. There is a common feature called. On the other hand, the syntax is
It is different as shown in FIG.

The realization by the dedicated hardware is a faithful hardware implementation of the protocol model, and has an advantage that the theoretical high speed can be obtained by the distributed processing. However, when implementing a complicated and fluid protocol such as MPEG2, there is a problem that the hardware becomes complicated and the flexibility becomes poor.

That is, the syntax defined by the MPEG2 system part is complicated in analysis as described above,
Since one-path analysis of syntax is indispensable, if these are realized by dedicated hardware, the syntax processing will be extremely complicated and a huge state machine will be realized, making it difficult to realize hardware. . Also, individual internal FIFOs depending on the input / output ports are required, and there are many resource parameters such as the size of these FIFOs. As described above, in the case of implementation by dedicated hardware, the problem that the hardware becomes complicated and lacks flexibility is highlighted.

On the other hand, in software implementation, MP
There is a problem that real-time processing defined by the EG2 system part is impossible. In other words, the software implementation is a software implementation of the protocol model, has few resource parameters, and can be used for complex syntax control and fluid specifications.
It has the advantage of having high flexibility. However, MPE
To process the multiplexing / separation of compressed data such as video (moving image) and audio specified by G2 in real time, several thousand M is required.
Processing performance exceeding IPS is required, and even if the current fastest processor (CPU) and memory are used, it is impossible to perform the multiplexing / separation in real time by software alone. As described above, the problem that real-time processing defined by the MPEG2 system part is impossible in software implementation is highlighted.

As described above, the above problems in the case where the protocol processing defined by the MPEG2 system part is realized by the conventional protocol processing apparatus such as "realization method by dedicated hardware" and "realization method by software" The same applies to various types of high-speed and high-performance protocol processing that will be developed, and in consideration of future development of various applications on the network, it will become an increasingly serious problem in the future. That is, a protocol processing device based on a new technology that achieves both high speed and flexibility is essential. However, conventionally, the above-mentioned document (1),
Even the above problem has not been pointed out, which is limited to realizing the protocol processing device shown in (2).

An object of the present invention is to provide a protocol processing device having both high speed required for a predetermined protocol and flexibility capable of easily dealing with a change in a predetermined protocol. . In particular, it is an object of the present invention to provide a protocol processing device suitable for implementing the protocol processing defined by the MPEG2-compliant system part.

[0015]

SUMMARY OF THE INVENTION The present invention is directed to assembling data in a plurality of input streams input from a plurality of input ports according to a predetermined syntax.
In a protocol processing device that performs processing (syntax processing) such as disassembly, insertion, deletion, processing, and rearrangement, and outputs as a plurality of output streams to a plurality of output ports, 2
A buffer memory configured by a port memory for storing a part of the input / output stream, a write control unit for controlling an operation of writing the plurality of input streams to the first port of the buffer memory, and a second memory of the buffer memory. Read control unit for controlling the operation of reading a plurality of output streams from the port, a data memory configured by a 2-port memory for temporarily storing work data for executing syntax processing, and a buffer memory in the buffer memory. And a programmable syntax processing control unit that implements processing for referring to and reading data, implementing the syntax processing using the data memory, and writing the syntax-processed data in the buffer memory, It is a protocol processing device that realizes a predetermined protocol process.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram showing a protocol processing device PD1 which is a first embodiment of the present invention.

The protocol processing device PD1 includes a buffer memory 1, a write control unit 2, a read control unit 3, a data memory 4, a syntax processing control unit 5, and a plurality (m).
The number of input ports 7 and the number (n) of output ports 8 are provided.

The buffer memory 1 is a buffer memory which is composed of a two-port memory and stores a part of the input / output stream. The write control unit 2 is a write control unit that controls an operation of writing a plurality of input streams to the first port of the buffer memory 1, and the read control unit 3 controls a plurality of output streams from the second port of the buffer memory 1. It controls the operation of reading to a stream. The data memory 4 is composed of a two-port memory, and is a memory for temporarily storing work data for syntax processing.

The syntax processing control unit 5 refers to the data in the buffer memory 1, reads the data, implements the syntax processing using the data memory, and writes the syntax-processed data into the buffer memory 1. Is a programmable controller.

The protocol processing device PD1 in which the syntax processing control unit 5 is configured by a central processing unit (CPU) is a second embodiment of the present invention.

The protocol processing device PD1 introduces parallel processing by memory distribution. That is, by separating the buffer memory 1 and the data memory 4, the stream input / output processing and the syntax processing are parallelized. In addition, the buffer memory 1 and the data memory 4 are 2
By porting, access from hardware and software is parallelized, and stream input processing and output processing are parallelized, thereby eliminating unnecessary transfer from the input side to the output side.

In FIG. 1, the upper and lower parts of the horizontal broken line operate independently of each other. That is, a set including the buffer memory 1, the write control unit 2, and the read control unit 3,
The set composed of the data memory 4 and the syntax processing control unit 5 operate independently of each other.

FIG. 2 is a diagram showing a basic operation outline of the above embodiment.

For comparison, an outline of operation in the case of a software-implemented system is also shown. In the case of realization by software, it takes a long time because each process in the figure is processed by software, and further, since each process operates sequentially, a huge amount of time is required.

However, in the above-described embodiment, it is possible to operate at extremely high speed by using dedicated hardware for each processing unit and their parallel pipeline operations.

Since the read control unit 3 and the write control unit 2 are implemented as dedicated hardware, the same high speed as the high-speed input / output control when the whole is implemented as dedicated hardware is realized. In addition, by using the buffer memory 1 having two ports, the syntax processing by software and the input / output processing by dedicated hardware can be operated in parallel. In addition, by using the data memory 4 having two ports, the transfer from the buffer memory 1 to the data memory 1 and, conversely, the transfer of data from the data memory 4 to the buffer memory 1 are parallelized.

Further, by making the buffer memory 1 for the input / output stream common, the operation of transferring the input stream in the buffer memory 1 to the output stream in the buffer memory 1 becomes unnecessary. For example, MPE
In the multiplexing (MUX) processing of the G2 system part, most of the input stream is added with a header and the like, and is included in the output stream. That is, when the input / output buffer is separated, unnecessary transfer during this time frequently occurs. These series of operations enable parallel pipeline processing as shown in FIG. 2 as a whole. In the above embodiment, the speed can be increased by several tens or more times as compared with a method in which the whole is processed by software.

Next, taking the multiplexing process of the MPEG2 system part as an example, the overall operation outline of the above embodiment will be described in more detail. In this case, three streams of video, audio, and user (elementary streams) are taken as an example of an input stream, and a transport is taken as an example of an output stream.

The light controller 2 (dedicated hardware) is
Video, audio, and user data are input from the input port 7, and the input data are stored in different address spaces of the buffer memory 1. In this case, the buffer address (start and end addresses) of each data and a predetermined header are searched, and the existing address is notified to the CPU.

The syntax processing control unit 5 creates predetermined headers of each elementary stream according to the notification from the write control unit 2 and the reference to the above elementary streams, and sets a predetermined address space of the buffer memory 1. And notifies the read control unit 3 of the length of the headers. In the second embodiment, the syntax processing control unit 5 is composed of a CPU, but in reality,
The syntax processing control is executed by the CPU + software (program).

The read controller 3 (dedicated hardware) is
According to the notification from the syntax processing control unit 5, the headers in the buffer memory 1 and a predetermined elementary stream obtained by subtracting the length of the headers from the predetermined packet length are sent to the output port 8. Buffer memory 1
Stores a part of the input / output stream according to the operations of the write controller 2, the read controller 3, and the syntax processing controller 5. The data memory 4 has a syntax processing control 6
Stores temporary work data in.

Each processing unit repeatedly executes the above operation, realizes the multiplexing processing of the input stream defined by the MPEG2 system part, and sends the output stream.

FIG. 3 shows that in the above embodiment, MPEG2 is used.
FIG. 4 is a diagram illustrating an example of use of a buffer memory 1 used when implementing two processes (transport stream processing for communication media and program stream processing for storage media) defined by a system part.

The difference between the transport stream processing and the program stream processing is defined in the MPEG2 system part, but the syntax thereof differs depending on the purpose of use (communication / storage).
What is important here is that if the input / output timings of the input / output streams are the same, the protocol processing of different syntax can be realized by the same hardware only by changing the usage method (memory map) of the buffer memory 1. It is. That is, the protocol processing device PD1
Has the flexibility to easily handle changes in syntax.

As described above, the protocol processing device PD1
Enables the high speed operation shown in FIG. 2 and the flexibility shown in FIG. That is, the protocol processing device PD1 has both high speed required for a predetermined protocol and flexibility capable of easily coping with a change of the predetermined protocol.
That is, it is possible to achieve both the high speed that the “dedicated hardware processing method” of the conventional protocol processing device has and the flexibility that the “software processing method” has. This makes it possible to easily realize a high-speed protocol that is complex, still fluid, and requires real-time processing, such as the MPEG2 system part.

In the second embodiment, the programmable syntax processing control section 5 is composed of a CPU, but the programmable syntax processing control section 5 may be composed of a program logic device. This is the third embodiment of the present invention. In the case of the third embodiment, the software portion in the above embodiment is read as a program logic device.

As the predetermined protocol, MPEG is used.
A protocol defined by the two system parts may be used and processed, which is a fourth embodiment of the present invention.

FIG. 4 shows an MU which is a fifth embodiment of the present invention.
It is a figure which shows the typical structure of the encoder system of MPEG2 using X.

The MUX of the fifth embodiment is an example applied to the multiplexing process as a special case of the fourth embodiment.

MPEG2 as a plurality of input streams
It handles compliant video streams, audio streams, and user streams, and handles a plurality of output streams such as transport streams or program streams. In FIG. 4, the MUX according to the fifth embodiment multiplexes three streams of video, audio, and user (referred to as “elementary stream”), and outputs one transport or program stream (a protocol processing device ( Multiplexer: MUX).

FIG. 5 is a DM showing a sixth embodiment of the present invention.
It is a figure which shows the typical structure of the decoder system of MPEG2 using UX. The sixth embodiment is an example applied to the separation processing as a special case of the fourth embodiment.

MPEG2 as a plurality of input streams
It handles compliant transport streams or program streams, and handles video streams, audio streams, and user streams as multiple output streams. In FIG. 5, the DMUX according to the sixth embodiment of the present invention separates one transport or program stream,
It is a protocol processing device (Demultiplexcer: DMUX) that outputs three streams of video, audio and user.

Thus, as is apparent from FIGS. 4 and 5, the multiplexing process (MU) of the MPEG2 system part is performed.
X) and the demultiplexing process (DMUX) are different in the operation of each protocol processing device, and the input / output specifications are different depending on each application. Therefore, the write control unit 2 and the read control unit 3 are different dedicated ones. Although it is hardware, the protocol processing device PD1 itself shown in FIG. 1 can be commonly used. Therefore, the above embodiment is highly flexible to different protocols.

Since the protocol processing device PD1 has both the high speed required for a predetermined protocol and the flexibility to easily deal with the change of the predetermined protocol, the input / output specifications depending on the application are required. Absorb write / read controller (number of ports, input / output timing,
The configuration of the input / output rate, etc.) may be set as necessary. For example, dedicated hardware may be used, or a program logic device may be used depending on the input / output rate desired to be realized. Further, in the above embodiment, the programmable syntax processing control unit 5 that realizes the syntax processing is composed of a CPU, but CP
The syntax processing control unit 5 may be configured by a component other than U. Furthermore, in the above embodiment, MPEG2 is applied as the type of protocol, but MPEG2
Other protocols may be applied.

The key point of the above embodiment is "introduction of parallel processing by memory distribution". In other words, the above embodiment is a memory-based general-purpose protocol processor configuration method for realizing a general-purpose protocol processor. (A Me
mory-based Protocol Processor Architecture). That is, the configuration method of the protocol processing device centering on the memory, the CPU, and the dedicated hardware for input / output is shown. Such a device configuration centering on a memory and a CPU can directly benefit from the continuous development of VLSI technology, in particular, speeding up of memory, increasing capacity, and speeding up of CPU. Further, it is possible to have a promising device configuration in the future, such as simplification and generalization of the configuration of the protocol processing device.

Further, as described above, even when the structure of the protocol processor centering on the CPU and the memory is implemented on VLSI, today, due to the progress of VLSI technology, a high-speed on-chip built-in CPU
Since a (high-speed, large-capacity, on-chip two-port memory, etc.) is supplied as a VLSI library (which will be referred to as a "core CPU"), one-chip VLSI can be easily realized. As described above, the above-described embodiment has a configuration that can be easily realized as a VLSI, and by using the VLSI, the size and cost can be reduced as compared with the conventional protocol processing device.

Further, in the above embodiment, the buffer memory for the input / output stream is shared, so that it is not necessary to transfer the input stream in the buffer memory to the output stream in the buffer memory. For example, in the multiplexing (MUX) processing of the MPEG2 system part, most of the input stream is included in the output stream with headers and the like added. That is, when the input / output buffer is separated, unnecessary transfer frequently occurs during this period.

Furthermore, the above embodiment is an extremely general-purpose and general protocol processing device that does not depend on the type of protocol or application. The syntax processing part, which is the most important part of the protocol, is programmable, so it will be extremely effective as a test bed for protocol development and experimentation.

The above embodiment has a very simple structure as a protocol processing device. When implemented on VLSI, the core CPU, 2-port memory, etc. can be provided as a library. Therefore, when implementing the above-described embodiment, only the read control unit and the write control unit from the input / output port to the buffer memory are dedicated hardware. All you have to do is Although these input / output processes depend on the application, they can be realized very easily by the recent logic synthesis technology.

As described above, since the above-described embodiment has an extremely simple structure based on the components made into a library (parts), it is applicable to a high-level synthesis technique (for example, system level synthesis) in the VLSI design technique. It is extremely effective as a certain target architecture, and will benefit from higher-level synthesis technology, and in the near future, it will be possible to automatically synthesize a protocol processing device based on the above-described embodiment from a high-level specification description into VLSI.

As described above, in the multimedia era based on future network technology, the role of the new protocol processing device, which achieves "combination of high speed and flexibility" provided by the above embodiment, is aimed at. I don't know.

[0052]

According to the present invention, in the protocol processing device, it is possible to have both the high speed required for a predetermined protocol and the flexibility to easily deal with the change of the predetermined protocol. Played, especially MPE
This has the effect of being suitable when implementing the protocol processing specified by the G2-compliant system part.

[Brief description of drawings]

FIG. 1 is a diagram showing a protocol processing device PD1 according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a basic operation outline of the above embodiment.

FIG. 3 shows an example of use of the buffer memory 1 used to realize two processes (transport stream process for communication media and program stream process for storage media) defined by the MPEG2 system part in the above embodiment. FIG.

FIG. 4 is a block diagram illustrating an MUX according to a fifth embodiment of the present invention,
It is a figure which shows the typical structure of the encoder system of PEG2.

FIG. 5 is an MPE using the sixth embodiment of the present invention.
It is a figure which shows the typical structure of the decoder system of G2.

FIG. 6 is a diagram showing an implementation method of protocol processing by conventional dedicated hardware.

FIG. 7 is a diagram showing an implementation method of protocol processing by conventional software.

FIG. 8 is a conceptual diagram of a hierarchical packet structure in a system part of MPEG2.

[Explanation of symbols]

 1 ... Buffer memory, 2 ... Write control unit, 3 ... Read control unit, 4 ... Data memory, 5 ... Syntax processing control unit, 7 ... Multiple (m) input ports, 8 ... Multiple (n) outputs port.

Claims (6)

[Claims] 1. The data in a plurality of input streams input from a plurality of input ports are subjected to processing such as data assembling, disassembling, inserting, deleting, processing, rearranging, etc. according to a predetermined syntax to obtain a plurality of data. In a protocol processing device for outputting a plurality of output streams to an output port, a buffer memory configured with a two-port memory and storing a part of an input / output stream; and the plurality of input streams to a first port of the buffer memory. A write control unit for controlling a writing operation; a read control unit for controlling an operation for reading a plurality of output streams from the second port of the buffer memory; a two-port memory, which is used to execute syntax processing A data memory for temporarily storing data; referencing and reading data in the buffer memory, A programmable syntax processing control unit that realizes the syntax processing using the data memory and writes the syntax-processed data in the buffer memory; and executes a predetermined protocol processing. A protocol processing device characterized by being realized. 2. The programmable syntax processing control unit according to claim 1, wherein
A protocol processing device characterized in that a CPU is used. 3. The programmable syntax processing control unit according to claim 1, wherein
A protocol processing device characterized in that a field program device is used. 4. The protocol processing device according to claim 1, wherein a protocol defined by an MPEG2 system part is used as the predetermined protocol and processes the protocol. 5. The MPEG4 compliant video stream, the audio stream, and the user stream are handled as the plurality of input streams, and the transport stream or the program stream is handled as the plurality of output streams. Protocol processor. 6. The MPEG2 compliant transistor port stream or program stream is handled as the plurality of input streams, and a video stream, an audio stream, and a user stream are handled as the plurality of output streams. Protocol processing device.