JPH09247222A - Receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a receiver which can estimate line quality that is more accurate than before at a high speed by estimating the line quality by using phase likelihood and a difference in amplitude value between a received signal and a signal point. SOLUTION: A detector 102 detects and converts a received signal 101 from an antenna into a bit array. A phase likelihood calculator 103 converts the bit array outputted from the detector 102 into signal points to find the phase likelihood with the receive signal. A 1st storage device A107 stores likelihood of M symbols so as to level the output of the phase likelihood calculator 103, and a mean value calculator 108 outputs its mean value. A 2nd storage device B105 stores a conversion table for converting the phase likelihood calculated by simulation or on the basis of measurement data into error rate characteristics showing the line quality, and an address converter 104 converts the output of the mean value calculator 108 into an address in the 2nd storage device B105, thereby outputting an error rate indicating the line quality.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiver used in a digital wireless communication system, and more particularly, to accurate estimation of channel quality at high speed by using a phase likelihood or a difference in amplitude value between a received signal and a signal point. The present invention relates to a receiving device that can perform.

[0002]

2. Description of the Related Art A block diagram of a conventional receiver is shown in FIG. A conventional receiver uses a detector 602 that detects a received signal that is a baseband symbol string and converts it into a bit string of 0 and 1, and a bit string that is output from the detector using redundant bits such as CRC and parity. An error determiner 603 that determines whether or not an error has occurred in the burst, an address converter 604 that converts the output of the average value calculator to an address in the storage device B in which the error rate is stored, a simulation or A storage device B605 that stores a conversion table from the output of the error determiner calculated based on the actual measurement data to the error rate characteristic indicating the line quality, and the output of the error determiner are averaged, and therefore the memory for the previous M slots is stored. The storage device A 607 stores the error determination result, and the average value calculator 608 averages the error determination results stored in the storage device A.

In the following, a case will be described in which the modulation format is QPSK and the data is communicated as shown in FIG. 5 in the frame format as shown in FIG. 2, but in the case of other frame formats, modulation methods and data. Is also the same. In FIG. 2, the frame format is a data bit 201 to be communicated and a parity bit for checking that makes the number of 1's in the data slot become an even number.
It consists of 202.

In FIG. 5, as the transmission signal sequence, the T-th data slot S (T) transmitted at time T
501, T + 1th data slot S (T + 1) 502 transmitted at time T + 1, T + 2nd data slot S (T + 2) 503 transmitted at time T + 2, and time T +
T + th third data slot S (T
+2) 504 are shown respectively, and as the received signal sequence,
Tth data slot R received at time T
(T) 505, T + 1th data slot R (T + 1) 506 received at time T + 1, T + 2nd data slot R (T + 2) 507 received at time T + 2, and T + 3 received at time T + 3. The th data slot R (T + 3) 508 is shown respectively.

Here, it is assumed that the time takes discrete values of the data slot timing, and the delay due to transmission is not considered.

When a data slot such as 501 in FIG. 5 is transmitted, the received signal 601 in FIG.
become that way. In FIG. 3, reference numeral 301 denotes the first received symbol R0 (T) in the data slot.
2 is the second received symbol R1 (T) in the data slot, and 303 is the third received symbol R2 (T) in the data slot.

When a reception signal as shown in FIG. 3 is given, the detection circuit 602 corrects the reception data slot "00111".
1 "is output. Since the number of bits of 1 in the received data slot is 4 (even number), the error determiner 603 outputs 0 and stores it in the storage device A. The average value calculator 608 calculates the average of the values stored in the storage device A and calculates the address converter 604.
Output to The address converter 604 converts into an address in which an error rate corresponding to the output of the average value calculator is stored.

The conventional receiving apparatus repeats this operation to identify the bit string. Let us consider a case where at time T + 2, a signal as shown in FIG. 4 is received as a received signal due to the influence of noise. In FIG. 4, 401 represents the first received symbol R1 (T + 2) in the data slot.
Is the second received symbol R2 (T + 2) in the data slot
403 is the third received symbol R in the data slot
3 (T + 2), respectively.

At this time, the detector 602 shown in FIG. 6 erroneously determines that "111011" is received as the data slot and outputs it. Since the number of 1 bits in the received data slot is odd, the error determiner 603 outputs 1 and stores it in the storage device A 607. The average value calculator 608 is a storage device A607.
The average value is output, the address converter 604 gives the address in the storage device corresponding to the value to the storage device B605, and the storage device B605 outputs the error rate stored at the specified address to the current line. Output as a value indicating quality.

It is assumed that the average value calculator 608 outputs the average value of four slots, and if the T + 3rd slot of 504 is received, the only erroneously received slot is the T + 2nd slot. Outputs 1/4. The address converter 604 gives the address in the storage device corresponding to the value to the storage device B605, and the storage device B605.
Outputs the error rate stored in the specified address as a value representing the current line quality.

The conventional receiving apparatus estimates the line quality as described above.

[0012]

However, in the case of estimating the line quality using the above-mentioned conventional method, the information on the distance between the signal point and the received signal is lost at the time when the information is judged from the received signal and obtained. Therefore, it is impossible to accurately estimate the line quality. Further, when the channel error rate is low, it is necessary to average many slots, which causes a problem that it takes time to estimate the channel quality.

The present invention solves the above-mentioned problems of the prior art, and estimates the quality of the line by using the difference between the phase likelihood and the amplitude value of the received signal and the signal point so that the line is more accurate than the conventional one. An object of the present invention is to provide a receiving device that can estimate quality at high speed.

[0014]

In order to achieve the above object, the invention according to claim 1 is a detector for detecting a received signal from an antenna and converting it into a bit string, and a received signal from the detected antenna. A phase likelihood calculator for obtaining a phase likelihood between signal points, a first storage device and an average value calculator for averaging the outputs of the phase likelihood calculator, and a line quality from the phase likelihood. A second storage device for storing a conversion table to the error rate characteristic and an address converter for converting the output of the phase likelihood calculator into an address in which the error rate characteristic indicating the line quality is stored.

In the configuration of such a receiving device, this receiving device has an effect that the channel quality can be estimated more quickly and more accurately than the conventional receiving device by using the phase likelihood information.

Further, by not using the amplitude information of the received signal but estimating the channel quality only by using the phase likelihood information, it is possible to significantly reduce the amount of calculation, and the signal processing cannot be performed using the DSP or the like. It has an effect of enabling the estimation of the line quality even at an extremely high transmission rate.

Further, the invention according to claim 2 detects a received signal from the antenna and converts it into a bit string, and a phase likelihood and an amplitude error between the detected received signal from the antenna and the signal point. An error calculator to be obtained, a first storage device and an average value calculator for averaging the outputs of the error calculator, and a conversion table from the error calculated by the error calculator to the error rate characteristic indicating the line quality are provided. A second storage device for storing the data and an address converter for converting the output of the error calculator into an address in which the error rate characteristic indicating the line quality is stored.

In this configuration of the receiving apparatus, since the receiving apparatus estimates the channel quality using both the amplitude information and the phase likelihood information, the channel quality can be estimated more accurately than the receiving apparatus. Has the effect of becoming.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram of a receiving apparatus showing a first embodiment of the present invention. In FIG. 1, the receiving device includes a detector 102 that detects a received signal that is a baseband symbol string and converts it to a bit string of 0 and 1, and a bit string that is output from the detector to a signal point for reception. The phase likelihood calculator 103 for obtaining the phase likelihood with the signal, and the second storage device B from the output of the average value calculator.
An address converter 104 that performs conversion into an address in which the error rate is stored, and a conversion table that stores the conversion rate from the phase likelihood calculated based on simulation or actual measurement data to the error rate characteristic indicating the line quality. 2 storage device B105 and the first storage device A107 that stores the phase likelihoods of the previous M symbols for averaging the outputs of the phase likelihood calculator, and the phase stored in the first storage device A. And an average value calculator 108 for averaging the likelihoods.

Here, the frame format shown in FIG.
Although QPSK is used as a modulation method and synchronous detection is used as a detection method, the present invention is also effective when another modulation method or differential detection is used.

The case of the slot transmitted at time T + 2 in FIG. 8 will be described as an example. 801 is the symbol R0 (T + 2) received first in the T + 2nd slot, and 802 is the second received symbol R1 (T + T + T in the T + 2nd slot.
2), and 803 represents the third received symbol R2 (T + 2) in the T + 2nd slot.

Reference numeral 804 denotes the original signal point position S0 (T + 2) of the symbol transmitted first in the T + 2nd slot.
805 is the original signal point position S1 (T + 2) of the second transmitted symbol in the T + 2nd slot, and 806 is the original signal point position of the third transmitted symbol in the T + 2nd slot. S2 (T + 2) is shown.

From the first received symbol R0 (T + 2), the detector 102 outputs the bit string "11". Phase likelihood calculator 1
03 obtains the transmission symbol S0 (T + 2) from the bit string “11”, and the phase likelihood with the reception symbol R0 (T + 2) | rad (R0 (T
+2))-rad (S0 (T + 2)) | to obtain the first storage device A1
Save to 07. If the channel quality is estimated by averaging every 3 symbols, the phase likelihood for 3 symbols will be stored in the first storage device A 107. The output of the average value calculator is 1/3 · Σ | rad (Rx (T + 2))-rad (Sx (T + 2)) |. Here, x takes an integer value of 0 to 3,
rad (x) represents the phase of the complex number x.

The address converter 107 converts the average value of the phase likelihoods into the address of the second storage device B in which the error rate is stored. The second storage device B105 outputs the value stored in this address as an error rate indicating the line quality. The conversion table from the phase likelihood to the address of the second storage device B in the address converter 107 can be configured by simulation or actual measurement data.

FIG. 9 shows that the modulation method is QPSK, the line qualities of various error rates are created by parameterizing the influence of noise and interference waves, and the average likelihood of 500 symbols at that time is measured 9 times by simulation. It was done. The horizontal axis represents the line error rate, and the vertical axis represents the phase likelihood in degrees. As shown in FIG. 9, since it is considered that the phase likelihood is almost constant in each channel situation if the average of 500 symbols is used, the second storage device B105 in which the error rate is stored from the phase likelihood based on this table. It is possible to convert the average phase likelihood into an error rate representing the line quality by providing the address converter 104 with a table for converting the medium address. Here, an example of 500-symbol averaging is shown, but if the averaging is performed in a shorter section, the accuracy becomes lower, but at a higher speed, and conversely, if the averaging section is made longer, it is possible to perform highly accurate line quality estimation.

(Second Embodiment) FIG. 7 is a block diagram of a receiving apparatus showing a second embodiment of the present invention. In FIG. 7, a receiving apparatus includes a detector 702 that detects a received signal that is a baseband symbol string and converts it into a bit string of 0 and 1, and a bit string that is output from the detector into a signal point and receives it. An error calculator 703 for obtaining an error in phase likelihood and amplitude with a signal, and an address converter 704 for converting an output of the average value calculator to an address in the second storage device B in which an error rate is stored. , A second storage device B705 that stores a conversion table from an error calculated based on simulation or actual measurement data to an error rate characteristic indicating the line quality.
And a first storage device A707 that stores the error calculation result for the previous M symbols in order to average the output of the error calculator,
An average value calculator 708 for averaging the error calculation results stored in the first storage device A.

Here, the frame format shown in FIG.
Although QPSK is used as a modulation method and synchronous detection is used as a detection method, the present invention is also effective when another modulation method or differential detection is used.

The case of the slot transmitted at time T + 2 in FIG. 8 will be described as an example. 801 is the symbol R0 (T + 2) received first in the T + 2nd slot, and 802 is the second received symbol R1 (T + T + T in the T + 2nd slot.
2), and 803 represents the third received symbol R2 (T + 2) in the T + 2nd slot.

804 is the original signal point position S0 (T + 2) of the symbol transmitted first in the T + 2nd slot.
805 is the original signal point position S1 (T + 2) of the second transmitted symbol in the T + 2nd slot, and 806 is the original signal point position of the third transmitted symbol in the T + 2nd slot. S2 (T + 2) is shown.

From the first received symbol R0 (T + 2), the detector 702 outputs the bit string "11". The error calculator 703 obtains the transmission symbol S0 (T + 2) from the bit string “11”,
A composite error | R0 (T + 2) · S0 * (T + 2) | of the phase likelihood and amplitude difference with the received symbol R0 (T + 2) is obtained and stored in the first storage device A707. Here, S0 * (T + 2) is S0 (T
+2) represents the conjugate complex number.

If the line quality is estimated by averaging every 3 symbols, the error of 3 symbols will be stored in the first storage device A707. The output of the average value calculator is 1/3 · Σ | Rx (T + 2) · Sx * (T + 2) |. Here, x takes an arbitrary integer value from 0 to 3.

The address converter 704 converts the average value of this error into the address of the second storage device B in which the error rate is stored. The second storage device B705 outputs the value stored in this address as an error rate representing the line quality. The conversion table from the error to the address of the second storage device B in the address converter 704 can be configured by simulation or actual measurement data as in the first embodiment.

[0034]

As described above, the receiving apparatus of the present invention estimates the channel quality using both the phase likelihood between the received signal and the signal point, or both the phase likelihood and the amplitude value difference between the received signal and the signal point. Therefore, it is possible to more accurately estimate the line quality at a higher speed than the conventional receiving device. Further, since the line quality can be estimated at high speed by using the receiving apparatus of the present invention, for example, the modulation scheme is changed according to the estimated line quality, or the coding rate is lowered when the estimated line quality is poor. Data communication can be performed, error correction capability can be enhanced, and the effect of effectively using the line can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of a receiving device according to a first embodiment of the present invention;

FIG. 2 is a diagram showing a frame format of a transmission signal used in the present invention,

FIG. 3 is a diagram in which a received signal when a T-th slot is received in the data communication example shown in FIG. 5 is expressed in a complex plane;

FIG. 4 is a diagram in which a received signal when the T + 2 th slot is received in the data communication example shown in FIG. 5 is expressed in a complex plane;

FIG. 5 is a diagram showing an example of data communication used for explaining a conventional example;

FIG. 6 is a block diagram of a conventional receiving device,

FIG. 7 is a block diagram of a receiving device according to a second embodiment of the present invention,

FIG. 8 is a diagram in which a received signal used to describe the present invention is expressed in a complex plane;

[FIG. 9] The horizontal axis represents the line error rate, and the vertical axis represents the phase likelihood.
It is a figure which shows the relationship of the phase likelihood and channel quality represented by.

[Explanation of symbols]

 101, 601, 701 Received signal from antenna 102, 602, 702 Detector 103, 603 Phase likelihood calculator 104, 604, 704 Address converter 105, 605, 705 Second storage B 106, 606, 706 Line Quality estimation value 107, 607, 707 First storage device A 108, 608, 708 Average value calculator 703 Error calculator

Claims (2)

[Claims] 1. A detector for detecting a received signal from an antenna and converting it into a bit string, a phase likelihood calculator for obtaining a phase likelihood between the detected received signal from the antenna and a signal point, and the phase likelihood A first storage device and an average value calculator for averaging the output of the degree calculator; a second storage device for storing a conversion table from the phase likelihood to the error rate characteristic indicating the channel quality; An address converter that converts an output of the likelihood calculator into an address in which an error rate characteristic indicating line quality is stored, and a receiving device. 2. A detector for detecting a received signal from an antenna and converting it into a bit string, an error calculator for obtaining a phase likelihood and an amplitude error between the detected received signal from the antenna and a signal point, and the error. A first storage device for averaging the outputs of the calculator and an average value calculator; and a second storage for storing a conversion table from the error calculated by the error calculator to an error rate characteristic indicating the line quality. A receiving device comprising: a device; and an address converter that converts an output of the error calculator into an address in which an error rate characteristic indicating line quality is stored.