JPH09247122A - Receiver and receiving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To correctly and easily generate a window synchronization signal in a DAB system receiver. SOLUTION: A tuner 2 extracts a desired signal from an RF signal which is received by an antenna 1 and an IF circuit 3 extracts I data and Q data. I data and Q data are supplied to a null signal detecting circuit 71, the null signal is detected and a time base circuit 7b generates a timing signal for generating a window by synchronizing with the timing of the detected null signal. A window generating circuit 7c synchronizes with the timing signal which is supplied from the time base circuit 7b so as to generate the window synchronization signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiving apparatus and a receiving method, and more particularly to a receiving apparatus and a receiving method for receiving an OFDM modulated signal which is modulated by the OFDM method.

[0002]

2. Description of the Related Art Conventionally, when transmitting a digital signal, one carrier wave is provided, and the digital signal is modulated by changing the phase and amplitude of the carrier wave at high speed corresponding to the input digital signal. . Phase modulation (PSK: Phase Sh) is used as a method of changing only the phase (when assigning a digital signal as an information sequence to only the phase).
quadrature modulation (QA) is a method for changing both amplitude and phase (a method for allocating a digital signal as an information sequence to both phase and amplitude).
The M: Quadrature Amplitude Modulation (M) method is well known.

As described above, conventionally, one carrier wave is modulated at a high speed so that it fits within a transmission band. However, recently, an orthogonal frequency division multiplexing system (OFDM) has been used.
A modulation method called cy Division Multiplex) has been proposed. In this OFDM system, a large number of orthogonal carriers are provided in the transmission band, and each orthogonal carrier is PSK.
And QAM are used for digital modulation. Since this method divides the transmission band by a large number of carriers,
Although the band per wave becomes narrower and the modulation speed becomes slower, the total transmission speed is the same as that of the conventional modulation method because of the large number of carriers.

In this OFDM system, since a large number of carriers are transmitted in parallel, the symbol transmission rate becomes slow,
In a transmission path where so-called multipath interference exists, the time length of multipath relative to the time length of a symbol can be shortened. Therefore, this method can be said to be a strong method against multipath interference, and due to such characteristics, it has been particularly noted for the transmission of digital signals by terrestrial waves which are strongly affected by multipath interference.

Furthermore, recent advances in semiconductor technology have made it possible to implement discrete Fourier transform and inverse discrete Fourier transform by hardware, and by using these, modulation and demodulation of the OFDM system can be easily performed. I can do it now. Further, according to the OFDM method, it can be considered that each carrier is subjected to non-selective fading even in a frequency selective fading environment, so that the OFDM method is also suitable for mobile communication. be able to.

Attention is paid to various advantages of the OFDM system, and in Europe, DAB (Digital Audio Broadcasti) is used as a broadcast using the OFDM system as a modulation system.
ng) method has been proposed, and in the UK from the fall of 1995 DA
The main broadcast of B has started.

FIG. 10 is a diagram showing the format of the DAB method. As shown in this figure, in the DAB method, one frame (96 ms) is used as a null signal for frame synchronization and one TFP as a reference symbol.
It is composed of R (Time Frequency Phase Reference) and 75 OFDM symbols. Information is transmitted by periodically and repeatedly sending such frames.

Each OFDM symbol is composed of carrier waves of 1,536 waves having different frequencies, and each carrier wave is π / 4 offset differential quadrature phase modulation (QPS).
K: Modulated by Quadrature Phase Shift Keying method. Further, the TFPR symbol is a symbol inserted for synchronizing various signals on the receiving device side.

In the DAB system, since modulation is performed by phase modulation, various kinds of synchronization are necessary for the receiving device to correctly demodulate the signal transmitted from the transmitting device. That is, the frequency and phase of the reproduction carrier used for converting the OFDM signal in the intermediate frequency band into the OFDM signal in the base band (OFDM signal in the base band) are
It is necessary to synchronize them with those on the transmitter side, and it is also necessary to synchronize the clock signal for demodulating the baseband OFDM signal with the clock signal on the transmitter side.
Furthermore, it is necessary to synchronize the window sync signal used to extract the symbols contained in each frame so that exactly one symbol is extracted.

The above-mentioned TFPR symbol is used to establish various kinds of synchronization as described above. That is, the reproduced carrier wave and the window synchronization signal are reproduced from the cross-correlation value between the received signal and the TFPR symbol, and the clock signal is reproduced from the channel impulse response of the TFPR symbol.

[0011]

By the way, when performing various kinds of synchronization processing using TFPR symbols, first, the TFPR symbols included in each frame must be accurately extracted from the received signal. , Extracted TF
It was necessary to perform a complicated operation in order to generate various synchronization signals from the PR symbol.

Therefore, according to the conventional method of performing various kinds of synchronization using TFPR symbols, the synchronization of various signals such as carrier waves and clocks must be established before TFP is used.
There is a problem that the R symbol cannot be extracted.

From the extracted TFPR symbol,
Hardware and software for generating various synchronization signals have been required. As a result, there are problems that the cost of the receiving device becomes high and the size of the receiving device becomes large.

The present invention has been made in view of such a situation, and it is possible to easily generate a basic OFDM window synchronization signal for obtaining various kinds of synchronization required in a receiving apparatus. To do.

[0015]

According to a first aspect of the present invention, there is provided a receiving device for detecting a no-signal state, and a reference signal for extracting predetermined information from a signal according to a detection result of the detecting means. And a reference signal generating means for generating.

A receiving method according to a fourth aspect of the present invention comprises the steps of detecting a no-signal state, and generating a reference signal for extracting predetermined information from the signal according to the detection result. And

In the receiving device according to the first aspect, the detecting means detects the no-signal state, and the reference signal generating means generates the reference signal for extracting predetermined information from the signal in accordance with the detection result of the detecting means. Is generated. For example, the null signal included in the OFDM signal can be detected by the detecting means, and the window synchronization signal can be generated according to the detection result.

In the receiving method according to the fourth aspect, the no-signal state is detected, and the reference signal for extracting the predetermined information from the signal is generated according to the detection result. For example, O
The null signal included in the FDM signal can be detected by the detecting means, and the window synchronization signal can be generated according to the detection result.

[0019]

1 is a block diagram showing the configuration of an embodiment of a receiving apparatus of the present invention. The outline of the operation of this embodiment will be described below with reference to this figure, and then the detailed configuration and operation of each unit will be described.

In FIG. 1, the antenna 1 is an RF (Radi
o Frequency) band signal is received and supplied to the tuner 2. The tuner 2 extracts a signal having a desired frequency from the signal in the RF band, converts it into an OFDM signal in the intermediate frequency band, and then outputs it to the IF circuit 3. The IF circuit 3 amplifies the intermediate frequency OFDM signal supplied from the tuner 2 by a predetermined amount, shapes the spectrum, and orthogonally uses the reproduced carrier wave supplied from the carrier wave reproduction circuit 10 (reference signal generation means). A demodulated baseband signal, that is, an OFD composed of I data and Q data
Extract the M signal.

I of the base band generated by the IF circuit 3
Data and Q data are sent to the FFT via signal lines 4 and 5.
(Fast Fourie Transform) It is input to the operation circuit 6 and the FFT window synchronization signal generation circuit 7. FF
The T window synchronization signal generation circuit 7 detects the null signal included in the I data and the Q data by the null signal detection circuit 7a (detection means), and the time base circuit 7b (reference signal) based on the null signal. The generation means) generates a timing signal for window generation and supplies it to the window generation circuit 7c (reference signal generation means). The window generation circuit 7c generates a window synchronization signal according to the timing signal supplied from the time base circuit 7b and outputs it to the FFT operation circuit 6.

The FFT operation circuit 6 extracts each symbol from the I data and Q data supplied from the IF circuit 3 in synchronization with the window synchronization signal. Then, an FFT operation is performed on the extracted symbols (demodulation based on the OFDM method), and the obtained reproduced I data and reproduced Q data are output via the signal lines 8 and 9.

The output data of the FFT calculation circuit 6 is also supplied to the carrier wave recovery circuit 10 and the clock recovery circuit 11 (reference signal generating means). The carrier wave reproduction circuit 10 reproduces a carrier wave according to the output data of the FFT calculation circuit 6 and supplies it to the IF circuit 3. The clock reproduction circuit 11 also generates a clock signal based on the output data of the FFT operation circuit 6 and supplies it to the FFT operation circuit 6 and the window generation circuit 7c, respectively.

Next, an outline of the operation of the embodiment shown in FIG. 1 will be described.

An RF signal transmitted from a transmitter (not shown) is received by the antenna 1 and supplied to the tuner 2. The tuner 2 extracts a desired signal included in the RF signal, converts the signal into an intermediate frequency signal, and supplies the intermediate frequency signal to the IF circuit 3. The IF circuit 3 amplifies the intermediate frequency signal supplied from the tuner 2 by a predetermined amount, and then uses the reproduced carrier wave supplied from the carrier wave reproduction circuit 10 to generate a signal (I signal component) in the base frequency band (base band). Q signal component). Then, after converting these I signal component and Q signal component into digital data, they are output as I data and Q data via the signal lines 4 and 5, respectively.

The I data and Q data output from the IF circuit 3 are supplied to the FFT operation circuit 6 and the FFT window synchronization signal generation circuit 7. The FFT calculation circuit 6 extracts I data and Q data for one symbol based on the synchronization signal supplied from the FFT window synchronization signal generation circuit 7, and performs a fast Fourier transform process (FFT process) on these data. Give.
Then, the reproduction I which is the real part of the resulting data
The data and the reproduced Q data which is the imaginary part are signal lines 8 and 9
Is output via.

The FFT window synchronization signal generation circuit 7 to which the I data and Q data output from the IF circuit 3 are input, detects the null signal contained in the I data and Q data by the null signal detection circuit 7a. Then, based on the detected null signal, the time base circuit 7b generates a timing signal for window generation, and in synchronization with this timing signal,
The window generation circuit 7c generates a window synchronization signal having a time width of 1 symbol and supplies it to the FFT operation circuit 6.

The FFT operation circuit 6 extracts I data and Q data for one symbol based on the window synchronization signal supplied from the window generation circuit 7c of the FFT window synchronization signal generation circuit 7,
Fast Fourier transform processing is applied to the extracted data.

The carrier wave reproducing circuit 10 includes an FFT arithmetic circuit 6
The carrier wave is reproduced based on the reproduced I data and the reproduced Q data output from and is supplied to the IF circuit 3.

The clock reproduction circuit 11 reproduces a clock signal based on the reproduced I data and the reproduced Q data output from the FFT calculation circuit 6, and the FFT calculation circuit 6 and the window generation circuit 7
c.

Next, a more detailed configuration example of each circuit of the embodiment shown in FIG. 1 will be described.

FIG. 2 shows the null signal detection circuit 7a shown in FIG.
FIG. 3 is a block diagram illustrating a configuration example of FIG. In this figure, I data and Q data input via signal lines 4 and 5 are
The adders 3 are squared by the squaring circuits 30 and 31, respectively.
2. The adder 32 adds the output signals of the squaring circuits 30 and 31 and supplies it to the adder 33. Adder 33
Adds the output signal of the adder 32 and the output signal of the delay circuit 34 and supplies the result to the subtractor 36. The delay circuit 34 delays the output signal of the subtractor 36 by one clock and outputs it to the adder 33. The delay circuit 35 delays the output signal of the adder 32 by a time corresponding to a time window described later and outputs the delayed signal to the subtractor 36. The subtractor 36 subtracts the output signal of the delay circuit 35 from the output signal of the adder 33, and outputs the calculation result as the output signal of the null signal detection circuit 7a.

Next, the operation of the embodiment shown in FIG. 2 will be described with reference to FIGS.

FIG. 3 is a timing chart for explaining the time window. FIG. 3A shows the clock signal output from the clock recovery circuit 11 shown in FIG. 1, and FIG. 3B shows the output signal of the adder 32.

Now, assume that I data and Q data are input to the null signal detection circuit 7a in synchronization with the clock C ₀ (FIG. 3A). At this time, the I data and Q data are squared by the squaring circuits 30 and 31, respectively, and added by the adder 32. As a result, the data D ₀ (Fig. 3
(B)) is generated. This data D ₀ is added to the adder 33.
Is input to the delay circuit 35. The adder 33 uses the data D
₀ and the output of the delay circuit 34 (the output of the subtractor 36 one clock before) are added and output.

In the present case, since the first data (D ₀ ) is input, the delay circuit 34 is in a non-output state. Therefore, the output of the adder 33 becomes the value of "D ₀ ". Further, the delay circuit 35 converts the input data into N
Since the output is delayed by the clock, the output is not output in this case. Therefore, from the subtractor 36, "D ₀ "
Is output.

Next, when the second I data and Q data are input in synchronism with the clock C ₁ , the same processing as described above is performed, and "D ₁ " is output from the adder 32. To be done. This “D ₁ ” is input to the adder 33, is added to the output value of the delay circuit 34 (the output data (= D ₀ ) of the subtractor 36 one clock before), and is output (that is, “D ₀ ”). + D
₁ "is output.) Since the delay circuit 35 outputs the output of the adder 32 N clocks before, it is still in a non-output state (= 0). The output "D ₀ + D ₁ " of the device 33 is output as it is.

When the above processing is repeatedly executed and the Nth I data and Q data are input to the null signal detection circuit 7a in synchronization with the clock C _N-1 (FIG. 3A), the addition is performed. The device 32 outputs the data "D _N-1 ". Delay circuit 3
Since the output value of 5 is still "0", the subtractor 36 outputs "D ₀ + D ₁ + ... + D _N-1 " as a result of the calculation.

Subsequently, when the (N + 1) th I data and Q data are input to the null signal detection circuit 7a in synchronization with the clock C _N (FIG. 3A), the data "" is output from the adder 32. D _N ″ (FIG. 3B) is output and input to the adder 33. Since the delay circuit 34 outputs "D ₀ + D ₁ + ... + D _N-1 " which is the output of the subtractor 36 one clock before, the output of the adder 33 is "D ₀ + D _1". + ・
.. + D _N-1 + D _N ″. At this time, the output of the adder 32 N clocks before (= D ₀ ) from the delay circuit 35.
Is output, the subtractor 36 subtracts the output value of the delay circuit 35 from the output value of the adder 33 to obtain "D ₁ + D ₂ + ...
+ D _N-1 + D _N ″ is output. That is, the null signal detection circuit 7a outputs a value obtained by adding all the data surrounded by the time window shown in FIG. It will be.

Further, at the next clock C _{N + 1} (FIG. 3A), the data D _{N + 1} is output from the adder 32, and this value and the output “D ₁ + D ₂ +. .. + D
_{“N 1} + D _N ” and “D ₁ + D ₂ + ... + D _N-1 +
D _N + D _{N + 1} ″ is output from the adder 33. Subtractor 3
6 is the output value of the delay circuit 35 from the output value of the adder 33 (=
"D ₂ + ... + D _N-1 + D _N + D _{N + 1} " obtained by subtracting D ₁ ) is output. That is, at this time, the null signal detection circuit 7a
A value obtained by adding all the data surrounded by the time window shown in FIG. 3D is output.

Therefore, according to such a configuration, a time window having a length of N clocks is set, and all (designated) I data and Q data surrounded by this time window are squared. Then, the added value can be obtained.

FIG. 4 is a timing chart showing the relationship between the phase of the time window and the output signal of the null signal detection circuit 7a. Now, assume that the time width of the time window is set to be equal to the time width of the null signal shown in FIG. At this time, the null signal detection circuit 7a squares the I data and Q data in the range surrounded by the time window in the baseband OFDM signal (the signal composed of I data and Q data (FIG. 4A)). Then, the cumulatively added value (FIG. 4C) is output.

In the signal modulated by the DAB method, the carrier of 1,536 waves in each symbol is modulated by π / 4 offset differential QPSK, so that the signal energy of each symbol is equal to each other. That is, the value (value corresponding to the signal energy) obtained by squaring and instantaneously adding the I data and the Q data at each instant is constant in each symbol period. Therefore, the time window is P0 (Fig. 4 (b))
Output values R0 of the null signal detection circuit 7a in the case of the position P1 and the position of P3 (FIG. 4B).
And R3 are equal.

The applicant of the present invention has performed simulations using a computer and confirmed that the output of the null signal detection circuit 7a is substantially constant between symbols.

Now, assuming that the time window is at the position of P0 (FIG. 4 (b)), the null signal detection circuit 7a causes the cumulative addition of the square of I data and Q data in the range surrounded by this time window. The value R0 (FIG. 4 (c)) is output. After that, it is assumed that a predetermined time has elapsed and the position of the time window has reached P1 (FIG. 4B). At this time, part of the time window overlaps part of the null signal. The null signal has no signal, and the signal energy of this portion is “0” when the influence of noise or the like is ignored. Therefore, the position of the time window is P1 (see FIG.
In the case of (b)), the output value R1 of the null signal detection circuit 7a (FIG. 4 (c)) becomes smaller (R1 than the output value R0 of the position P0 (FIG. 4 (b)). <R0).

Then, when the time window reaches the position of P2 (the position where the time window completely overlaps the null signal), the output of the null signal detection circuit 7a becomes the minimum value R2 (= 0) (FIG. 4 (c)). Become. After that, the output value of the null signal detection circuit 7a gradually increases, and after passing the position of P3 (FIG. 4B), a constant value R3.
(Fig. 4 (c)).

Therefore, in the output signal of the null signal detection circuit 7a, the timing (T
Immediately before the FPR signal is input), it has a minimum value.

Although the influence of noise is ignored in the above description, even when noise is superimposed on the received signal (RF signal), the output signal of the null signal detection circuit 7a (see FIG. 4).
(C) does not become "0" as in the case where noise is not included, but it has a predetermined minimum value. Therefore,
Even in such a case, the null signal (FIG. 4A) can be detected.

FIG. 5 shows the time base circuit 7b shown in FIG.
FIG. 3 is a block diagram illustrating a configuration example of FIG. In this figure, the output signal of the null signal detection circuit 7a is input to the respective terminals A of the comparator 50, the selector 51, and the comparator 52. The comparator 52 compares the output of the null signal detection circuit 7a input to the terminal A with the reference voltage V _RF of the reference power supply 56 input to the terminal B, and as a result, the reference voltage V _RF When is large, the output signal is set to the "H" state.

The differentiator 53 differentiates the output signal of the comparator 52 and outputs it to the register 54. In the selector 51, the output signal of the register 54 is input to the terminal B, and the output of the null signal detection circuit 7a is input to the terminal A. If the output signal of the comparator 50 is in the "H" state, the selector 51 selects the signal input to the terminal A (the output signal of the null signal detection circuit 7a), and conversely in the "L" state. If so, the signal input to the terminal B (output signal of the register 54) is selected and output to the register 54. The register 54 stores (holds) the output signal of the selector 51 and supplies it to the respective terminals B of the selector 51 and the comparator 50.

The comparator 50 compares the output signal of the register 54 with the output signal of the null signal detection circuit 7a. If the output signal of the register 54 is larger, the output signal is "H".
State. The differentiator 55 differentiates the output signal of the comparator 50 and outputs it as the output signal of the time base circuit 7b.

Next, the operation of the time base circuit 7b shown in FIG. 5 will be described with reference to the timing chart shown in FIG.

Now, the output value of the null signal detection circuit 7a is V
_If it becomes smaller than _RF, the output signal of the comparator 52 is in the "H" state (FIG. 6 (c)), and the differentiator 53
Outputs an impulse-shaped signal at the rising portion of the output pulse of the comparator 52 (FIG. 6 (d)). As a result, the reset signal is supplied to the register 54, and the register 54 is reset to the value of (10 × V _RF ), for example. Then, since the reset value (= 10 × V _RF ) is supplied to the terminal B of the comparator 50, the value input to the terminal A (the output of the null signal detection circuit 7a) is
The signal input to the terminal B becomes larger, and the output signal becomes "H" (FIG. 6 (e)). As a result, the selector 51 is connected to the terminal A side, and the output of the null signal detection circuit 7a is supplied to and stored in the register 54.

After that, since the output value of the null signal detection circuit 7a gradually decreases, the output value of the null signal detection circuit 7a becomes smaller than the value stored in the register 54, and the output signal of the comparator 50 becomes " It remains in the H "state (Fig. 6).
(E)). Therefore, the selector 51 is continuously connected to the terminal A side, and the value stored in the register 54 is sequentially updated by the output of the null signal detection circuit 7a.

After the time W1 when the output of the null signal detection circuit 7a reaches the minimum value, the null signal detection circuit 7a
, The output of the null signal detection circuit 7a input to the terminal A of the comparator 50 becomes larger than the output of the register 54 input to the terminal B.
As a result, the output of the comparator 50 becomes "L" (FIG. 6 (e)). Then, the connection of the selector 51 is switched to the terminal B side, and the value currently stored in the register 54 is input to the register 54 again.
Therefore, the minimum value at the time W1 is held in the register 54 as it is.

The differentiator 55 differentiates the output signal of the comparator 50, detects the falling portion of the output signal, and outputs an impulse-shaped signal at this portion (FIG. 6 (f)).
The output signal of the comparator 50 falls at the portion where the output of the null signal detection circuit 7a becomes minimum as described above.
Therefore, the differentiator 55 outputs an impulse-shaped signal at the timing when the output signal of the null signal detection circuit 7a becomes minimum.

When noise or the like is superimposed on the received signal (RF signal), the output signal of the null signal detection circuit 7a does not have an ideal minimum value as shown in FIG. 6 (b). In some cases (cases without sharp peaks) may occur. In such a case, there is a possibility that the timing when the null signal becomes the minimum value and the timing when the impulsive signal is output from the differentiator 55 do not match. However, according to the simulation performed by the applicant using a computer, the timing at which the impulse-shaped signal is output from the differentiator 55 is calculated from the null signal detection circuit 7a even when noise or the like is superimposed on the received signal. It is sufficiently coincident with the timing of outputting the minimum value, and it has been confirmed that the impulse signal (output signal of the time base circuit 7b) obtained by such a configuration can be used as a stable timing signal. .

FIG. 7 is a block diagram showing a configuration example of the window generation circuit 7c shown in FIG. In this figure, the NOR element 71 includes a timing signal output from the time base circuit 7b (impulse signal output from the differentiator 55 in FIG. 5 (FIG. 6 (f))) and an output signal from the counter 72. A negative logical sum is calculated between and, and the result is supplied to the clear terminal of the counter 72. The counter 72 uses the clock recovery circuit 11
A countdown operation is performed in synchronization with a clock signal supplied from the device, and when the countdown is completed, an impulse signal indicating the end is output.

Next, the operation of this structural example will be described with reference to the timing chart shown in FIG.

The output signal of the time base circuit 7b (see FIG. 8).
(B)) is input to one terminal of the NOR element 71. The counter 72 displays the time width τ of each symbol of the baseband OFDM signal in synchronization with the clear timing.
Is divided by the period T _C of the clock signal.
That is, when the output of the NOR element 72 is in the "L" state (when the output of the time base circuit 7b is in the "H" state, or when the output of the counter 72 is in the "H" state). Case), the above values are set. Then, the counter 72 counts down the set value in synchronization with the clock signal supplied from the clock reproduction circuit 11.

Now, assuming that the output of the time base circuit 7b is in the "H" state at the end of the null signal (immediately before the TFPR symbol) (FIG. 8B), the output of the NOR element 71. Becomes "L" (Fig. 8
(D)), the counter 72 starts counting down.
As described above, the value set in the counter 72 is the value obtained by dividing the time width τ of each symbol of the baseband OFDM signal (FIG. 8A) by the cycle T _C of the clock signal (= τ / T _C )
Therefore, when the counter 72 finishes counting down this value (when the time corresponding to the time width τ of each symbol elapses), the counter 72 outputs an impulse-like signal (FIG. 8 (c)).

When the counter 72 outputs an impulse-shaped signal, the output signal of the NOR element 71 becomes "L" (FIG. 8 (d)), and the counter 72 displays the value "τ / T".
_C ”is set again and the countdown starts.
Then, when the countdown is completed, an impulse-shaped signal is output (FIG. 8C), so that the countdown is started again as in the case described above.

Such an operation is performed by the time base circuit 7b.
Is repeated until the impulse signal is output again (until the null signal of the next frame is detected), and the impulse signal output from the NOR element 71 is
The output signal (window synchronization signal) of the window generation circuit 7c is FF
It is supplied to the T arithmetic circuit 6.

According to such an embodiment, as shown in FIG. 8 (d), it becomes "H" in synchronization with the start portion of each symbol of the baseband OFDM signal and "L" in synchronization with the end portion. It is possible to generate a signal in the state of, that is, a window synchronization signal. Further, this window synchronization signal is the time base circuit 7b.
Since it is generated in synchronism with the timing signal from (a signal generated based on the end portion of the null signal), an accurate window synchronization signal can be generated as long as the null signal can be received.

In the configuration example shown in FIG. 7, the clock signal output from the clock recovery circuit 11 is used for the countdown, but the clock recovery circuit 11 uses a voltage controlled crystal oscillator. With such a configuration, the receiving device can generate an accurate window synchronization signal even when synchronization has not been established yet. Further, in that case, since the window synchronization signal is generated for each frame with reference to the null signal, the accumulated error in the frame becomes negligible and the clock error is not accumulated.

In the above embodiment, the null signal detection circuit 7a is used.
In, the sum of the squares of the I data and the Q data is obtained, and the null signal is detected based on this result. However, as shown in FIG. 9, the null signal may be detected from the sum of absolute values of I data and Q data.

That is, in the configuration shown in FIG. 9, 2 shown in FIG.
The squaring circuits 30 and 31 are replaced with absolute value circuits 80 and 81, respectively. Other configurations are similar to those shown in FIG.

The absolute value circuits 80 and 81 calculate the absolute value of each of the input I data and Q data. The adder 32 adds the absolute values of the I data and the Q data and outputs the result to the adder 33. Then, the delay circuits 34 and 35 and the subtractor 36 perform the same processing as that described above, and the null signal is detected.

In the above embodiment, the square value or absolute value of each of I data and Q data is added by the adder 32 and used. However, for example, either one of I data and Q data is used. You may make it use the square value and absolute value only. With such a configuration, the circuit configuration can be further simplified and the size of the receiving device can be further reduced.

[0070]

According to the receiving device of the first aspect and the receiving method of the fourth aspect, the non-signal state is detected and the reference signal for extracting the information is generated, which is simple. Various circuits can generate various synchronization signals. Further, even if the synchronization of the receiving device is not established, various synchronization signals can be generated.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a receiving apparatus of the present invention.

FIG. 2 is a block diagram showing a configuration example of a null signal detection circuit 7a shown in FIG.

FIG. 3 is a timing chart for explaining the operation principle of the null signal detection circuit 7a shown in FIG.

FIG. 4 is a timing chart for explaining the operation principle of the null signal detection circuit 7a shown in FIG.

5 is a block diagram showing a configuration example of a time base circuit 7b shown in FIG.

FIG. 6 is a timing chart for explaining the operation principle of the time base circuit 7b shown in FIG.

7 is a block diagram showing a configuration example of a window generation circuit 7c shown in FIG.

8 is a timing chart for explaining the operation principle of the window generation circuit 7c shown in FIG.

9 is a block diagram showing another configuration example of the null signal detection circuit 7a shown in FIG. 1. FIG.

FIG. 10 is a diagram showing a format of a DAB system signal.

[Explanation of symbols]

7 FFT window synchronization signal generation circuit, 7a null signal detection circuit (detection means), 7b time base circuit (reference signal generation means), 7c window generation circuit (reference signal generation means), 10 carrier recovery circuit (reference signal generation means) ，
11 Clock reproduction circuit (reference signal generation means)

Claims (4)

[Claims] 1. A receiving device for receiving a signal in which a non-signal state is periodically inserted, a detection means for detecting the non-signal state, and predetermined information from the signal according to a detection result of the detection means. And a reference signal generating means for generating a reference signal for extracting the signal. 2. The signal in which a no-signal state is periodically inserted is an OFDM signal, the detecting means detects a null signal in the no-signal state of the OFDM signal, and the reference signal generating means is The window synchronization signal is generated according to the detection result of the detecting means.
3. The receiving device according to claim 1. 3. The receiving method according to claim 1, wherein the detecting means calculates the energy of the signal within a predetermined period, and detects the timing when the calculated energy becomes minimum. 4. A receiving method for receiving a signal in which a signalless state is periodically inserted, the step of detecting the signalless state, and extracting predetermined information from the signal according to a detection result. Generating a reference signal.