JPH09246972A - Delta sigma modulation type analog/digital conversion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the mounting area of a circuit and to finely adjust an amplitude limit value in performing amplitude limiting for preventing oscillation. SOLUTION: A voltage amplifier 12 is interposed in at least one part among integrators M1-M7 cascade connected for plural stages and excessive input signals are clipped by the amplitude limit value stipulated by a power supply voltage in the integrators M3-M7 of a poststage. Thus, relating to the respective integrators M3-M7, the mounting area is reduced compared to the case of providing a limiter circuit composed of a diode or the like and the limit value for the input amplitude of the integrator is finely adjusted by adjusting the gain of the voltage amplifier 12 and the input of the integrator following it.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is preferably carried out with respect to an acoustic signal, and in recording, reproducing and transmitting the acoustic signal as a 1-bit digital signal, the acoustic signal is converted into a 1-bit digital signal by analog / digital. The present invention relates to a delta-sigma modulation type analog / digital conversion circuit for conversion.

[0002]

2. Description of the Related Art In recent years, analog / digital conversion circuits using a delta-sigma modulation system have been used, which can improve the conversion accuracy without raising the sampling frequency too much. This delta-sigma modulation type analog-to-digital conversion circuit generally includes a plurality of cascaded integrators, an adder that adds outputs from the integrators, and a 1-bit quantum output from the adder. And a digital / analog converter for analog-converting the output from the quantizer and feeding back to the input.

In such a delta-sigma modulation type analog / digital conversion circuit, generally, by increasing the number of stages of the integrator, that is, the feedback order, the noise shaping effect of moving the quantization noise to the high frequency side. Is obtained, and it is known that the S / N can be improved. Further, in order to improve the S / N, it is required to set a large allowable input level with a high input gain.

However, there is a problem that the circuit is more likely to oscillate as the integrator is configured in a higher order and the input gain is increased. The oscillation occurs when the signal level exceeds a predetermined oscillation limit value. Therefore, it is important to control the signal level, and in a typical conventional technique, the signal level is controlled as shown in FIG.

FIG. 5 is a block diagram showing an electrical configuration of a typical conventional delta-sigma modulation type analog / digital conversion circuit 1. The analog / digital conversion circuit 1 includes a seventh-order integrator m1, m2, ...
m7, the feedback resistor r0, the adder 3, the quantizer 4,
The digital / analog converter 5 is provided.

The first-order integrator m1 has an input resistance r1 and
It comprises a differential amplifier a1 and a capacitor c1 as a time constant element. The analog audio signal from the input terminal 6 is input to the inverting input terminal of the differential amplifier a1 via the input resistor r1. The non-inverting input terminal of the differential amplifier a1 is grounded. The output from the differential amplifier a1 is output to the adder 3 and also to the inverting input terminal via the capacitor c1 to be negatively fed back.

The remaining integrators m2 to m7 are also the above-mentioned integrators m to m7.
1, and the reference numerals of the corresponding parts are the same alphabetical characters with the addition of the subscript corresponding to the order of each of the integrators m2 to m7. Thus, for example, the second
In the next integrator m2, the output from the integrator m1 is input via the input resistor r2, and the output is input to the adder 3 and also to the next-stage integrator m3.

The outputs from the integrators m1 to m7 are input to the adder 3 and added to each other as described above, and then input to the quantizer 4. The quantizer 4 derives an output of “1” from the output terminal 7 when the output from the adder 3 is 0 or more, and derives an output of “0” when the output is less than 0. Output added value from ~ m7 is 1
Bit quantization is performed. The output of the quantization result by the quantizer 4 is converted into an analog value by the digital / analog converter 5, and then is negatively fed back to the input side via the feedback resistor r0.

In this analog / digital conversion circuit 1,
In order to realize the control of the signal level, limiter circuits d3, d4, ..., D7 are provided for the third and subsequent integrators m3 to m7 whose amplitude increases.
The limiter circuits d3 to d7 are constructed by connecting diodes of mutually opposite polarities in parallel, and are provided in parallel with the feedback capacitors c3 to c7.

Therefore, with respect to the input voltage to each of the differential amplifiers a3 to a7 shown in FIG.
When the diode has a conduction voltage equal to or higher than the conduction voltage as indicated by reference symbol Vs1 in (b), the output voltage is fed back to the feedback capacitors c3 to c7 by the limiter circuits d3 to d7.
Is bypassed and negative feedback is given. The number of stages of the diode is determined according to the amplitude value to be limited. In this way, the amplitude value of the output from each of the differential amplifiers a3 to a7 does not exceed the amplitude limit value for stably operating the integrators m1 to m7, as shown by reference numeral Vs2 in FIG. 6B. To prevent the oscillation.

[0011]

The above-described conventional analog / digital conversion circuit 1 has a relatively simple and economical circuit structure, but the limiter circuits d3 to d are provided.
There is a problem that the number of components of 7 is large and the mounting area of the circuit is large. That is, in the example of FIG. 5 described above, the power supply voltage of each differential amplifier a1 to a7 is, for example, 5
V, and correspondingly, the diodes of the limiter circuits d3 to d7 have two stages, that is, the limiter circuits d3 to d7.
It is composed of four diodes. Therefore, there is a problem that a mounting area for a large number of diodes is required.

Further, since the limit value of the amplitude is determined to be a value that is an integral multiple of the ON voltage of the diode, there is a problem that it is not possible to make a minute adjustment.

An object of the present invention is to reduce the mounting area of a circuit in order to prevent oscillation in a high-order delta-sigma modulation type analog-to-digital conversion circuit and to make a fine adjustment of an amplitude limit value. An object of the present invention is to provide a delta-sigma modulation type analog / digital conversion circuit which can be performed.

[0014]

According to another aspect of the present invention, there is provided a delta-sigma modulation type analog / digital conversion circuit, which is a high-order delta-sigma modulation type analog / digital conversion circuit in which a plurality of stages of integrators are cascaded. In the conversion circuit, the integrator is realized by using a differential amplifier that can obtain a predetermined proper gain and linearity with respect to a change in power supply voltage, and the power supply voltage is provided between at least one integrator. The voltage amplifier using the amplitude limiting action of the differential amplifier corresponding to the above is interposed.

According to the above arrangement, the fact that the operating region of the differential amplifier forming the integrator is limited by the power supply voltage makes use of the differential amplifier at the time of proper input.
A gain is suppressed by increasing the linearity of the amplification operation with an appropriate gain, and when the input is strong, the gain is suppressed as it approaches the limit value of the operation region that is set corresponding to the power supply voltage. Clip and cut off.

Therefore, for example, by interposing a voltage amplifier such as a differential amplifier between the second-order integrator and the third-order integrator, the input gain of the third-order integrator can be reduced. The amplitude limiting operation for preventing oscillation can be performed, the mounting area of the circuit can be reduced, and the S / N can be improved by setting the input gain high. Further, by adjusting the gain of the voltage amplifier and the input gain of the third-order integrator, it is possible to finely adjust the limit value with respect to the input amplitude of the third-order integrator.

Further, in the delta-sigma modulation type analog / digital conversion circuit according to the invention of claim 2, the voltage amplifier is interposed between the second-order integrator and the third-order integrator, and the power supply voltage is increased. The gain setting is performed so that the amplitude limit value of the differential amplifier corresponding to (3) matches the amplitude limit value at which the third and subsequent integrators operate stably.

According to the above configuration, in the strong input signal, the portion exceeding the amplitude limit value determined corresponding to the power supply voltage is clipped, and this amplitude limit value is oscillated by the gain of the subsequent integrator. Since it is less than the limit value, oscillation does not occur. In this way, the amplitude limiting operation for preventing oscillation can be realized.

Furthermore, a delta-sigma modulation type analog / digital conversion circuit according to a third aspect of the present invention is a high-order delta-sigma modulation type analog / digital conversion circuit configured by cascade-connecting a plurality of stages of integrators. , Each integrator is divided into multiple groups, power can be supplied individually to each group, and a power supply circuit that can limit the amplitude of each integrator according to the power supply voltage must be provided. Is characterized by.

According to the above configuration, for each integrator including a differential amplifier and a feedback capacitor,
For example, set the power supply voltage so that a predetermined gain can be obtained for the integrator in the front stage side, and set the power supply voltage so that the excessive amplitude can be clipped for the integrator in the rear stage side. Set to suppress the amplitude value of the output of the integrator and prevent oscillation.

Thus, for example, by providing the power supply circuits capable of supplying different power supply voltages to the respective groups on the front stage side and the rear stage side, oscillation can be prevented without using the voltage amplifier. Amplitude limiting operation can be performed.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION Regarding one embodiment of the present invention,
The following is a description based on FIGS. 1 to 3.

FIG. 1 is a block diagram showing an electrical configuration of a delta-sigma modulation type analog / digital conversion circuit 11 according to an embodiment of the present invention. The analog / digital conversion circuit 11 includes seven-order integrators M1 and M1 connected in cascade.
2, ..., M7, the feedback resistor R0, the voltage amplifier 12,
It is configured to include an adder 13, a quantizer 14, and a digital / analog converter 15.

The first-order integrator M1 has an input resistor R1 and
It comprises a differential amplifier A1 and a capacitor C1 as a time constant element. The analog audio signal from the input terminal 16 is input to the inverting input terminal of the differential amplifier A1 via the input resistor R1. The non-inverting input terminal of the differential amplifier A1 is grounded. The output from the differential amplifier A1 is output to the adder 13 and also input to the inverting input terminal via the capacitor C1 to be negatively fed back.

The remaining integrators M2 to M7 are also the integrators M
The reference numeral of the corresponding portion is the same as the alphabetic character with the suffix corresponding to the order of each of the integrators M2 to M7. Thus, for example, the second
In the next integrator M2, the output from the integrator M1 is input via the input resistor R2, and the output is input to the adder 13 and the next stage integrator M3 via the voltage amplifier 12. .

The outputs from the integrators M1 to M7 are input to the adder 13 and added to each other as described above, and then input to the quantizer 14. In the quantizer 14, the adder 1
When the output from 3 is greater than or equal to 0, the output of "1" is derived from the output terminal 17, and when the output is less than 0, the output of "0" is derived. Thus, the output added value from each of the integrators M1 to M7 is One bit quantization is performed. Also, this quantizer 1
4 is converted to an analog value by the digital / analog converter 15 and then output to the feedback resistor R.
It is negatively fed back to the input side via 0.

It should be noted that in the analog / digital conversion circuit 11, the voltage amplifier 12 is interposed between the second-order integrator M2 and the third-order integrator M3. Therefore, the output from the differential amplifier A2 is amplified by the voltage amplifier 12 with a predetermined gain, and
It is given to the inverting input terminal of the differential amplifier A3 via the input resistor R3. This voltage amplifier 12 includes an integrator M3
Is an amplifier for setting the gain of the input signal to
For example, it can be realized by a general differential amplifier as shown in FIG.

FIG. 2 is an electric circuit diagram showing a specific structure of the voltage amplifier 12. The voltage amplifier 12 includes a differential amplifier 20, an input resistor Ra, feedback resistors Rb and Rc, and a resistor Rd that grounds a connection point between the feedback resistors Rb and Rc. Therefore, when the input voltage of the voltage amplifier 12 is Vin and the output voltage is Vout, the input / output characteristic of the voltage amplifier 12 is Vout =
-[{(Rb + Rc) / Ra} + RbRc / RaRd]
It becomes Vin. Therefore, the smaller the resistance Rd,
The gain becomes large, and it is possible to obtain a desired gain that allows the integrator M3 to limit the amplitude.

On the other hand, each of the differential amplifiers A1 to A7 is a differential amplifier having appropriate gain and linearity with respect to a power supply voltage in a predetermined range. Therefore, for an appropriate input voltage, an amplifying operation having linearity is performed with the gain, while the output is clipped by the amplitude limit value when the input is strong. That is,
Therefore, the gain is suppressed as the input signal approaches the amplitude limit value determined corresponding to the power supply voltage without generating an output voltage higher than the power supply voltage.

Therefore, the gain of the voltage amplifier 12 and the input gain of the integrator M3 are set so that the limit value for the input amplitude to the integrator M3 is less than the oscillation limit value determined by the gains of the integrators M3 to M7 in the subsequent stage. By setting to 1, it is possible to prevent oscillation of the analog / digital conversion circuit 11 including the high-order integrators M1 to M7.

That is, the integrator M3 includes the voltage amplifier 12
3A is an appropriate input as indicated by reference numeral Vin1 in FIG. 3A, an amplification operation with appropriate gain and linearity is performed as indicated by reference numeral Vout1 in FIG. 3B. Derive the performed output. On the other hand, in FIG.
At the time of excessive input as shown by 2, when the amplification is performed with the proper gain, the waveform exceeds the amplitude limit value Vth as shown by reference symbol Vout2 in FIG. Clipping is performed with the power supply voltage, and an amplitude limiting operation is performed as indicated by reference numeral Vout2a in FIG.

Therefore, in the analog / digital conversion circuit 11 according to the present invention, it is not necessary to provide a limiter circuit for each integrator as described with respect to the analog / digital conversion circuit 1 of the prior art, and a general differential amplifier is used. It is sufficient to use the voltage amplifier 12 which can be realized by, for example, an input gain setting to the integrator, and to insert the voltage amplifier 12 in at least one of the integrators M1 to M7, preferably between the integrators M2 and M3. The mounting area can be reduced, and the S / N can be improved by setting the input gain to the analog / digital conversion circuit 11 to be high.
Further, by adjusting the gain of the voltage amplifier 12 and the input gain of the subsequent integrator, the limit value for the input amplitude to the integrator can be finely adjusted.

Another embodiment of the present invention will be described below with reference to FIGS. 3 and 4.

FIG. 4 is a block diagram showing an electrical configuration of a delta-sigma modulation type analog / digital conversion circuit 21 according to another embodiment of the present invention. The analog / digital conversion circuit 21 is similar to the analog / digital conversion circuit 11 described above, and corresponding parts are designated by the same reference numerals and the description thereof will be omitted.

It should be noted that in the analog / digital conversion circuit 21, each integrator M1 to M7 has two groups M1 and M2 instead of the voltage amplifier 12.
The differential amplifiers A1 and A2 of each group are divided into M3 to M7, and the power supply circuits 22 and
That is, power is individually supplied from 23. The differential amplifiers A1 and A2 are connected to the power supply voltage Vc from the power supply circuit 22.
Amplification is performed with a gain corresponding to c1 and linearity is provided with respect to changes in the power supply voltage Vcc1. The power supply circuit 22 also includes the quantizer 14 and the digital / analog converter 15 in the analog / digital conversion circuit 21.
Supply power to the remaining circuits such as.

On the other hand, the differential amplifiers A3 to A7 are
The power supply voltage Vcc2 from the power supply circuit 23 limits the amplitude value of an input signal having a predetermined amplitude limit value or more. For example, when the power supply voltage Vcc1 is selected to be 5V, the power supply voltage Vcc2
Is selected as 3V, and when the power supply voltage Vcc1 is selected as 9V, the power supply voltage Vcc2 is selected as 4V.

Even in this way, the integrators M3 to M are also provided.
In FIG. 3 (c), an excessive amplitude that is Vout2 in FIG. 3 (b) is less than the amplitude limit value Vth in the integrators M3 to M7 without providing a special configuration in FIG. Since the oscillation is prevented by suppressing the waveform indicated by the symbol Vout2a, the circuit mounting area can be reduced, and the amplitude limit value can be finely adjusted by adjusting the power supply voltage Vcc2.

The delta-sigma modulation type analog / digital conversion circuits have a difference in stability depending on the algorithm, and the analog / digital conversion circuits 11 and 21 described above are
1 shows a basic circuit example for preventing oscillation. For example, in the analog / digital conversion circuit 11, only one voltage amplifier 12 is inserted between the integrator M2 and the integrator M3. Depending on the algorithm, a plurality of voltage amplifiers may be inserted between other integrators. Further, in the analog / digital conversion circuit 21, the integrators M1 to M7 have two groups M1, M2; M3 to M.
Although the power supply circuits 22 and 23 are respectively divided into seven parts, the integrator M corresponds to the above algorithm.
The groups 1 to M7 may be divided into other forms, and the number of groups may be two or more.

[0039]

As described above, the delta-sigma modulation type analog / digital conversion circuit according to the first aspect of the present invention is a high-order delta-sigma modulation type analog / digital conversion circuit configured by cascade-connecting a plurality of stages of integrators. In the digital conversion circuit, the fact that the operating region of the differential amplifier forming the integrator is limited by the power supply voltage between at least any one of the integrators makes use of the amplitude value exceeding the operating region. For the input signal, a voltage amplifier is provided for clipping and cutting off the portion exceeding the operating region.

Therefore, the amplitude limiting operation for preventing oscillation can be performed only by interposing a voltage amplifier such as a differential amplifier, the circuit mounting area can be reduced, and the input gain can be increased. It can be set to improve S / N. Further, by adjusting the gain of the voltage amplifier and the input gain of the integrator that follows it, it is possible to finely adjust the limit value with respect to the input amplitude of the integrator.

Further, the delta-sigma modulation type analog / digital conversion circuit according to the invention of claim 2 is as described above.
The voltage amplifier is interposed between the second-order integrator and the third-order integrator, and the amplitude limit value of the differential amplifier corresponding to the power supply voltage is the amplitude at which the third-order integrator and the subsequent integrator operate stably. Set the gain so that it matches the limit value.

Therefore, in the strong input signal, a portion exceeding the amplitude limit value determined corresponding to the power supply voltage is clipped, and this amplitude limit value is less than the oscillation limit value determined by the gain of the subsequent integrator. Thus, the amplitude limiting operation for preventing oscillation can be realized in this way.

Furthermore, the delta-sigma modulation type analog / digital conversion circuit according to the invention of claim 3 is a high-order delta-sigma modulation type analog circuit in which a plurality of stages of integrators are cascade-connected as described above. In the / digital conversion circuit, each integrator is divided into a plurality of groups, power is individually supplied to each group, and the amplitude of each integrator is limited according to the power supply voltage.

Therefore, for example, the power supply voltage is set so that a predetermined gain can be obtained for the integrator of the front stage side, and the excessive amplitude is clipped for the integrator of the rear stage side. By setting the power supply voltage such that the above can be achieved, the amplitude limiting operation for preventing oscillation can be performed without using the voltage amplifier.

[Brief description of drawings]

FIG. 1 is a block diagram showing an electrical configuration of a high-order delta-sigma modulation type analog / digital conversion circuit according to an embodiment of the present invention.

FIG. 2 is an electric circuit diagram showing a specific configuration of a voltage amplifier in the analog / digital conversion circuit shown in FIG.

FIG. 3 is a waveform diagram for explaining the operation of the analog / digital conversion circuit shown in FIGS. 1 and 4.

FIG. 4 is a block diagram showing an electrical configuration of a high-order delta-sigma modulation type analog / digital conversion circuit according to another embodiment of the present invention.

FIG. 5 is a block diagram showing an electrical configuration of a typical prior art delta-sigma modulation type analog / digital conversion circuit.

6 is a waveform diagram for explaining the operation of the analog / digital conversion circuit shown in FIG.

[Explanation of symbols]

 11 analog / digital conversion circuit 12 voltage amplifier 13 adder 14 quantizer 15 digital / analog converter 20 differential amplifier 21 analog / digital conversion circuit 22 power supply circuit 23 power supply circuit A1 to A7 differential amplifier C1 to C7 feedback capacitor M1 To M7 integrator R0 feedback resistance R1 to R7 input resistance Ra input resistance Rb, Rc feedback resistance Rd resistance

Claims (3)

[Claims] 1. A high-order delta-sigma modulation type analog-to-digital conversion circuit configured by cascade-connecting a plurality of stages of integrators, wherein the integrator has an appropriate gain predetermined with respect to a change in power supply voltage. And a linearity-providing differential amplifier, and a voltage amplifier using the amplitude limiting action of the differential amplifier corresponding to the power supply voltage is interposed between at least one integrator. Delta-sigma modulation type analog / digital conversion circuit. 2. The voltage amplifier includes a second-order integrator and a third-order integrator.
The gain is set so that the amplitude limit value of the differential amplifier, which is interposed between the next integrator and corresponding to the power supply voltage, matches the amplitude limit value at which the third and subsequent integrators operate stably. The delta-sigma modulation type analog / digital conversion circuit according to claim 1. 3. A high-order delta-sigma modulation type analog / digital conversion circuit configured by cascade-connecting a plurality of stages of integrators, each integrator is divided into a plurality of groups, and each group is individually Delta-sigma modulation type analog / characterized by including a power supply circuit capable of supplying power and limiting the amplitude of each integrator in accordance with the power supply voltage
Digital conversion circuit.