JPH09246402A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize high integration without lowering the driving capability of a transistor, by forming a source/drain region on one sidewall of each of a plurality of V-shaped grooves, forming a channel region on the other sidewall, and forming a plurality of gate electrodes on the plurality of V-shaped grooves in a direction of crossing the V-shaped grooves via gate insulating films. SOLUTION: An oxide film is formed on the surface of a P-type silicon substrate 21. After a photoresist film is formed on the oxide film, anisotropic wet etching is performed using the photoresist film as a mask, thus forming a plurality of V-shaped grooves 22 in parallel. On one sidewall 22a of each of the V-shaped grooves 22, an N-type source/drain region 23 is formed. Across the plurality of V-shaped grooves 22, a plurality of gate electrodes 24 are formed via gate insulating films 25 in a direction perpendicular to the V-shaped grooves 22. Thus, high integration may be realized without lowering the driving capability of a transistor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a memory cell array of an LSI memory excellent in high integration and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, with the high integration of memory cell arrays, the MOS transistors forming them have been greatly reduced in size, and the element area is small and the M drive capacity is large.
The need for OS transistors is increasing. Conventionally, this type of memory cell array has been highly integrated by using a flat cell structure. That is, as shown in FIG. 3, a plurality of source / drain regions 2 to be bit lines are formed in parallel on the surface of the silicon substrate 1, and a plurality of gates to be word lines are formed on these source / drain regions 2. Electrodes 3 are formed in a direction orthogonal to source / drain regions 2 via gate oxide film 4, and MOS transistors are arranged in a grid pattern.

Further, in order to achieve higher integration, as shown in FIG. 4, a plurality of rectangular trench grooves 12 are formed in parallel on the surface portion of the silicon substrate 11, and between these trench grooves 12, 12. At the bottom of the trench groove 12
It is proposed that the drain region 14 is formed, and a plurality of gate electrodes 16 are formed on the trench groove 12 and the source / drain regions 14 via the gate oxide film 15 in a direction orthogonal to the trench groove 12.

The manufacturing method is shown in FIGS. First, a plurality of rectangular trench grooves 12 are formed in parallel on the surface portion of the silicon substrate 11 (see FIG. 5A), and then the trench grooves 12 are formed by the chemical vapor deposition method and the anisotropic etching technique. Sidewalls 13 of SiO ₂ film are formed on both side walls 12a and 12b. Next, the sidewall 13
Using the mask as a mask, impurities are ion-implanted 101 (see FIG.
(See (b)), after forming the source / drain regions 14 in the peripheral portion and the bottom portion of the trench groove 12, the sidewall 13 is removed.

Then, thermal oxidation is performed to form a gate oxide film 15 on the trench groove 12 and the source / drain regions 14 (see FIG. 5C). After that, the gate oxide film 1
5, a gate electrode material is deposited, and the gate electrode material is patterned using photolithography and etching techniques to form a plurality of gate electrodes 16 in a direction orthogonal to the trench grooves 12 (see FIG. 5D). .

Thereafter, when writing information to the MOS transistors and separating elements between the MOS transistors, the photoresist film 1 is formed on the entire surface of the silicon substrate 11.
7 is formed, the photoresist film 17 on the channel region of one side wall 12a of the MOS transistor is opened by the photolithography technique, and then impurities are ion-implanted into one side wall 12a of the trench groove 12 (see FIG. 6). . Further, impurities are ion-implanted into the other side wall 12b by the procedure described above.

Alternatively, without using the photoresist film 17, impurities are ion-implanted 103 into one side wall 12a of the trench groove 12 from an oblique direction (see FIG. 7 (a)), and impurities are obliquely injected into the other side wall 12b. Ion implantation 104 is performed from the direction (see FIG. 7B) to change the threshold value of the MOS transistor. It should be noted that such a technique is disclosed in, for example, Japanese Patent Application Laid-Open No. 2-312278.

A source / drain region is formed on the surface of the trench groove, and a gate electrode is formed on both side walls of the trench groove via a gate oxide film, which is disclosed in, for example, Japanese Patent Laid-Open No. 5-308135. Has been done. Further, a source / drain region is formed in the central portion and the peripheral portion of the recess, and a gate electrode is formed on the side of the recess via a gate insulating film.
No. 861 and Japanese Patent Laid-Open No. 64-73673.

Further, source / drain regions are formed on the surface of the semiconductor substrate with a channel region therebetween, and the upper surface of the channel region has a rectangular wave shape or a triangular wave shape.
A structure in which a gate electrode is formed on a channel region via a gate insulating film is disclosed in, for example, Japanese Patent Application Laid-Open No. 5-75121.

[0010]

However, the present inventor has found that the above-mentioned memory cell array has the following problems. That is, JP-A-2-
In Japanese Patent No. 312278 (shown in FIGS. 4 to 7), the MOS
Since the channel region and the element isolation region of the transistor are formed on both side walls 12a and 12b of the trench groove 12, when the photoresist film 17 is used to write information into the MOS transistor and isolate the element, the trench groove 12 is formed. One side wall 12a or the other side wall 12b
It is necessary to form a pattern of the photoresist film 17 that exposes only the vicinity thereof.

For this reason, the number of steps is increased and the width of the trench groove 12 must be set to a resolvable width including the alignment margin of the pattern of the photoresist film 17, which limits the miniaturization. Occurs. This is Japanese Patent Laid-Open No.
-308135, JP-A-63-153861, JP-A-64-73673 and JP-A-5-7.
The same can be said for the 5121 publication.

When the width of the trench groove 12 is narrow and the photoresist film 17 cannot be used, the trench groove 12 is used.
Since both side walls 12a and 12b of the trench are vertically formed with respect to the silicon substrate 11, impurities are ion-implanted into one side wall 12a of the trench groove 12 from an oblique direction.
However, the impurities must be ion-implanted 104 into the other side wall 12b from an oblique direction. That is, two tilted ion implantation processes are required, which increases the number of processes.

Further, in such tilted ion implantation, it is difficult to implant impurities with good controllability over the entire area of one side wall 12a (or the other side wall 12b) in the vertical direction, and the other side wall 12b (or one side wall 12a). Since the upper corner of () obstructs the ion implantation, the impurity ion implantation varies, and the desired breakdown voltage cannot be obtained.

Of course, since the impurities are ion-implanted over the entire area of the both side walls 12a and 12b, the impurity implantation energy may be changed and the impurities may be implanted in plural times, but this increases the number of steps.

The object of the present invention is to solve the above-mentioned problems.
It is an object of the present invention to provide a semiconductor device which can be highly integrated without reducing the driving ability of a transistor in a small number of steps, and a manufacturing method thereof. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0016]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. In the semiconductor device of the present invention, a plurality of V-shaped grooves are formed on a semiconductor substrate, a source / drain region is formed on one side wall of the plurality of V-shaped grooves, and a channel region is formed on the other side wall of the plurality of V-shaped grooves. Are formed, and a plurality of gate electrodes are formed on a plurality of V-shaped grooves in a direction intersecting with the plurality of V-shaped grooves via a gate insulating film.

The semiconductor device manufacturing method of the present invention is
After forming a plurality of V-shaped grooves on the surface of the semiconductor substrate and forming a gate insulating film on the plurality of V-shaped grooves, impurities of a conductivity type different from those of the semiconductor substrate are obliquely formed on one side wall of the V-shaped grooves. Ion implantation is performed to form source / drain regions, and a plurality of gate electrodes are formed on the gate insulating film in a direction intersecting with the plurality of V-shaped grooves, and then the same kind of conductivity as the semiconductor substrate is formed on the other side wall of the plurality of V-shaped grooves. Type impurities are ion-implanted in a direction perpendicular to the semiconductor substrate, and a plurality of V-shaped grooves are formed by anisotropic wet etching. Impurities of different conductivity types are formed in parallel with the other sidewalls of the V-shaped grooves. Ions are implanted into one side wall of the V-shaped groove at an inclination angle larger than the inclination angle of the other side wall.

According to the above-mentioned means, impurities are ion-implanted into one side wall having the taper of the V-shaped groove in an oblique direction, particularly parallel to the other side wall of the V-shaped groove or at an inclination angle larger than the inclination angle of the other side wall. , The source / drain regions are formed in self-alignment with good controllability. At this time,
Since the other side wall of the V-shaped groove also has a taper, the ion implantation into one side wall is not hindered.

Impurity ion implantation for writing information and element isolation is performed on the other side wall having a taper of a V-shaped groove from the direction perpendicular to the semiconductor substrate, so that information writing and element isolation are controlled. It can be performed with good performance and stability. When the gate electrode is formed by etching, since the base is a V-shaped groove, the coverage of the gate electrode material is improved and no etching residue occurs.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings. Here, FIG. 1 is a perspective sectional view of a memory cell array according to an embodiment of the present invention, and FIG. 2 is a process sectional view illustrating a method for manufacturing a memory cell array according to the embodiment of the present invention. In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numeral, and the repeated description thereof will be omitted.

In FIG. 1, the main part of the memory cell array is such that a plurality of V-shaped grooves 22 are formed in parallel on a P-type silicon substrate 21, and one side wall 22a of the V-shaped groove 22 has an N-type source / drain region 23. And a plurality of V-shaped grooves 2 are formed.
2, a plurality of gate electrodes 24 are formed in a direction orthogonal to the V-shaped groove 22 via a gate oxide film 25, and the other side wall 22b of the V-shaped groove 22 is a channel region or an element isolation region. It has become an area.

Next, a method of manufacturing such a memory cell array will be described with reference to FIG. First, (100)
An oxide film (not shown) as a protective film is formed on the main surface of the P-type silicon substrate 21 having a crystal plane. Next, after forming a photoresist film (not shown) on this oxide film,
The P-type silicon substrate 2 is formed by using the photolithography technique.
The photoresist film is opened on the region 1 in which the V-shaped groove is to be formed.

Then, using this photoresist film as a mask, the oxide film is removed by etching, and anisotropic wet etching with a potassium hydroxide (KOH) solution or a trimethylammonium hydroxide (TMAH) solution is performed to obtain a P type. A plurality of V-shaped grooves 22 arranged in parallel are formed on the surface of the silicon substrate 21.

In this case, the V-shaped groove 22 has a width of, for example, 1 to 2 μm and a depth of, for example, 0.5 to 1 μm. After that, the photoresist film is removed by ashing,
The oxide film is also removed. In addition, potassium hydroxide (KOH) solution or trimethylammonium hydroxide (TM
In the anisotropic wet etching using the (AH) solution, the oxide film is hardly etched and the (111) plane is hardly etched in the P-type silicon substrate 21,
In the (100) plane P-type silicon substrate 21, the amount of side etching is small (see FIG. 2A).

Next, thermal oxidation is performed in a high temperature oxygen atmosphere,
After depositing a gate oxide film 25 on the V-shaped groove 22,
For example, arsenic (As) is formed on one side wall 22a of the V-shaped groove 22.
Ion implantation 105 is performed with an N-type impurity such as the above at a concentration of about 3 × 10 ¹⁵ cm ⁻² in an oblique direction.

At this time, the N-type impurity is injected only into the one side wall 22a so that it is parallel to the other side wall 22b of the V-shaped groove 22 or slightly larger than the inclination angle of the other side wall 22b, for example, 35 °. Ion implantation 1 at ~ 40 °
05. As a result, the N-type source / drain region 23 is formed on one side wall 22a of the V-shaped groove 22, and the other side wall 22 is formed.
b is a channel region or an element isolation region (see FIG. 2).
(B)).

Next, a polysilicon layer which is a gate electrode material is deposited on the gate oxide film 25 by the CVD method, and then the polysilicon layer is patterned using photolithography and etching techniques to form a plurality of gate electrodes 24. , Is formed in a direction orthogonal to the V-shaped groove 22 so as to extend over the plurality of V-shaped grooves 22 (see FIG. 2C).

After that, a photoresist film 26 is deposited on the P-type silicon substrate 21, and the photoresist film 26 is formed on the element isolation region formation scheduled region between the MOS transistors by using the photolithography technique. Thereafter, for example, boron (B) is ion-implanted 106 at a dose amount of about 3 × 10 ¹³ cm ^-2 through the opening 26a of the photoresist film 26 to perform element isolation.

Further, when writing information to a desired MOS transistor, a photolithography technique is used to open a region of the photoresist film 26 where a channel region is to be formed, and the photoresist film 26 is used as a mask for boron (B ) Write ion implantation (see FIG. 2D),
Change the threshold value of the MOS transistor. Then, the photoresist film 26 is removed by ashing to complete the memory cell array (see FIG. 1).

As described above, in this embodiment, the one side wall 22a having the taper of the V-shaped groove 22 is parallel to the other side wall 22b of the V-shaped groove 22 or slightly larger than the inclination angle of the other side wall 22b. By ion-implanting the impurities 105 from the oblique direction, the source / drain regions 23 are easily self-aligned with good controllability.

Ion implantation 106 of impurities for writing information and separating elements is performed from the direction perpendicular to the semiconductor substrate 21 to the other side wall 22b having the taper of the V-shaped groove 22. Therefore, information writing and element isolation can be performed stably with good controllability.

After depositing the polysilicon layer by the CVD method,
When patterning the polysilicon layer using photolithography and etching techniques, the underlying V-shaped groove 2
2, the coverage of the polysilicon layer is good,
There is no etching residue on the polysilicon layer. Therefore, the highly reliable gate electrode 24 is formed. Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say,

Although the memory cell array is formed on the P-type silicon substrate in the present embodiment, it may be formed on the N-type silicon substrate. In this case, the source / drain regions are of P type, and N type is used as the impurity for writing information and element isolation. Further, as N-type impurities, arsenic (As)
In addition, phosphorus (P) may be used, and gallium (Ga) or the like may be used as the P-type impurity in addition to boron (B).

[0034]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows. According to the present invention, since one side wall of the V-shaped groove has a taper, impurities are ion-implanted in an oblique direction, particularly in parallel to the other side wall of the V-shaped groove or at an inclination angle larger than the inclination angle of the other side wall. The / drain region is self-aligned and easily formed with good controllability. As a result, the mask forming step is not necessary, and the number of steps can be reduced.

Since the impurity ion implantation for writing information and element isolation is performed to the other side wall having the taper of the V-shaped groove from the direction perpendicular to the semiconductor substrate, the information writing and element isolation is performed. Can be performed stably with good controllability, and high integration can be achieved without lowering the drive capability of the MOS transistor.

Furthermore, when the gate electrode is formed by etching, since the base is a V-shaped groove, the coverage of the gate electrode material is improved and no etching residue is generated, so that the reliability of the MOS transistor can be improved.

[Brief description of drawings]

FIG. 1 is a perspective sectional view of a memory cell according to an embodiment of the present invention.

2A to 2D are process cross-sectional views illustrating a method for manufacturing a memory cell according to an embodiment of the present invention.

FIG. 3 is a perspective cross-sectional view of a memory cell using a conventional flat cell structure.

FIG. 4 is a perspective cross-sectional view of another conventional memory cell.

5A to 5D are process cross-sectional views explaining a method of manufacturing another memory cell which is a conventional example.

FIG. 6 is a process cross-sectional view illustrating the method of manufacturing another memory cell that is the conventional example.

7A and 7B are process cross-sectional views illustrating a method for manufacturing another memory cell which is a conventional example.

[Explanation of symbols]

 21 P-type silicon substrate 22 V-shaped groove 22a One side wall 22b Other side wall 23 N-type source / drain region 24 Gate electrode 25 Gate oxide film 26 Photoresist film

Claims (3)

[Claims] 1. A plurality of V-shaped grooves are formed on a semiconductor substrate, a source / drain region is formed on one side wall of the plurality of V-shaped grooves, and a channel region is formed on the other side wall of the plurality of V-shaped grooves. And a plurality of gate electrodes are formed on the plurality of V-shaped grooves in a direction intersecting the plurality of V-shaped grooves via a gate insulating film. 2. A step of forming a plurality of V-shaped grooves on a surface portion of a semiconductor substrate, a step of forming a gate insulating film on the plurality of V-shaped grooves, and the semiconductor substrate on one side wall of the V-shaped grooves. Is a step of ion-implanting impurities of different conductivity types from an oblique direction to form source / drain regions, and a step of forming a plurality of gate electrodes on the gate insulating film in a direction intersecting with the plurality of V-shaped grooves. And a step of ion-implanting impurities having the same conductivity type as that of the semiconductor substrate into the other side walls of the plurality of V-shaped grooves in a direction perpendicular to the semiconductor substrate. 3. The plurality of V-shaped grooves are formed by anisotropic wet etching, and the impurities of different conductivity types are parallel to one side wall of the V-shaped groove or to the other side wall of the V-shaped groove. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the ion implantation is performed at an inclination angle larger than the inclination angle.