JPH0924635A - Thermal print head - Google Patents

Thermal print head

Info

Publication number
JPH0924635A
JPH0924635A JP8217229A JP21722996A JPH0924635A JP H0924635 A JPH0924635 A JP H0924635A JP 8217229 A JP8217229 A JP 8217229A JP 21722996 A JP21722996 A JP 21722996A JP H0924635 A JPH0924635 A JP H0924635A
Authority
JP
Japan
Prior art keywords
pads
driving
pad
input
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8217229A
Other languages
Japanese (ja)
Inventor
Takanari Nagahata
▲隆▼也 長畑
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP8217229A priority Critical patent/JPH0924635A/en
Publication of JPH0924635A publication Critical patent/JPH0924635A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19043Component type being a resistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electronic Switches (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To simplify a wiring pattern to implement ICs for driving a heat resisting element on a head by partially-disposing the ICs, an output pad for driving signals, respective input pads of GND, VDD signals and STR signals, output pads of data, clock and latch signals at respective sides. SOLUTION: In driving ICs 1 for a thermal printer head, an output pad train 2 corresponding to 64 bits and is constituted of 64 output pods 21 in the vicinity of the upper side. An input pad train 3 which is constituted of three pairs of input pads 33 of GND, an input pad 32 for VDD signals, and an input pad 33 for STR signals is fitted in the vicinity of the lower side. An input pad train 4 which is constituted of an input pad 41 for clock signals, an input pad 42 for data signals, and an input pad 43 for latch signals is fitted in the vicinity of the left side. An output pad 5 for output signals corresponding to respective input signals is fitted in the vicinity of the right side, and input/output pads 41, 51: 43, 53 are connected by use of pattern in the IC 1.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、感熱方式、熱転写
方式のファクシミリやプリンタ等に使用するサーマルプ
リントヘッドに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thermal print head for use in a heat-sensitive type or thermal transfer type facsimile or printer.

【0002】[0002]

【従来の技術】ファクシミリやプリンタ等に使用される
サーマルプリントヘッドは、一般に印字走査方向に延在
する発熱抵抗体と、抵抗体を駆動するための駆動用IC
と、抵抗体とICを連絡するための配線パターンとを有
する。サーマルプリントヘッドは、印字ドット数に応じ
た発熱抵抗体を有し、この抵抗体を印字ドットパターン
に則して駆動するためのデータ信号を各抵抗体に送るた
めに、幾つかの抵抗体を一まとめにした組数に相当する
数のICが設けられる。
2. Description of the Related Art A thermal print head used in a facsimile, a printer or the like generally has a heating resistor extending in a print scanning direction and a driving IC for driving the resistor.
And a wiring pattern for connecting the resistor and the IC. The thermal print head has a heating resistor corresponding to the number of print dots, and several resistors are provided in order to send a data signal for driving the resistor according to the print dot pattern to each resistor. ICs are provided in a number corresponding to the number of sets combined.

【0003】この駆動用ICは、一般に図4に示すよう
に、IC100上面の1辺の近傍に、発熱抵抗体を駆動
する信号を送り出す全ての出力パッド101を配列し
て、出力パッド列102とし、対向辺の近傍に入力信号
(データ、クロック、ラッチ、GND、VDD、STR等
の信号)を受ける全ての入力パッド103を配列して、
入力パッド列104としている。
In this driving IC, as shown in FIG. 4, generally, all the output pads 101 that send out signals for driving the heating resistors are arranged near one side of the upper surface of the IC 100 to form an output pad row 102. , All input pads 103 for receiving input signals (data, clock, latch, GND, V DD , STR, etc.) are arranged in the vicinity of the opposite side,
The input pad row 104 is used.

【0004】[0004]

【発明が解決しようとする課題】ところで、殆どのサー
マルプリントヘッドでは、データ、クロック、ラッチ、
GND、VDDの信号は各1系統しか使用していないた
め、セラミック基板上又はフレキシブルケーブル上で各
ICの信号を接続している。又、STRの信号は数系統
に分割して使用している。
By the way, in most thermal print heads, data, clock, latch,
Since only one system is used for each of GND and V DD signals, signals of each IC are connected on a ceramic substrate or a flexible cable. The STR signal is divided into several systems for use.

【0005】しかしながら、セラミック基板上で上記の
如き駆動用ICの配線接続を行う場合、出力パッドを1
辺寄りに集中配置してあるので、入力信号の配線は他の
対向する1辺側となり、基板上に複雑な配線パターンを
形成したり、多層配線を行ったりする必要がある。それ
ばかりか、VDDやGNDの電圧低下を防ぐにはVDDやG
NDに対応する配線パターン幅をできるだけ大きくしな
ければならないが、出力パッドを1辺に偏って配置して
あるので、限られた配線領域内で十分な幅のパターンを
形成するのが困難である。
However, when the wiring connection of the driving IC as described above is made on the ceramic substrate, the output pad is set to 1
Since the input signals are concentrated on one side, the wiring for input signals is on the other side facing each other, and it is necessary to form a complicated wiring pattern on the substrate or perform multilayer wiring. Not only that, but to prevent the voltage drop of V DD and GND, V DD and G
Although the wiring pattern width corresponding to ND must be made as large as possible, it is difficult to form a pattern having a sufficient width in a limited wiring region because the output pads are arranged on one side. .

【0006】又、フレキシブルケーブル上で配線する場
合、セラミック基板との接続部の信号数が多くなるた
め、信頼性の劣化やコスト高につながる。このように、
セラミック基板上の配線とフレキシブルケーブル上の配
線とのパターン抵抗の相違、及びICの使用上必要な信
号系と不要な信号系との関連性を考慮すると、従来の駆
動用ICは通常のセラミック基板又はフレキシブルケー
ブルのどちらかに配線しなければならないのに、実際は
セラミック基板又はフレキシブルケーブル上で殆ど全て
の配線を行っているため、上記電圧低下又は信頼性の劣
化等の問題点が生ずる。
Further, when wiring is performed on a flexible cable, the number of signals at the connecting portion with the ceramic substrate increases, which leads to deterioration of reliability and high cost. in this way,
Considering the difference in the pattern resistance between the wiring on the ceramic substrate and the wiring on the flexible cable, and the relationship between the signal system necessary for using the IC and the unnecessary signal system, the conventional driving IC is a normal ceramic substrate. Alternatively, the wiring must be provided on either the flexible cable, but in reality, almost all the wiring is performed on the ceramic substrate or the flexible cable, which causes the problems such as the voltage drop and the deterioration of reliability.

【0007】従って、本発明の目的は、配線パターンを
単純化すると共に、配線パターンでの電圧低下を防止
し、信頼性を向上できるサーマルプリントヘッドを提供
することにある。
SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a thermal print head which simplifies a wiring pattern, prevents a voltage drop in the wiring pattern, and improves reliability.

【0008】[0008]

【課題を解決するための手段】前記目的を達成する本発
明の請求項1のサーマルプリントヘッドでは、絶縁基板
上にグレーズ層を形成し、このグレーズ層上に発熱抵抗
体を形成し、この発熱抵抗体に通電する電極パターンを
形成し、発熱抵抗体を駆動する駆動用ICを設けたもの
において、前記駆動用ICは、平面視が四角形のICの
上面に、1辺の近傍に沿って発熱抵抗体駆動用信号の出
力パッドを等間隔で配置し、この辺の対向辺の近傍の両
端と真中にGNDの入力パッドを配置し且つGNDの入
力パッドの間にVDD信号の入力パッドとSTR信号の入
力パッドを配置し、残りの辺のうちの1辺の近傍に沿っ
てデータ、クロック及びラッチ信号の入力パッドを等間
隔で配置し、別の残りの辺の近傍に沿ってデータ、クロ
ック及びラッチ信号の出力パッドを等間隔で配置してな
るものであることを特徴とする。
In the thermal print head according to claim 1 of the present invention which achieves the above object, a glaze layer is formed on an insulating substrate, and a heating resistor is formed on the glaze layer. An electrode pattern for energizing a resistor is formed, and a driving IC for driving a heating resistor is provided. The driving IC generates heat along the vicinity of one side on the upper surface of the IC having a quadrangular shape in plan view. The resistor driving signal output pads are arranged at equal intervals, the GND input pad is arranged in the middle of both ends in the vicinity of the opposite side of this side, and the V DD signal input pad and the STR signal are arranged between the GND input pads. Input pads for data, clock, and latch signals are arranged at equal intervals along the vicinity of one of the remaining sides, and data, clock, and latch signals are arranged along the vicinity of another remaining side. Latch signal Characterized in that it is made of the output pad arranged at equal intervals.

【0009】又、請求項2のサーマルプリントヘッドで
は、絶縁基板上にグレーズ層を形成し、このグレーズ層
上に発熱抵抗体を形成し、この発熱抵抗体に通電する配
線パターンを形成し、発熱抵抗体を駆動する駆動用IC
を設けたものにおいて、前記駆動用ICは、平面視が四
角形のICの上面に、1辺の近傍に沿って発熱抵抗体駆
動用信号の出力パッドを等間隔で配置し、この辺の対向
辺の近傍の両端と真中にGNDの入力パッドを配置し且
つGNDの入力パッドの間にVDD信号の入力パッドとS
TR信号の入力パッドを配置し、残りの辺のうちの1辺
の近傍に沿ってデータ、クロック及びラッチ信号の入力
パッドを等間隔で配置し、別の残りの辺の近傍にデータ
信号の出力パッドを配置してなるものであることを特徴
とする。
Further, in the thermal print head according to the present invention, a glaze layer is formed on the insulating substrate, a heating resistor is formed on the glaze layer, and a wiring pattern for energizing the heating resistor is formed to generate heat. Driving IC for driving resistor
In the driving IC, the output pads of the heating resistor driving signals are arranged at equal intervals along the vicinity of one side on the upper surface of the IC having a quadrangular shape in plan view, and the pads on the opposite side of this side are arranged. A GND input pad is arranged at both ends and in the middle of the vicinity, and a VDD signal input pad and an S pad are provided between the GND input pads.
The TR signal input pad is arranged, the data, clock and latch signal input pads are arranged at equal intervals along the vicinity of one of the remaining sides, and the data signal is output near the other remaining side. It is characterized in that pads are arranged.

【0010】請求項1及び請求項2のサーマルプリント
ヘッドでは、いずれの駆動用ICも、従来のように全て
の出力パッドをICの1辺付近に配置し、全ての入力パ
ッドを対向辺付近に配置するのとは異なり、全パッドの
うち、GNDの入力パッド、VDD信号の入力パッド及び
STR信号の入力パッドを、発熱抵抗体駆動用信号の出
力パッドが設けられる辺に対向する1辺付近に配置し、
データ、クロック及びラッチ信号の入力パッドを残りの
辺のうちの1辺付近に配置し、データ、クロック及びラ
ッチ信号(請求項2ではデータ信号のみ)の出力パッド
を別の残りの辺付近に配置してある。即ち、従来のIC
では、2辺のみにパッドを配置していたのに対し、本発
明のサーマルプリントヘッドにおけるICでは、制御上
必要な信号とパターン抵抗を加味して信号系を分類し、
信号系に応じて、IC列に直交する他の辺にもパッドを
分割配置したので、配線パターンを単純化でき、しかも
パターン幅を大きくすることができる。この結果、配線
パターンでの電圧低下が防止され、サーマルプリントヘ
ッドの信頼性が向上する。
In the thermal print heads of claims 1 and 2, all the output pads of any driving IC are arranged near one side of the IC as in the conventional case, and all the input pads are arranged near the opposite side. Unlike the arrangement, the GND input pad, the V DD signal input pad, and the STR signal input pad among all the pads are located near one side facing the side where the heating resistor driving signal output pad is provided. Placed in
An input pad for data, clock and latch signals is arranged near one of the remaining sides, and an output pad for data, clock and latch signals (only the data signal in claim 2) is arranged near another remaining side. I am doing it. That is, conventional IC
In contrast, while the pads are arranged only on two sides, in the IC in the thermal print head of the present invention, the signal system is classified in consideration of the signal necessary for control and the pattern resistance,
According to the signal system, the pads are also arranged on the other side orthogonal to the IC row, so that the wiring pattern can be simplified and the pattern width can be increased. As a result, the voltage drop in the wiring pattern is prevented, and the reliability of the thermal print head is improved.

【0011】[0011]

【発明の実施の形態】以下、本発明を実施の形態に基づ
いて説明する。但し、本発明は駆動用ICに特徴があ
り、絶縁基板上のグレーズ層や発熱抵抗体の形態は従来
のものと特に変わらないので、以下では駆動用IC及び
それに係る配線パターンを中心に説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on embodiments. However, the present invention is characterized by the driving IC, and the forms of the glaze layer and the heating resistor on the insulating substrate are not particularly different from the conventional ones. Therefore, the driving IC and its wiring pattern will be mainly described below. .

【0012】図1はその一実施形態のサーマルプリント
ヘッドにおける駆動用ICの平面を示す。この駆動用I
C1は、1辺(図中の上辺、発熱抵抗体が存在する側の
辺)の近傍に、64ビット分に相当する出力パッド列2
が設けられている。出力パッド列2は64個の出力パッ
ド21からなり、出力パッド21は等間隔を置いて並列
する。出力パッド21は、サーマルプリントヘッドの発
熱抵抗体を駆動する信号を出力するもので、各々の印字
出力信号を対応する発熱抵抗体に送り出す。
FIG. 1 shows a plane of a driving IC in the thermal print head of the embodiment. This drive I
C1 is an output pad row 2 corresponding to 64 bits in the vicinity of one side (the upper side in the figure, the side on which the heating resistor exists).
Is provided. The output pad row 2 is composed of 64 output pads 21, and the output pads 21 are arranged in parallel at equal intervals. The output pad 21 outputs a signal for driving the heating resistor of the thermal print head, and sends each print output signal to the corresponding heating resistor.

【0013】上辺の対向辺(図中の下辺)の近傍には、
GND、VDD、STR信号の入力パッド列3が設けられ
る。入力パッド列3のうち、両端と真中に2個のパッド
を近接して配置した入力パッド31はGNDで、GND
の間にVDD信号の入力パッド32、STR信号の入力パ
ッド33を配置してある。別の1辺(図中の左辺)の近
傍には、クロック信号の入力パッド41、データ信号の
入力パッド42、ラッチ信号の入力パッド43を順に配
した入力パッド列4を設けてある。この対向辺(図中の
右辺)の近傍には、各入力信号に対応する出力信号の出
力パッド列5が設けられている。クロック信号の入力パ
ッド41と出力パッド51、ラッチ信号の入力パッド4
3と出力パッド53は、それぞれIC1内のパターンで
接続されている。出力パッド列5は、クロック信号の出
力パッド51、データ信号の出力パッド52、ラッチ信
号の出力パッド53からなる。
In the vicinity of the opposite side of the upper side (lower side in the figure),
An input pad row 3 for GND, V DD and STR signals is provided. In the input pad row 3, the input pad 31 in which two pads are arranged close to each other at both ends and in the middle is GND.
An input pad 32 for the V DD signal and an input pad 33 for the STR signal are arranged between them. An input pad row 4 in which a clock signal input pad 41, a data signal input pad 42, and a latch signal input pad 43 are arranged in this order is provided near another one side (the left side in the drawing). An output pad row 5 for an output signal corresponding to each input signal is provided near the opposite side (right side in the figure). Clock signal input pad 41 and output pad 51, latch signal input pad 4
3 and the output pad 53 are connected by a pattern in the IC 1. The output pad row 5 includes a clock signal output pad 51, a data signal output pad 52, and a latch signal output pad 53.

【0014】このような駆動用IC1では、ICの左右
の辺に1系統の信号(クロック、データ、ラッチ信号)
の入出力パッドを配置してあるので、この信号系の配線
パターンはICの下側に形成し、各パッドと配線パター
ン間をワイヤボンディングしてもよいし、或いは、隣接
するICのパッド間をワイヤボンディングしてもよい。
又、下辺(出力パッドの配列される辺に対向する辺)に
配した入力パッド列3におけるパッド間の間隔が十分に
大きいため、これらのパッドの信号系(GND、VDD
STR)の入力パッドに係る配線パターンを単純化でき
るだけでなく、パターンを広幅にすることができる。
In such a driving IC 1, one system of signals (clock, data, latch signal) is provided on the left and right sides of the IC.
Since the input / output pads are arranged, the signal system wiring pattern may be formed on the lower side of the IC and wire bonding may be performed between each pad and the wiring pattern, or between adjacent IC pads. You may wire-bond.
Further, since the spacing between the pads in the input pad row 3 arranged on the lower side (the side opposite to the side where the output pads are arranged) is sufficiently large, the signal system (GND, V DD ,
Not only can the wiring pattern associated with the (STR) input pad be simplified, but the pattern can be made wider.

【0015】このIC1をサーマルプリントヘッドに実
装する場合、例えば通常のA4サイズのヘッド(200
DPI)への適用では、図1に示す64ビットIC1を
27個使用することになる。図2に、ヘッドに実装した
場合の各IC1の接続形態を説明する図を示す。各(又
は2〜7個の)IC毎に、入力パッド列3に並ぶGN
D、VDD、STRの各パッドをセラミック基板上の対応
配線パターンにワイヤボンディングによって接続し、G
ND、VDD、STRの3信号を各パターンから入力す
る。
When this IC1 is mounted on a thermal print head, for example, a normal A4 size head (200
When applied to DPI, 27 64-bit IC1 shown in FIG. 1 are used. FIG. 2 is a diagram illustrating a connection form of each IC 1 when mounted on the head. GN arranged in the input pad row 3 for each (or 2 to 7) ICs
Connect each pad of D, V DD and STR to the corresponding wiring pattern on the ceramic substrate by wire bonding, and
Three signals of ND, V DD and STR are input from each pattern.

【0016】入出力パッド列4,5にある他の信号(ク
ロック、データ、ラッチ)のパッドを全ICで1系統に
まとめるために、他の信号系の配線パターンはIC1の
下側において左右方向に平行に形成してあり、このIC
1に対しては各パッドに対応する3本の配線を並列させ
てある。各入出力パッドと配線パターンとの接続は、ワ
イヤボンディングにより行う。又は、図2に示すよう
に、各パッド間を直接ワイヤボンディング60によって
接続してもよい。或いは、直接ワイヤボンディング60
の以外にも、各ICとの間にワイヤボンディング用の中
継点(パッド)を設け、IC上のパッドからのワイヤを
中継点にボンディングし、隣のICの対応パッドからの
ワイヤも同じ中継点にボンディングする態様も構わな
い。
In order to combine the pads of other signals (clock, data, latch) in the input / output pad rows 4 and 5 into one system for all ICs, the wiring pattern of the other signal system is in the left and right direction under the IC1. This IC is formed parallel to
For No. 1, three wires corresponding to each pad are arranged in parallel. The connection between each input / output pad and the wiring pattern is performed by wire bonding. Alternatively, as shown in FIG. 2, the pads may be directly connected by wire bonding 60. Alternatively, direct wire bonding 60
In addition to the above, a relay point (pad) for wire bonding is provided between each IC, and the wire from the pad on the IC is bonded to the relay point, and the wire from the corresponding pad of the adjacent IC is also the same relay point. It does not matter how the bonding is performed.

【0017】ここで、図1に示す64ビットIC1の実
寸例を示すと、寸法aは約5〜6mmで、寸法bは約
1.5mmであり、このサイズのIC1を前記のように
配線すると、フレキシブルケーブル上でのセラミック基
板との接続部のピッチを2.7mm程度確保できること
になる。図3は、他の実施形態に係る駆動用ICを搭載
したヘッド基板を示す部分図である。ここで示す駆動用
IC10は、図2に示したものと相違し、データ、クロ
ック及びラッチ信号用のパッド41,42,43は、出
力用パッド列2の配列される辺に直交する辺の1辺(図
では左辺)にのみ設けられており、この辺に対向する辺
(図では右辺)には、データ信号の出力パッド52のみ
が設けられている。
Here, showing an actual size example of the 64-bit IC1 shown in FIG. 1, the dimension a is about 5 to 6 mm, and the dimension b is about 1.5 mm. When the IC1 of this size is wired as described above. Therefore, the pitch of the connection portion with the ceramic substrate on the flexible cable can be secured at about 2.7 mm. FIG. 3 is a partial view showing a head substrate on which a driving IC according to another embodiment is mounted. The driving IC 10 shown here is different from that shown in FIG. 2, and the pads 41, 42, 43 for the data, clock and latch signals are one of the sides orthogonal to the side on which the output pad row 2 is arranged. It is provided only on the side (the left side in the figure), and only the output pad 52 for the data signal is provided on the side (the right side in the figure) facing this side.

【0018】この実施形態では、基板20の上面に、各
IC10の下面を通り、出力用パッド列2に平行に、ク
ロック、データ、及びラッチ用の配線パターン61,6
3が形成され、また左端及び右端のICの左側及び右側
と、各IC間に、ICの各クロック、データ、及びラッ
チ用のパッド41,42,43に対応して中継点(パッ
ド)71,72,73が設けられ、各IC10の左側の
中継点71,72,73と、各ICの入力パッド41,
42,43がボンディングワイヤ81,82,83で接
続されている。またデータ出力パッド52がIC10の
右側のデータ入力中継点42に接続されている。このデ
ータ出力パッド52と次のIC10のデータ入力パッド
42とは、直接ボンディングワイヤにより接続されても
よい。
In this embodiment, wiring patterns 61, 6 for clock, data, and latch are formed on the upper surface of the substrate 20 in parallel with the output pad row 2 through the lower surface of each IC 10.
3 are formed, and between the ICs on the left and right sides of the ICs at the left and right ends and between the ICs, relay points (pads) 71, 41 corresponding to the pads 41, 42, 43 for each clock, data, and latch of the IC 72, 73 are provided, the relay points 71, 72, 73 on the left side of each IC 10 and the input pad 41,
42 and 43 are connected by bonding wires 81, 82 and 83. The data output pad 52 is connected to the data input relay point 42 on the right side of the IC 10. The data output pad 52 and the data input pad 42 of the next IC 10 may be directly connected by a bonding wire.

【0019】この実施形態に係るIC10は、クロック
及びラッチ信号用の入力と出力の内部配線が不要であ
る。
The IC 10 according to this embodiment does not require internal wiring for input and output for clock and latch signals.

【0020】[0020]

【発明の効果】本発明の請求項1及び請求項2のサーマ
ルプリントヘッドでは、以上説明したように、いずれも
搭載する発熱抵抗体駆動用ICが、平面視四角形のIC
の上面において、発熱抵抗体駆動用信号の出力パッド
と、GNDの入力パッド、VDD信号の入力パッド及びS
TR信号の入力パッドと、データ、クロック及びラッチ
信号の入力パッドと、データ、クロック及びラッチ信号
(請求項2ではデータ信号のみ)の出力パッドとを、そ
れぞれ信号系に応じて各辺に分割配置したので、ICを
ヘッドに実装する際に絶縁基板の配線パターンを単純化
又は削減でき、しかもパターン幅を広くしてパターン抵
抗を低く抑えることができる。このため、配線パターン
での電圧低下が防止され、高い信頼性が得られ、コスト
も安くなる。
As described above, in the thermal print heads according to the first and second aspects of the present invention, the heating resistor driving ICs mounted on both are ICs having a quadrangular shape in plan view.
On the upper surface of the heater, a heating resistor driving signal output pad, a GND input pad, a V DD signal input pad and S
An input pad for the TR signal, an input pad for the data, clock and latch signals, and an output pad for the data, clock and latch signals (only the data signal in claim 2) are separately arranged on each side according to the signal system. Therefore, when the IC is mounted on the head, the wiring pattern of the insulating substrate can be simplified or reduced, and the pattern width can be widened to reduce the pattern resistance. Therefore, the voltage drop in the wiring pattern is prevented, high reliability is obtained, and the cost is reduced.

【0021】又、ユーザのカスタム要求に幅広く対応で
きる。
Further, it is possible to meet a wide range of user custom requests.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施形態に係るサーマルプリントヘ
ッドにおける駆動用ICの平面図である。
FIG. 1 is a plan view of a driving IC in a thermal print head according to an embodiment of the present invention.

【図2】図1のICをサーマルプリントヘッドに実装す
る場合において、各ICの接続形態を説明するための図
である。
FIG. 2 is a diagram for explaining a connection form of each IC when the IC of FIG. 1 is mounted on a thermal print head.

【図3】本発明の別実施形態に係るサーマルプリントヘ
ッドにおける駆動用ICの実装例及びその接続形態を説
明するための図である。
FIG. 3 is a diagram for explaining a mounting example of a driving IC and a connection form thereof in a thermal print head according to another embodiment of the present invention.

【図4】従来の一般的な駆動用ICの平面図である。FIG. 4 is a plan view of a conventional general driving IC.

【符号の説明】[Explanation of symbols]

1,10 駆動用IC 2 駆動信号の出力パッド列 3 GND、VDD、STR信号の入力パッド列 4 クロック、データ、ラッチ信号の入力パッ
ド列 5 クロック、データ、ラッチ信号の出力パッ
ド列
1,10 Driving IC 2 Drive signal output pad row 3 GND, V DD , STR signal input pad row 4 Clock, data, latch signal input pad row 5 Clock, data, latch signal output pad row

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】絶縁基板上にグレーズ層を形成し、このグ
レーズ層上に発熱抵抗体を形成し、この発熱抵抗体に通
電する配線パターンを形成し、発熱抵抗体を駆動する駆
動用ICを設けたサーマルプリントヘッドにおいて、 前記駆動用ICは、平面視が四角形のICの上面に、1
辺の近傍に沿って発熱抵抗体駆動用信号の出力パッドを
等間隔で配置し、この辺の対向辺の近傍の両端と真中に
GNDの入力パッドを配置し且つGNDの入力パッドの
間にVDD信号の入力パッドとSTR信号の入力パッドを
配置し、残りの辺のうちの1辺の近傍に沿ってデータ、
クロック及びラッチ信号の入力パッドを等間隔で配置
し、別の残りの辺の近傍に沿ってデータ、クロック及び
ラッチ信号の出力パッドを等間隔で配置してなるもので
あることを特徴とするサーマルプリントヘッド。
1. A drive IC for driving a heating resistor by forming a glaze layer on an insulating substrate, forming a heating resistor on the glaze layer, forming a wiring pattern for energizing the heating resistor. In the provided thermal print head, the driving IC is mounted on the upper surface of the IC having a quadrangular shape in plan view.
Output pads for driving the heating resistor are arranged at equal intervals along the vicinity of the side, GND input pads are arranged at both ends and in the middle in the vicinity of the opposite side of this side, and V DD is provided between the GND input pads. A signal input pad and an STR signal input pad are arranged, and data is provided along the vicinity of one of the remaining sides,
Clock and latch signal input pads are arranged at equal intervals, and data, clock and latch signal output pads are arranged at equal intervals along the vicinity of another remaining side. Print head.
【請求項2】絶縁基板上にグレーズ層を形成し、このグ
レーズ層上に発熱抵抗体を形成し、この発熱抵抗体に通
電する配線パターンを形成し、発熱抵抗体を駆動する駆
動用ICを設けたサーマルプリントヘッドにおいて、 前記駆動用ICは、平面視が四角形のICの上面に、1
辺の近傍に沿って発熱抵抗体駆動用信号の出力パッドを
等間隔で配置し、この辺の対向辺の近傍の両端と真中に
GNDの入力パッドを配置し且つGNDの入力パッドの
間にVDD信号の入力パッドとSTR信号の入力パッドを
配置し、残りの辺のうちの1辺の近傍に沿ってデータ、
クロック及びラッチ信号の入力パッドを等間隔で配置
し、別の残りの辺の近傍にデータ信号の出力パッドを配
置してなるものであることを特徴とするサーマルプリン
トヘッド。
2. A driving IC for driving a heating resistor, comprising forming a glaze layer on an insulating substrate, forming a heating resistor on the glaze layer, forming a wiring pattern for energizing the heating resistor. In the provided thermal print head, the driving IC is mounted on the upper surface of the IC having a quadrangular shape in plan view.
Output pads for driving the heating resistor are arranged at equal intervals along the vicinity of the side, GND input pads are arranged at both ends and in the middle in the vicinity of the opposite side of this side, and V DD is provided between the GND input pads. A signal input pad and an STR signal input pad are arranged, and data is provided along the vicinity of one of the remaining sides,
A thermal print head, characterized in that input pads for clock and latch signals are arranged at equal intervals, and output pads for data signals are arranged near another remaining side.
【請求項3】前記駆動用ICのデータ、クロック及びラ
ッチ信号の入力パッドに対応して、それらの入力パッド
の近傍に位置する基板上の配線パターン部分に、それら
入力パッドに対向するパッドを形成し、これら配線パタ
ーンのパッド間を個別に結ぶ配線パターンを形成し、前
記駆動用ICのデータ、クロック及びラッチ信号の入力
パッドと配線パターンの対応パッドとをボンディングワ
イヤで接続したことを特徴とする請求項1又は請求項2
記載のサーマルプリントヘッド。
3. Pads facing the input pads of the drive IC are formed in a wiring pattern portion on the substrate near the input pads of the data, clock and latch signals corresponding to the input pads of the drive IC. Then, a wiring pattern for individually connecting the pads of these wiring patterns is formed, and the input pad for the data, clock and latch signals of the driving IC and the corresponding pad of the wiring pattern are connected by a bonding wire. Claim 1 or Claim 2
The thermal print head described.
JP8217229A 1996-08-19 1996-08-19 Thermal print head Pending JPH0924635A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8217229A JPH0924635A (en) 1996-08-19 1996-08-19 Thermal print head

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8217229A JPH0924635A (en) 1996-08-19 1996-08-19 Thermal print head

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP3181492A Division JPH0787199B2 (en) 1991-03-29 1992-02-19 Head drive IC and head substrate

Publications (1)

Publication Number Publication Date
JPH0924635A true JPH0924635A (en) 1997-01-28

Family

ID=16700877

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8217229A Pending JPH0924635A (en) 1996-08-19 1996-08-19 Thermal print head

Country Status (1)

Country Link
JP (1) JPH0924635A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6822164B2 (en) 2002-01-25 2004-11-23 Seiko Epson Corporation Semiconductor device and electro-optical device including the same
CN100337015C (en) * 2002-12-16 2007-09-12 日产自动车株式会社 Particulate filter regenerating device
KR101114760B1 (en) * 2008-03-07 2012-02-29 세이코 엡슨 가부시키가이샤 Head substrate, method for mounting driver ic on head substrate, and thermal head substrate

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6822164B2 (en) 2002-01-25 2004-11-23 Seiko Epson Corporation Semiconductor device and electro-optical device including the same
CN100337015C (en) * 2002-12-16 2007-09-12 日产自动车株式会社 Particulate filter regenerating device
KR101114760B1 (en) * 2008-03-07 2012-02-29 세이코 엡슨 가부시키가이샤 Head substrate, method for mounting driver ic on head substrate, and thermal head substrate

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