JPH09246336A - Method and device for inspecting wafer with pattern - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately inspect even a wafer which is patterned using different aligners. SOLUTION: Each correction value based on the error to a design coordinate is computed for every combination of aligners A, B and C and photomasks (a) to (i), and when wafers 40 with an actual pattern are inspected, the design coordinate is corrected by the combinational correction value of the aligner A and the photomask (a) which are used when the wafer 40 is patterned. A wafer with correction value setting pattern is formed for every combination of each aligner and each photomask, the error with design coordinate is measured for every wafer with correction value setting pattern, and the correction value for every combination of each aligner and photomask is computed based on the error of measurement. Consequently, as the difference in inspection result between the aligner and the photomask can be prevented, high inspection accuracy can be maintained even under the condition where the photomask is used in plurality of aligners, and the lowering of the yield of production of semiconductor device can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for inspecting a patterned wafer, and more particularly to a technique for correcting an error caused by distortion of an exposure apparatus and a photomask, and for example, a scanning electron microscope (Scanning Electron Micro).
Scopy) is used to inspect a patterned wafer.

[0002]

2. Description of the Related Art Generally, a semiconductor integrated circuit device (hereinafter referred to as I
Called C. ) Is a semiconductor wafer (hereinafter referred to as a wafer).
It is manufactured by transferring the pattern of the photomask onto the substrate using an exposure device and patterning. The quality of the transfer of the pattern onto the wafer by the exposure apparatus has a great influence on the productivity such as the manufacturing yield of ICs. The inspection method is conventionally practiced.

With the high integration and high speed of today's ICs,
The pattern transferred to the wafer has become extremely fine. Therefore, a method for inspecting a wafer with a pattern using a scanning electron microscope having an extremely high resolution has been proposed for inspecting defects in this ultra-miniaturized pattern.

Incidentally, as an example in which a patterned wafer inspection technique using a scanning electron microscope is described, there is JP-A-59-134842.

[0005]

By the way, in an IC manufacturing plant, a plurality of exposure apparatuses of the same type are arranged in parallel to perform productivity, and the patterning work of the same type is divided and carried out. You can improve the sex.

However, when a plurality of exposure apparatuses are used, the characteristics such as the error of the stage and the aberration of the lens are different between the individual exposure apparatuses, so that the patterns of the same type of photomask are exposed separately. When each patterned wafer transferred by the device is inspected by the same patterned wafer inspection device, a difference occurs in the inspection result between the patterned wafers, especially the pattern using the scanning electron microscope. The present inventor has revealed that there is a problem that the difference in the inspection result becomes remarkable in the case of the attached wafer inspection device.

It is an object of the present invention to provide a patterned wafer inspection technique capable of accurately inspecting patterned wafers that have been subjected to the same type of patterning work by different exposure apparatuses of the same type.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, the patterned wafer inspecting apparatus for inspecting the patterned wafer patterned by the exposure apparatus and the photomask is determined in advance for each combination of each exposure apparatus and each photomask based on the error with respect to the design coordinates. A combination of a correction value memory that stores a correction value and an exposure device and a photomask used for patterning a patterned wafer to be inspected when inspecting an actual patterned wafer that is patterned by the exposure device and the photomask. And a controller that reads the correction value corresponding to the above from the correction value memory and corrects the design coordinates based on the read correction value.

The correction value for each combination of each exposure device and each photomask to be stored in the correction value memory can be obtained in advance as follows. A wafer with each correction value setting pattern is created for each combination of each exposure apparatus and each photomask. The error with respect to the design coordinates is measured for each wafer with the correction value setting pattern, and each correction value for each combination of each exposure apparatus and each photomask is obtained based on the measured error.

When an actual patterned wafer patterned by the exposure apparatus and the photomask is inspected by the patterned wafer inspection apparatus, the exposure apparatus and the photomask used for patterning the actual patterned wafer to be inspected The correction value corresponding to the combination is read from the correction value memory by the controller, the design coordinates are corrected, and the stage and the like are controlled.

[0013]

1 is a schematic diagram showing a patterned wafer inspection method according to an embodiment of the present invention. FIG.
FIG. 1 is a schematic view showing a patterned wafer inspection apparatus which is an embodiment of the present invention. FIG. 3 and subsequent figures are explanatory diagrams for explaining the operation.

In the present embodiment, the patterned wafer inspection method according to the present invention is carried out by a patterned wafer inspection apparatus equipped with a scanning electron microscope (hereinafter referred to as a patterned wafer inspection). The scanning electron microscope 2 of the patterned wafer inspection apparatus 1 includes an electron beam generation / molding unit 3 for generating and shaping an electron beam, a deflecting unit 4 for deflecting the electron beam, and an electron beam on an inspected wafer. Irradiation position control unit 5 for controlling the irradiation of the wafer to be inspected, a stage 6 for mounting and holding the inspection wafer, and a controller 7 for setting the irradiation position of the inspection wafer and controlling the stage 6. A signal detection unit 8 that detects a signal obtained by irradiating the wafer to be inspected with an electron beam and a position specifying unit 9 that specifies a position on the wafer to be inspected by using the detection signal are provided. Further, the patterned wafer inspection apparatus 1 is provided with a correction value memory 10 for storing each correction value obtained in advance based on the error with respect to the design coordinates for each combination of each exposure apparatus and each photomask. The correction value memory 10 is connected to the controller 7 so that the correction value designated by the read command of the controller 7 is appropriately transmitted to the controller 7.

The operation of the patterned wafer inspection apparatus 1 will be described below. The electron beam from the electron beam generating / shaping unit 3 is deflected by the deflecting unit 4 and is applied to a predetermined place on the wafer to be inspected. Secondary electrons, X-rays, etc. emitted to the outside by the irradiation of the electron beam are detected and amplified by the signal detection unit 8 to generate a detection signal. The position specifying unit 9 detects the detection signal from the signal detection unit 8, the deflection signal from the irradiation position control unit 5,
The position is specified based on a control signal or the like from the controller 7.

Hereinafter, a patterned wafer inspection method which is an embodiment of the present invention when the patterned wafer inspection apparatus having the above-mentioned configuration is used will be described.

In this method for inspecting a wafer with a pattern, a plurality of exposure apparatuses of the same type are arranged in parallel, and when different exposure apparatuses are used and the patterns of a plurality of photomasks are transferred onto the wafer and patterned. In addition, it is used when the patterns of these patterned wafers are respectively inspected by the patterned wafer inspection apparatus 1. For convenience, first reduction projection exposure apparatus (hereinafter referred to as first exposure apparatus) A, second reduction projection exposure apparatus (hereinafter referred to as second exposure apparatus) B, and third reduction projection exposure apparatus (as exposure apparatuses of the same type) Hereinafter, referred to as a third exposure apparatus.) As an example, a first photomask a, a second photomask b, a third photomask c, a third photomask c, a fourth photomask d, ... explain.

In this patterned wafer inspection method, the first exposure apparatus A, the second exposure apparatus B, and the third exposure apparatus C, the first reticle a, the second reticle b, and the correction value setting process described below are used. Third reticle c and fourth
A correction value is obtained in advance for each combination with the reticle d. First, as shown in FIG. 1, the first exposure apparatus A
And a first reticle a are combined to form a wafer with a first correction value setting pattern (hereinafter referred to as an A-a wafer).
11 is created. The A-a wafer 11 is created in a shot matrix by the design repeat pitch. Similarly, by combining the first exposure apparatus A and the second reticle b, a wafer with a second correction value setting pattern (hereinafter, referred to as A-
b wafer. ) 12 is created, and a wafer with a third correction value setting pattern (hereinafter referred to as an A-c wafer) 1 is obtained by the combination of the first exposure apparatus A and the third reticle c.
3 is created. The first reticle a, the second reticle b, and the third reticle c are used to manufacture the first product.

A combination of the second exposure device B and the fourth reticle d forms a wafer with a fourth correction value setting pattern (hereinafter referred to as Bd wafer) 14, and the second exposure device B and the fifth reticle. A wafer with a fifth correction value setting pattern (hereinafter referred to as a Be wafer) in combination with e.
Reference numeral 15 denotes a wafer with a sixth correction value setting pattern (hereinafter, referred to as B by a combination of the second exposure apparatus B and the sixth reticle f).
-F wafer. ) 16 are created respectively. The fourth reticle d, the fifth reticle e, and the sixth reticle f are used to manufacture the second product.

Further, the third exposure device C and the seventh reticle g
By the combination of the third exposure apparatus C and the eighth reticle h, and the seventh correction value setting patterned wafer (hereinafter, referred to as Cg wafer) 17 Hereinafter, a C-h wafer) 18 and a ninth correction value setting patterned wafer (hereinafter, referred to as C-i wafer) 19 are created by the combination of the third exposure apparatus C and the ninth reticle i. It The seventh reticle g, the eighth reticle h, and the ninth reticle h
Reticle i shall be used to manufacture the third product.

By the way, it is preferable that the wafer with the correction value setting pattern is prepared only for the correction value setting.
You may use together the manufacturing wafer actually input into this manufacturing process. When a manufacturing wafer is also used, it is desirable to apply it to the first manufacturing wafer when each reticle whose correction value is to be set is introduced into the manufacturing process. Further, these wafers with correction value setting patterns do not have to be continuously prepared, and may be prepared in a timely manner depending on the circumstances of the IC manufacturing process. Further, the method for producing the wafer with the correction value setting pattern is the same as the method for producing a normal manufacturing wafer, and includes a resist coating step, an exposing step, a developing step and the like.

The A-a wafer 11 to C-i wafer 19 produced as described above are measured by the patterned wafer inspecting apparatus 1 for an error from the design coordinates, and correction values are respectively determined based on the error. Desired. The calculated correction values are sequentially stored in the correction value memory 10 of the patterned wafer inspection apparatus 1. Hereinafter, the error measurement work and thereafter will be described by using the Aa wafer as a typical example.

First, the Aa wafer 11 is mechanically aligned with the stage 6 of the patterned wafer inspection apparatus 1 and set as shown in FIG.

Subsequently, the Aa wafer 11 on the stage 6
Are globally aligned. That is, the design coordinates previously specified based on the design data regarding the first reticle a are read by the controller 7, and the stage 6 is moved by the controller 7. With this movement,
As shown in FIG. 3B, the target pattern 21 located at the design coordinates on the Aa wafer 11 is arranged in the visual field 22 of the scanning electron microscope 2. This field of view 22
The center of the screen is the center of the electron beam irradiation position, which is the position of the design coordinate 23 designated by the controller 7. Therefore, the X-direction error ΔX and the Y-direction error ΔY are measured by moving the X length measurement cursor 24 and the Y length measurement cursor 25 located at the design coordinates 23 to the target pattern 21.

Then, as shown in FIG. 3A, when the X-direction error ΔX and the Y-direction error ΔY of the two target patterns 21, 21 on the Aa wafer 11 are measured, the stage Aa wafer 1 set to 6
One global alignment can be performed.

When global alignment for eliminating the error measured as described above is executed, FIG.
As shown in (a), the coordinate origin O ₁₁ of the Aa wafer ₁₁ is in a state of being aligned with the coordinate origin O ₆ of the stage 6. Incidentally, the global alignment can be executed by virtually moving the Aa wafer 11 and the stage 6 relative to each other by the correction value. In addition,
For convenience, in FIG. 3A, the rotation error and the expansion / contraction error are not shown.

After the global alignment is performed, a plurality of shots at positions separated from each other are designated in the shot matrix group formed on the Aa wafer, and a plurality of target patterns in each shot and a plurality of target patterns are assigned to each target pattern. The error from the corresponding design coordinates is measured respectively. Based on the measured error, the expansion / contraction error correction value, the rotation error correction value, and the offset error correction value for each designated shot are obtained. Here, the reason why a plurality of shots at positions distant from each other are specified is that an error in the movement of the exposure stage of the exposure apparatus appears in the error between the shots, and in order to correct this error, the Aa wafer This is because it is necessary to measure the error of the measurement points over the entire surface. Incidentally, the movement error of the exposure stage of the exposure apparatus tends to increase as the distance from the center of the exposure stage increases.

Next, the correction value setting process for each shot will be described with reference to FIG. As shown in FIG. 4A, shots for which correction values are to be set (hereinafter referred to as corrected value setting shots) 26 are designated at a plurality of locations separated from each other. Each correction value setting shot 26 is designated by A-a.
This is executed by designating the origin coordinates of each corrected value setting shot 26 on the wafer 11. When the origin coordinates of the corrected value setting shot 26 are designated, the stage 6 is moved to align the visual field (not shown) of the scanning electron microscope 2 with the designated origin of the corrected value setting shot 26. .

Subsequently, as shown in FIG. 4B, three ideal target patterns (hereinafter, referred to as ideal patterns) in the corrected value setting shot 26 at three positions apart from each other.
M ₁ , M ₂ , and M ₃ are sequentially designated by the design coordinates.
At this time, the second ideal pattern M ₂ and the third ideal pattern M ₃
Are located at two points orthogonal to each other with the first ideal pattern M ₁ as a base point. That is, when the design coordinates of the first ideal pattern M ₁ are (Xa, Yb), the design coordinates of the second ideal pattern M ₂ are (Xc, Yb), and the third ideal pattern M ₃
The design coordinates of are (Xa, Yd).

Design coordinates of the first ideal pattern M ₁ (Xa,
Yb) is designated, the stage 6 is moved, and as shown in FIG.
As shown in (b), the corrected value setting shot 2
A first ideal pattern M ₁ located at design coordinates (Xa, Yb) within 6 is arranged in the visual field 22 of the scanning electron microscope 2. The center of the screen of the field of view 22 is the center of the electron beam irradiation position, and is the position of the design coordinates (Xa, Yb) of the first ideal pattern M ₁ designated by the controller 7. Therefore,
The X measurement cursor 24 and the Y measurement cursor 25 located at the design coordinates (Xa, Yb) of the first ideal pattern M ₁ are set as the actual target pattern (hereinafter, referred to as the first actual pattern) N ₁ in the visual field 22. by moved, X direction error [Delta] x ₁ of the first actual pattern N ₁ and Y direction error [Delta] y ₁
Is measured. For example, a first actual pattern N ₁ coordinates (Xa ', Yb') Assuming that, X direction error [Delta] x ₁ of the first actual pattern N ₁ is (Xa'-Xa), Y direction error Δy ₁ is (Yb'-Yb). Similarly, X-direction of the second actual pattern N ₂ error [Delta] x ₂ and Y
The direction error Δy ₂ (not shown) and the X direction error Δx ₃ and the Y direction error Δy ₃ (not shown) of the third actual pattern N ₃ are sequentially measured.

The X-direction error Δx ₁ and the Y-direction error Δy _{1 of} the first actual pattern N ₁ measured as described above, the second
The X-direction error Δx ₂ and the Y-direction error Δy of the actual pattern N _2
2 , and based on the X-direction error Δx ₃ and the Y-direction error Δy ₃ of the third actual pattern N ₃ , the correction value of the expansion / contraction error, the correction value of the rotation error, and the offset error with respect to the design coordinates of this corrected value setting shot 26. The correction value of is calculated.
The expansion / contraction error correction value, the rotation error correction value, and the offset error correction value can be obtained by executing a statistical calculation process using each error. The calculated correction value is stored in the correction value memory 10.

Thereafter, each correction value is sequentially obtained for each of the correction value setting shots 26 ... Designated in the same manner, and sequentially stored in the correction value memory 10. By the above work, for example, the correction value list 27 as shown in FIG. 5 is virtually sequentially created. The correction value has the form of coefficients α, β, and γ. Then, this correction value list is updated every time an exposure apparatus and a reticle are added.

Next, a method of inspecting a patterned wafer for inspecting a patterned wafer used for manufacturing while making corrections using the correction values stored in the correction value memory will be described with reference to FIG.

As shown in FIG. 6, in a patterned wafer (hereinafter referred to as an inspected wafer) 40 patterned by an exposure device and a reticle, the identification code attached thereto is read by the wafer identification code reading device 31. The combination of the exposure device and the reticle used for patterning together with the read identification code is transmitted to the lot management computer 32 that controls the production of the wafer 40 to be inspected. The identification code and the combination of the exposure apparatus and the reticle sent to the lot management computer 32 are sent to the database 33 with a product type name and a process name, and recorded in the database 33. The database 33 is constructed so that the production history of the inspected wafer 40 is automatically managed by the identification code until the so-called pre-process is completed.

When the patterned wafer 40 to be inspected is sent to the patterned wafer inspection apparatus 1, the lot management computer 3 is installed in the patterned wafer inspection apparatus 1.
The type name and the process name are transmitted from 2 in correspondence with the identification code of the inspected wafer 40 to be inspected. Further, the recipe management computer 34 sends data necessary for inspecting the inspected wafer 40 to be inspected. The data necessary for the inspection includes, for example, an inspection sequence and coordinates designated in advance.
Further, the console 3 of the patterned wafer inspection apparatus 1
An operator code or the like is input by 5.

When the inspection of the wafer 40 to be inspected is performed, the patterned wafer inspection apparatus 1 reads out the correction values stored in advance from the correction value memory 10 as described above. The reading of the correction value is executed by designating the identification code of the wafer 40 to be inspected and the type name and process name from the lot management computer 32. For example, when the combination of the exposure apparatus and the reticle used for patterning the pattern to be inspected of the wafer to be inspected 40 is the first exposure apparatus A and the first reticle a, it is shown in FIG. The correction value data of the beginning area in the correction value list 27 that is present is read.

When the wafer 40 to be inspected is held on the stage 6 of the patterned wafer inspection apparatus 1, mechanical alignment and global alignment are carried out. Thereafter, a shot (hereinafter referred to as an inspected shot) 41 to be inspected based on the inspection data from the recipe management computer 34 is designated by the origin coordinates as shown in FIG. 7A. When the origin coordinates of the shot 41 to be inspected are designated, the stage 6 is moved to align the visual field of the scanning electron microscope 2 with the origin of the shot 41 to be inspected.

Next, based on the inspection data from the recipe management computer 34, as shown in FIG. 7B, the pattern 42 to be inspected (hereinafter referred to as the inspected pattern) 42 in the shot 41 to be inspected. Design coordinates are specified. Here, the patterned wafer inspection apparatus 1 executes the correction based on the correction value on the design coordinates.

For example, as shown in FIG. 7B, the actual coordinates of the pattern 42 to be inspected are (Xa ', Y
b ′), the design coordinates 43 of the pattern 42 to be inspected are (Xa,
Yb), X direction error Δx ₁ and Y direction error Δy ₁ are corrected (Xa + Δx ₁ ) in the X direction and (Yb + Δy ₂ ) in the Y direction. However, this description is an example for easy understanding, and the correction is actually executed by the calculation using the correction coefficient. The inspection of the inspection pattern 42 includes an X-direction length inspection and a Y-direction length inspection of the inspection pattern 42, and the inspection pattern 42 includes wiring and through holes.

After that, a plurality of shots at positions distant from each other in the shot matrix group formed on the wafer to be inspected 40 are designated as the shots to be inspected 41, and the inspection to the inspected pattern 42 in each of the shots to be inspected 41 is sequentially performed. Go running. When inspecting each pattern 42 to be inspected, the correction value for each shot is sequentially applied.
Since the correction value is applied to each shot, it is possible to realize the inspection with extremely high accuracy as compared with the case where a single correction value is applied to the inspection target wafer 40.

By the way, since the recent production of ICs tends to produce a large variety of products in small quantities, and mixed production is inevitable, wafers patterned by different exposure apparatuses and reticles are alternately arranged in the patterned wafer inspection apparatus 1. Are often sent to. For example, after the first reticle a inspects a group of lots patterned by the first exposure apparatus A, the fourth reticle d inspects another lot patterned by the second exposure apparatus b. In such a situation,
When performing, for example, dimension inspection by the patterned wafer inspection apparatus 1, the first exposure apparatus A and the first reticle a
When the inspection is performed only by the correction value corresponding to the combination of the exposure apparatus A and the exposure apparatus B, the stage movement error between the first exposure apparatus A and the second exposure apparatus B is different.
In addition, the inspection result may differ between the reticles a and d.

However, in this embodiment, since the correction value is set for each combination of the exposure apparatus and the reticle and the inspection is performed by the patterned wafer inspection apparatus, the inspection result between the exposure apparatus and the reticle is not changed. Differences can be prevented. Therefore, it is possible to maintain high accuracy in the inspection of patterned wafers even under mixed flow production in high-mix low-volume production, and prevent reduction in IC manufacturing yield and the like. In addition, the productivity of the IC can be improved by realizing the mixed flow production in combination with preventing the production yield from decreasing.

According to the above embodiment, the following effects can be obtained. (1) An exposure apparatus is set by setting a correction value for each combination of an exposure apparatus and a reticle, and correcting the control of the stage for each combination of the exposure apparatus and the reticle when performing inspection by the patterned wafer inspection apparatus. Also, because it is possible to prevent differences in inspection results between reticles, high accuracy in patterned wafer inspection is maintained even when multiple reticles are properly mounted and used in multiple exposure apparatuses. It is possible to prevent a decrease in IC manufacturing yield and the like.
Productivity can be increased.

(2) Even under a situation where a plurality of reticles are properly mounted on a plurality of exposure apparatuses and used, by maintaining a high precision in the patterned wafer inspection, mixed production in a large number of kinds of small quantity production can be achieved. Since it can be realized, it is possible to improve the productivity of the IC in combination with preventing the production yield from decreasing.

(3) When setting the correction value, a plurality of shots at positions distant from each other in the shot matrix group are designated as shots for which the correction value is to be set in the correction value setting wafer, thereby setting the correction value. Since the correction value can be set for each local area on the entire surface of the wafer, the accuracy of the patterned wafer inspection can be further improved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say.

For example, the number of exposure apparatuses of the same type is not limited to three, and the number of reticles used is not limited to three. The exposure apparatus is not limited to the reduction projection exposure apparatus, and the photomask is not limited to the reticle which is the enlarged photomask.

The patterned wafer inspection apparatus is not limited to the scanning electron microscope, but may be an optical type or an X-ray type. In particular, when applied to a patterned wafer inspection apparatus that inspects ultrafine patterns, excellent effects are exhibited.

[0049]

The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.

A correction value is set for each combination of the exposure apparatus and the photomask, and the stage control is corrected for each combination of the exposure apparatus and the photomask when the inspection is performed by the patterned wafer inspection apparatus. Since it is possible to prevent differences in inspection results between photomasks and photomasks, high accuracy is maintained for patterned wafer inspection even when multiple photomasks are properly mounted and used in multiple exposure apparatuses. Therefore, it is possible to prevent a decrease in the manufacturing yield of the semiconductor device, and it is possible to improve the productivity.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a patterned wafer inspection method according to an embodiment of the present invention.

FIG. 2 is a schematic diagram showing a patterned wafer inspection apparatus according to an embodiment of the present invention.

FIG. 3 shows a global alignment process,
(A) is a schematic whole screen view, (b) is an enlarged partial screen view.

4A and 4B show a correction value setting step, wherein FIG. 4A is a schematic overall screen view, and FIG. 4B is a schematic enlarged partial screen view.

FIG. 5 is a schematic diagram showing a correction value list.

FIG. 6 is a block diagram showing an actual patterned wafer inspection method.

7A and 7B show an actual patterned wafer inspection method, wherein FIG. 7A is a schematic overall plan view, and FIG. 7B is a schematic enlarged partial screen view.

[Description of Symbols] 1 ... Patterned wafer inspection device, 2 ... Scanning electron microscope, 3 ... Electron beam generation / molding unit, 4 ... Deflection unit, 5 ... Irradiation position control unit, 6 ... Stage, 7 ... Controller, 8 ... Signal detection unit, 9 ... Position specifying unit, 10 ... Correction value memory, A ... First reduced projection exposure apparatus (first exposure apparatus), B ... Second reduced projection exposure apparatus (second exposure apparatus), C ... Third Reduction projection exposure apparatus (third exposure apparatus), a ... First reticle (photomask), b ... Second reticle (photomask), c ... Third reticle (photomask), 11 ... Wafer with first correction value setting pattern ( Aa wafer), 12 ... Second correction value setting patterned wafer (Ab wafer), 13 ... Third correction value setting patterned wafer (Ac wafer), 14 ...
Fourth correction value setting patterned wafer (Bd wafer), 15 ... Fifth correction value setting patterned wafer (B
-E wafer), 16 ... Wafer with sixth correction value setting pattern (Bf wafer), 17 ... Wafer with seventh correction value setting pattern (Cg wafer), 18 ... Seventh correction value setting pattern Wafer (C-h wafer), 19 ... Wafer with seventh correction value setting pattern (C-i wafer), 21
... target pattern, 22 ... scanning electron microscope field of view, 23
... designed coordinates, 24 ... X measurement cursors, 25 ... Y measurement cursors, O ₁₁ ... coordinate origin of A-a wafer, the coordinate origin of the O ₆ ... stage, 26 ... the correction value setting shots, M _1,
M ₂ , M ₃ ... Ideal target pattern (ideal pattern),
(Xa, Yb) ... Design coordinates of the first ideal pattern M ₁ , N
₁ ... Actual target pattern (first actual pattern), Δx ₁
... X-direction error of first actual pattern N ₁ , Δy ₁ ... Y-direction error, N ₂ ... second actual pattern, Δx ₂ ... X-direction error of second actual pattern, Δy ₂ ... Y-direction error of second actual pattern , N ₃ ... third fact pattern, [Delta] x ₃ ... third actual X direction error pattern N _3, [Delta] y ₃ ... third actual pattern N ₃
Y-direction error, 27 ... Correction value list, 31 ... Wafer identification code reader, 32 ... Lot management computer, 33
... database, 34 ... recipe management computer, 35
... Console, 40 ... Inspected wafer, 41 ... Inspected shot, 42 ... Inspected pattern, 43 ... Design coordinates.

Claims (3)

[Claims] 1. When inspecting an actual patterned wafer patterned by the exposure apparatus and the photomask, each correction value based on the error with respect to the design coordinates is obtained in advance for each combination of each exposure apparatus and each photomask. A method for inspecting a patterned wafer, wherein design coordinates are corrected by a correction value corresponding to a combination of an exposure apparatus and a photomask used for patterning an actual patterned wafer to be inspected. 2. A wafer with each correction value setting pattern is created for each combination of each exposure apparatus and each photomask, and an error with respect to design coordinates is measured for each wafer with each correction value setting pattern, and The correction value for each combination of each exposure apparatus and each photomask is obtained in advance based on the measured error.
The patterned wafer inspection method described in 1. 3. A patterned wafer inspection apparatus for inspecting a patterned wafer patterned by an exposure apparatus and a photomask, each of which is previously determined based on an error with respect to design coordinates for each combination of each exposure apparatus and each photomask. A correction value memory for storing correction values, an exposure apparatus and a photomask used for patterning an actual patterned wafer to be inspected when inspecting an actual patterned wafer patterned by the exposure apparatus and the photomask. And a controller that reads the correction value corresponding to the combination from the correction value memory and corrects the design coordinates based on the read correction value.