JPH09245076A - Wiring board designing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board designing device for highly accurately performing the respective kinds of the simulation of a waveform, heat, a timing and electromagnetic radiation, etc., in the design of a printed wiring board and a multi-chip module substrate. SOLUTION: This device is provided with plural simulators 10-13 for executing the simulation for supporting design relating to the arrangement of electronic components and wiring, a preparation data for analysis storage means 3 for storing the power consumption parameter or electrical characteristic information parameter of the electronic component required by the plural simulators 10-13 and a data-for-analysis processing means 9 for changing the parameter stored in the preparation data for analysis storage means 3 based on the simulated result of one of the plural simulators 10-13. Then, the plural simulators 10-13 respectively input the parameter changed by the data for analysis processing means 9 and execute the simulation again.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board and a multi-chip module (hereinafter referred to as MCM).
In board design, various simulations such as waveform, heat, timing, electromagnetic radiation (hereinafter referred to as EMC) are linked, real-time execution function, and time-dependent time-dependent change simulation function The present invention relates to a wiring board design device having

[0002]

2. Description of the Related Art The structure of a conventional printed wiring board designing apparatus is shown in FIG. In FIG. 21, 1 is input means for inputting data for layout and wiring design using a mouse or keyboard, 3 is design preparation data storage means for storing information such as shape of electronic parts in advance, and 4 is input. A layout and wiring design means for performing actual layout and wiring on the printed board based on the information input by the means 1 and the information stored in the design preparation data storage means 3 is a design for storing the designed layout and wiring information. Data storage means, 6 is analysis data extraction means for extracting information necessary for simulation from the layout and wiring design information, 33 is analysis data storage means for storing data necessary for simulation by a simulator, which will be described later, and 10 is a waveform. A simulator, 11 is a timing simulator, 12 is a thermal simulator, 13 is an EMC simulator, and 14 is a waveform stain. Waveform simulation result storage means for storing a simulation result of the regulator 10, and the same in 15 timing simulation result storage means, 16 thermal simulation result storage means 17 is EMC simulation result storage means. Reference numeral 18 denotes a simulation result display means for displaying each simulation result.

Next, the operation of the conventional printed wiring board designing apparatus and each simulator will be described. The placement and wiring design means 4 uses the input means 1 to perform actual placement and routing, outputs the result to the design data storage means 5, inputs the result, and outputs the analysis data necessary for the simulation performed later to the analysis data extraction means. 6 is used for extraction and stored in the analysis data storage means 33. The simulators 10 to 13 are operated using this analysis data, the simulation results are stored in the simulation result storage means 14 to 17 of the respective simulators 10 to 13, and the simulation result display means 18 displays them on the screen.

Inputs to the waveform simulator 10 include how to connect the wiring, the shape of the wiring, the electrical characteristics of the wiring, and the characteristics of the parts used. This waveform simulator 10
Solves the electromagnetic field equations for each circuit to simulate what kind of waveform is output to the output buffer when there is an appropriate input in the input buffer of each circuit. The simulation result is stored in the waveform simulation result storage means 14 and is displayed on the screen by using the simulation result display means 18.

The input of the timing simulator 11 is how to connect the wiring, the delay time per unit length of the wiring, and the like. The timing simulator 11 simulates the electrical timing between each component using delay time and the like. The simulation result is stored in the timing simulation result storage means 15, and is displayed on the screen by using the simulation result display means 18.

The input of the thermal simulator 12 is the component arrangement and power consumption of each component. This heat simulator 12
Simulates the temperature of each component by performing calculations for heat and convection for air. The simulation result is stored in the thermal simulation result storage means 16 and is displayed on the screen by using the simulation result display means 18.

The inputs of the EMC simulator 13 include how to connect the wiring, the shape of the wiring, the electrical characteristics of the wiring, and the characteristics of the parts used. This EMC simulator 13 solves the electromagnetic field equations for the circuit and the space or the surrounding space, so that when there is an appropriate input in the input buffer of each circuit, what electromagnetic radiation is emitted in the surrounding space. To simulate. The simulation result is stored in the EMC simulation result storage means 17, and is displayed on the screen using the simulation result display means 18.

[0008]

In the conventional wiring board design apparatus, since various simulators are independently used as described above, when designing the printed wiring board and the MCM board, the waveform, timing, heat, A simulation that could affect the mutual influence of each simulator of EMC could not be performed. Moreover, the simulation could not be executed in synchronization with the change of the placement and routing information. Furthermore, since various simulations were carried out assuming that electronic components and ambient environment parameters were in a steady state, malfunctions could not be detected in the process of reaching a steady state. Further, since the analysis data transferred from the layout and wiring design means to the simulator is huge, it takes a lot of time to process the data in each functional block that handles the data. Furthermore, the result analyzed by the simulator only displays the state, and the designer was left with the means for detecting the location where the error occurred and for avoiding the problem. Therefore, the designer's ability to avoid problems causes variations in the design quality of the wiring board.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a wiring board designing device which realizes the following contents. (1) Highly accurate simulation is possible by cooperative control that changes the execution parameters of the simulation based on the correlation of various simulators. (2) By observing the placement and routing information, it is possible to perform a simulation in synchronization with changes in the placement and routing information. (3) A malfunction can be detected in the process of reaching a steady state. (4) It is possible to shorten the data processing time in each functional block that handles the data by taking out a part of the analysis data transferred from the layout and wiring design means to the simulator. (5) The design quality of the wiring board can be made uniform by analyzing the result analyzed by the simulator and presenting the place where the error has occurred and the problem avoidance means.

[0010]

The wiring board designing apparatus of the first invention requires a plurality of simulators for executing a simulation for supporting a design relating to the layout and wiring of electronic components, and the plurality of simulators. Based on the analysis preparation data storage means for storing the power consumption parameter or the electrical characteristic information parameter of the electronic component and the simulation result of one of the plurality of simulators, the analysis preparation data storage means stores the data. An analysis data processing means for changing the above parameters is provided,
Each of the plurality of simulators inputs the parameters changed by the analysis data processing means and re-executes the simulation.

The wiring board design apparatus of the second invention is a waveform simulator for analyzing the transmission waveform of a signal, a timing simulator for verifying the correctness of a signal change point, a thermal simulator for analyzing the heat distribution of a wiring board, or a wiring board. It is equipped with a simulator which is an EMC simulator for analyzing the electromagnetic radiation noise.

The wiring board designing apparatus of the third invention is provided with a time control means for repeatedly causing the plurality of simulators to execute the simulation until the electronic components are stably operated.

In the wiring board designing apparatus of the fourth aspect of the invention, the analysis result history storage means for storing the simulation results of the plurality of simulators together with the simulation time, and the simulation result history storage means for storing the simulation results at a designated time are used. It is provided with an analysis result history display means for extracting and displaying.

A wiring board designing apparatus according to a fifth aspect of the present invention includes a plurality of simulators for inputting analysis data for a simulation and executing a simulation for supporting a design relating to the layout and wiring of the electronic components. Arrangement and wiring design means for designing arrangement and wiring of parts, operation monitoring means for monitoring whether the electronic parts are moved, rotated, or changed in wiring information by the arrangement and wiring design means, and this operation monitoring means And a real-time control means for causing the plurality of simulators to execute the simulation when the change is detected.

In the wiring board designing apparatus of the sixth aspect of the invention, when the operation monitoring means detects the change, the analysis differential data extracting means for extracting the analysis data of only the changed portion, and the before-change portion are used. Pre-analysis data storage means for storing analysis data, the analysis data extracted by the analysis difference data extraction means and the analysis data before the change stored in the pre-analysis data storage means And an analyzing data synthesizing means for synthesizing.

A wiring board designing apparatus according to a seventh aspect of the present invention comprises critical path storage means for storing a critical path such as a bus or a high speed signal, and the operation monitoring means stores the critical path stored in the critical path storage means. Is monitored, and the analysis difference data extraction means extracts the analysis data of only the changed part of the critical path when the critical path is changed.

The wiring board design apparatus of the eighth invention stores an error criterion for determining whether or not there is an error in the simulation results of the plurality of simulators, and based on this error criterion, the error criterion in the simulation results is stored. It is provided with an error analysis means for specifying an error.

The wiring board designing apparatus of the ninth invention comprises error analysis result reporting means for displaying the error specified by the error analyzing means.

The wiring board designing apparatus of the tenth aspect of the invention comprises an error analysis result image display means for displaying an image of the location where the error identified by the error analysis means has occurred.

The wiring board designing apparatus of the eleventh invention comprises a navigation processing means for displaying a method for avoiding the error specified by the error analyzing means.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1. Embodiment 1 of the present invention will be described below with reference to the drawings. The first embodiment is characterized in that the correlation of the results of various simulators such as waveform, heat, timing, and EMC is discriminated, and the parameter at the time of executing the simulation is changed to execute the simulation with higher accuracy. It is a thing. FIG. 1 is a configuration diagram of a wiring board design device according to the first embodiment. In the figure, 1 is an input means for inputting information for layout and wiring design using a keyboard and a mouse, and an execution mode (cooperative control mode, real-time control mode, aging control mode),
Reference numeral 3 is a design preparation data storage means for holding information such as a shape of a design electronic component necessary for designing a wiring board, connection information between the electronic components, and a board layer configuration, and 4 is an input means 1 and a design preparation data storage means 3 Placement / wiring design means for designing a wiring board such as arrangement of parts and wiring between parts using the information of 5 is a design data storage means for storing wiring board information designed by the placement / wiring design means 4, 6 Is an analysis data extraction means for extracting data for various simulators such as waveform, timing, heat, and EMC from the wiring board information of the design data storage means 5.

Reference numeral 8 is an analysis preparation data storage means for holding parameters necessary for various simulations such as electric power consumption and electric characteristic information of electronic parts, and 9 is a simulator for any of waveform, timing, heat, EMC and the like. It is an analysis data processing unit that changes the parameters stored in the analysis preparation data storage unit 8 based on the simulation result.

Reference numeral 10 is a waveform simulator for analyzing the transmission waveform of a signal using the information from the analyzing data processing means 9,
Reference numeral 11 is a timing simulator that uses information from the analysis data processing means 9 to verify the correctness at the change point of the signal, and 12 is a thermal simulator that uses information from the analysis data processing means 9 to analyze the heat distribution of the wiring board. , 13 are EMC simulators for analyzing the electromagnetic radiation noise of the wiring board using the information from the analysis data processing means 9.

Reference numeral 14 is a waveform simulation result storage means for storing the result of the waveform simulator 10, 15 is a timing simulation result storage means for storing the result of the timing simulator 11, and 16 is a thermal simulator 12.
Thermal simulation result storage means for storing the result of 1
Reference numeral 7 denotes an EMC simulation result storage means for storing the result of the EMC simulator 13. Reference numeral 18 is a simulation result display means for displaying the results of various simulations accumulated in the waveform simulation result storage means 14, the timing simulation result storage means 15, the thermal simulation result storage means 16 and the EMC simulation result storage means 17.

Reference numeral 19 is an analysis mode discriminating means for discriminating the execution mode of the simulation input by the input means 1, and 20 is stored in the various simulation result storing means 14 to 17 when the analysis mode discriminating means 19 judges that the simulation is a cooperative simulation. It is an analysis cooperation control means for judging each correlation from the obtained data and transmitting the information to the analysis data processing means 9.

Next, the correlation of the results of various simulators is judged, and the parameters for executing various simulations are changed (hereinafter referred to as cooperative simulation).
The procedure in this case will be described below with reference to FIGS. 1 and 2.
2A and 2B are views showing images of various simulation results displayed on the simulation result display means 18. FIG. 2A is a thermal simulation result, FIG. 2B is a waveform simulation result, and FIG. The EMC simulation result, the same figure (d) shows the timing simulation result.

The analysis mode discriminating means 19 transmits the instruction for executing the cooperative simulation to the analysis cooperation controlling means 20 based on the information from the input means 1. Analysis cooperation control means 2
At 0, the data for analysis obtained by inputting the layout and wiring information stored in the design data storage means 5 to the analysis data extraction means 6 and the thermal analysis stored in the analysis preparation data storage means 8 are used. The preparation data is input to the analysis data processing means 9, and the data is output to the thermal simulator 12. The thermal simulator 12 executes thermal simulation on the above-mentioned analysis data, and stores the result in the thermal simulation result storage means 16. The data accumulated in the thermal simulation result storage means 16 is displayed on the simulation result display means 18 as the thermal simulation result of FIG.

The analysis data processing means 9 is based on the thermal simulation result accumulated in the thermal simulation result storage means 16 and has a waveform depending on heat in the analysis preparation data stored in the analysis preparation data storage means 8. The parameters for simulation and EMC simulation are changed depending on the temperature, and the layout and wiring information stored in the design data storage means 5 is input to the analysis data extraction means 6 together with the analysis data obtained, and the waveform simulator 10 and The data is output to the EMC simulator 13.

The waveform simulator 10 and the EMC simulator 13 execute the waveform simulation and the EMC simulation on the above-mentioned analysis data, and accumulate the results in the waveform simulation result storage means 14 and the EMC simulation result storage means 17. The data accumulated in the waveform simulation result storage means 14 and the EMC simulation result storage means 17 are displayed on the simulation result display means 18 as the waveform simulation result of FIG. 2B and the EMC simulation result of FIG. 2C.

In the same procedure, the analysis data processing means 9 uses the thermal simulation result stored in the thermal simulation result storage means 14 as a basis to analyze the heat in the analysis preparation data stored in the analysis preparation data storage means 8. The parameter for the timing simulation that depends on is changed depending on the temperature. Then, in the wiring that connects between the analysis data obtained by inputting the layout and wiring information stored in the design data storage means 5 into the analysis data extraction means 6 and the electronic parts stored in the waveform simulation result storage means 14. The delay time is output to the timing simulator 11. The timing simulator 11 executes a timing simulation on the above-mentioned analysis data, and stores the result in the timing simulation result storage means 15. The data accumulated in the timing simulation result storage means 15 is the simulation result display means 1
8 is displayed as the timing simulation result of FIG.

As described above, according to this embodiment, by changing the parameters in the analysis preparation data of another simulation based on the thermal simulation result,
Highly accurate simulation is possible. In addition, in this embodiment, the case where another simulation is performed after performing the thermal simulation is shown. However, instead of the thermal simulation, another simulation is performed first, and the next simulation is performed based on the simulation result. The parameters may be changed.

Embodiment 2 FIG. In the second embodiment, whether or not the placement / wiring information is changed is monitored, and each time it is changed, a simulation of the situation after the change is performed and the result is displayed to optimize the placement / wiring data while observing the simulation result. It is characterized by Hereinafter, the second embodiment will be described with reference to the drawings. Embodiment 1
The description of the same function is omitted because it has the same function.

FIG. 3 is a block diagram of a wiring board designing apparatus according to the second embodiment. In the figure, reference numeral 2 is an operation monitoring means for monitoring the operation status such as movement and rotation of electronic parts in the layout and wiring design means 4 and wiring information change, 21 is a notification of the layout and wiring information change by the operation monitoring means 2, and When the analysis mode determination means 19 determines the real-time mode, the design data stored in the design data storage means 5 is replaced with the latest design data, and the analysis data extraction means 6 is used for various simulations from the design data storage means 5. Is a real-time control means for causing the analysis data processing means 9 to execute the processing of the analysis data.

FIG. 4 is a diagram showing the layout and wiring design data displayed by the layout and wiring design means 4, and the part A is an electronic component in the layout and wiring design data. FIG. 5 is a diagram in which an execution result of a simulation using the placement and routing data of FIG. 4 is displayed as an image. FIG. 5A shows a thermal simulation result using the placement and routing data, and FIG. 5B shows the placement. The waveform simulation result using the wiring data, the figure (c) is the EMC simulation result using the placement and routing data, and the figure (d) is the timing simulation result using the placement and routing data.

FIG. 6 is a view showing the layout and wiring design data after the layout of the electronic component A is changed by the layout and wiring design means 4. FIG. 7 is a diagram showing an image of the execution result of the simulation using the placement and routing data of FIG. 6, FIG. 7A is a thermal simulation result using the changed placement and routing data, and FIG. A waveform simulation result using the changed placement and routing data, FIG. 6C shows an EMC simulation result using the changed placement and routing data,
FIG. 11D shows the timing simulation result using the changed placement and routing data.

Next, the procedure for changing the results of various simulators (hereinafter referred to as real-time simulation) in accordance with the movement and rotation of electronic parts and the change of wiring information will be described.

From the information of the input means 1, the analysis mode discrimination means 19 transmits an instruction to execute the real-time simulation to the real-time control means 21. The electronic component A in the component placement and routing data of FIG.
If you move, the component placement and routing data will be as shown in Fig.
The operation monitoring unit 2 detects a change in the placement / wiring information in the placement / wiring designing unit 4. The operation monitoring means 2 notifies the real-time control means 21 through the analysis mode determination means 19 that the component placement / wiring data has changed, and the placement / wiring designing means 4 continuously sends the component placement / wiring data to the design data storage means 5. Output.

The processing thereafter is performed by the analysis mode discrimination means 1
This is the same as the first embodiment in which it is determined in 9 that the cooperative simulation mode is set.

As described above, according to this embodiment, the operation of monitoring the change of the placement / wiring information is monitored, and the heat, the waveform, the E are changed from the time when the change of the placement / wiring information occurs depending on the contents of the change.
Perform MC and timing simulation continuously. In synchronism with this, the thermal simulation result is shown in FIG.
(A), waveform simulation result FIG. 5 (b), EMC
Simulation result FIG. 5 (c) and timing simulation result FIG. 5 (d) show thermal simulation result FIG. 7 (a) and waveform simulation result FIG. 7 respectively.
(B), EMC simulation result FIG. 7C, and timing simulation result FIG. 7D continuously change, so that it is possible to optimize the placement and routing data while observing the simulation result.

Embodiment 3 In the third embodiment, a simulation is executed along a time axis until the electronic components and ambient environment parameters reach a steady state, and a waveform,
It is characterized in that malfunctions in the process of reaching a steady state are detected by displaying changes in heat, timing, EMC and the like. Hereinafter, the third embodiment will be described with reference to the drawings. Since the same parts as those in the first embodiment have the same functions, the description thereof will be omitted.

FIG. 8 is a block diagram of a wiring board designing apparatus according to the third embodiment. In the figure, reference numeral 22 is a time control means for causing the analysis data processing means 9 to execute data processing for time change when the analysis mode determination means 19 determines the time simulation mode, and 32 is the waveform analysis simulation result storage means 14. And an analysis of accumulating various simulation results accumulated in the timing simulation result storage means 15, the thermal simulation result storage means 16 and the EMC simulation result storage means 17 together with the time span (time step width used for simulation) input from the input means 1. It is a result history storage means.

Next, simulation is performed along the time axis along the process until the electronic components and ambient environment parameters reach a steady state (the electronic components operate stably and the parameters hardly change along the time axis). A procedure for executing the operation and detecting a malfunction in the process of reaching the steady state by displaying changes in the waveform, heat, timing, EMC, etc. (hereinafter, referred to as time-dependent simulation) will be described.

The analysis mode discriminating means 19 transmits an instruction for executing the temporal simulation to the temporal control means 22 based on the information from the information of the input means 1. The analysis data processing unit 9 receives the analysis data from the analysis data extraction unit 6 and the analysis preparation data accumulated in the analysis preparation data storage unit 8 under the control of the time-lapse control unit 22, and then the thermal simulator. The data is output to 12. The thermal simulator 12 executes thermal simulation on the above-mentioned analysis data, and stores the result in the thermal simulation result storage means 16. The data accumulated in the thermal simulation result storage means 16 is displayed on the simulation result display means 18 as the thermal simulation result of FIG.

The analysis data processing means 9 is based on the thermal simulation result accumulated in the thermal simulation result storage means 16 and has a waveform depending on heat in the analysis preparation data stored in the analysis preparation data storage means 8. Parameters for simulation and EMC simulation are changed, and the layout and wiring information stored in the design data storage means 5 is input to the analysis data extraction means 6 together with the data for analysis obtained in the waveform simulator 10 and the EMC simulator 13. Is output.

The waveform simulator 10 and the EMC simulator 13 execute the waveform simulation and the EMC simulation on the above-mentioned analysis data, and store the results in the waveform simulation result storage means 14 and the EMC simulation result storage means 17. The data accumulated in the waveform simulation result storage means 14 and the EMC simulation result storage means 17 are displayed on the simulation result display means 18 as the waveform simulation result of FIG. 2B and the EMC simulation result of FIG. 2C.

In the same procedure, the analysis data processing means 9 uses the heat simulation results accumulated in the heat simulation result storage means 14 to generate heat in the analysis preparation data stored in the analysis preparation data storage means 8. The parameter for the timing simulation that depends on is changed.
Then, in the wiring that connects between the analysis data obtained by inputting the layout and wiring information stored in the design data storage means 5 into the analysis data extraction means 6 and the electronic parts stored in the waveform simulation result storage means 14. The delay time is output to the timing simulator 11. The timing simulator 11 executes a timing simulation on the above-mentioned analysis data, and stores the result in the timing simulation result storage means 15. The data accumulated in the timing simulation result storage means 15 is displayed on the simulation result display means 18 as the timing simulation result of FIG.

In the same procedure, the analysis data processing means 9 uses the timing simulation result stored in the timing simulation result storage means 15 to generate the timing in the analysis preparation data stored in the analysis preparation data storage means 8. The parameters for the thermal simulation depending on are changed. Then, the layout and wiring information stored in the design data storage means 5 is input to the analysis data extraction means 6 and is output to the thermal simulator 12 together with the analysis data obtained. In the thermal simulator 12, the thermal simulation is executed again with the above-mentioned analysis data, and the result is stored in the thermal simulation result storage means 12. The data accumulated in the thermal simulation result storage means 16 is displayed on the simulation result display means 18 as the timing simulation result of FIG.

The above operation is repeated until a steady state is reached. The determination of the steady state is made by the analysis data processing means 9 based on the N-th timing simulation result stored in the timing simulation result storage means 15,
The (N-1) th timing simulation results stored in the analysis result history storage means 32 are compared, and as a result, when the difference between the respective data is sufficiently small, the time control simulation is performed by the time control means 22. finish. Further, when the set simulation time ends, the time-dependent control simulation ends in synchronization with it.

As described above, according to this embodiment, a simulation is executed along the time axis until the electronic components and the ambient environment parameters reach the steady state, and the waveform,
By displaying changes in heat, timing, EMC, etc. (examples of changes are shown in FIGS. 9, 10, and 11), malfunctions in the process of reaching a steady state can be detected.

Embodiment 4 In the fourth embodiment, the result of executing the time-dependent simulation described in the third embodiment is stored together with its time axis, and after the analysis is completed, the data at a specific time is extracted from the stored simulation result and displayed, so that a steady state is obtained. The feature is that a malfunction in the process leading to is detected in detail. Hereinafter, the fourth embodiment will be described with reference to the drawings. Since the same parts as those in the third embodiment have the same functions, the description thereof will be omitted.

FIG. 12 is a block diagram of a wiring board designing apparatus according to the fourth embodiment. In the figure, reference numeral 26 is an analysis result history display means for displaying a history of analysis results accumulated in the analysis result history storage means 32 based on the time designation information inputted by the input means 1.

Next, a procedure for reviewing the result of the temporal simulation as shown in the third embodiment after the simulation (hereinafter, referred to as playback display) will be described.

The time designation information is input to the analysis result history display means 26 by the input means 1. Analysis result history display means 2
6 extracts the analysis result at the designated time in the analysis result history storage means 32 and displays it on the screen. The subsequent processing is the same as in the third embodiment.

As described above, according to this embodiment, from the history of the results of the simulation of the process until the electronic components and the ambient environment parameters reach the steady state along the time axis, at a specific time after the end of the analysis. By extracting and displaying the data, it is possible to detect in detail the malfunction in the process of reaching the steady state.

Embodiment 5. The fifth embodiment reduces the data amount of the analysis data by synthesizing the analysis data passed from the layout and wiring design means to the simulator from the design data difference and the pre-analysis data. It is characterized by. Hereinafter, Embodiment 5
Will be described with reference to FIG. Since the same parts as those in the second embodiment have the same functions, the description thereof will be omitted.

FIG. 13 is a block diagram of a wiring board designing apparatus according to the fifth embodiment. In the figure, when the operation monitoring means 2 detects that the layout and wiring information of the layout and wiring designing means 4 is changed, the reference numeral 23 extracts only the changed portion information from the layout and wiring information stored in the design data storing means 5. The analysis differential data extracting means, 24 is the pre-analysis data storage means for storing the previously executed analysis data, and 7 is the changed portion data extracted by the analysis difference data extracting means 23 and the pre-analysis data storage means 24. The analyzing data synthesizing means synthesizes the analyzing data stored in the.

Next, in the real-time simulation as shown in the second embodiment, the data of only the changed portion (hereinafter,
A procedure for utilizing difference data) (hereinafter referred to as difference data utilization real-time simulation) will be described.

When the placement / wiring design means 4 changes the placement / wiring information, the operation monitoring means 2 detects the change information and inputs the change information to the analysis difference data extracting means 23. The analysis difference data extraction unit 23 extracts only the data of the changed portion of the layout and wiring information stored in the design data storage unit 5. In the analysis data synthesizing means 7, analysis of the changed portion newly extracted by the analysis difference data extracting means 23 based on the analysis data in the pre-analysis data storage means 24 for storing the previously executed analysis data. Data for analysis is synthesized to create data for analysis. The subsequent processing is the same as in the second embodiment.

As described above, according to this embodiment, since only the changed data is extracted when the design data is changed, compared with the case where all the analysis data is extracted,
It is possible to reduce the amount of analysis data and the extraction time.

Embodiment 6 FIG. According to the sixth embodiment, in executing various simulations accompanying the change of the layout and wiring design information, only the change information regarding the critical path set in advance in the critical path storage means is handled and only the necessary analysis data is created. The feature is that the amount of analysis data is reduced. Embodiment 6 will be described below with reference to the drawings. Since the same parts as those in the fifth embodiment have the same functions, the description thereof will be omitted.

FIG. 14 is a block diagram of a wiring board designing apparatus according to the sixth embodiment. In the figure, reference numeral 25 is a critical path storage means for storing a critical path such as a bus or a high speed signal input by the input means 1.

Next, a procedure will be described in the case where the differential data utilizing real-time simulation as shown in the fifth embodiment is performed only for the critical path (hereinafter, critical path extraction real-time simulation).

The input unit 1 points out a critical path such as a bus or a high-speed signal in the connection information between electronic components stored in the design preparation data storage unit 3, and stores the critical path in the critical path storage unit 25. . The analysis difference data extracting means 23 receives the change notification of the placement / wiring information from the operation monitoring means 2 and the critical path information from the critical path storage means 25, and selects the critical path of the placement / wiring information stored in the design data storage means 5. Extract the data for analysis of the changed part only. The subsequent processing is the same as in the fifth embodiment.

As described above, according to this embodiment, since only the change data of the critical path in the design data is extracted, the data amount of the analysis data is smaller than that in the case of extracting all the analysis data. It is possible to reduce and shorten the extraction time.

Embodiment 7 FIG. In the seventh embodiment, by analyzing the result analyzed by the simulator, an error that adversely affects the function realized by the wiring board is identified, and the location where the error occurs is reported, thereby making a design error in the layout and wiring information. It is also characterized by preventing mistakes in change. Hereinafter, Embodiment 7 will be described with reference to the drawings.
Since the same parts as those in the first embodiment have the same functions, the description thereof will be omitted.

FIG. 15 is a block diagram of a wiring board designing apparatus according to the seventh embodiment. In the figure, 27 is a waveform simulation result storage means 14, a timing simulation result storage means 15, and a thermal simulation result storage means 16.
And error analysis means for analyzing the presence or absence of an error on the basis of an error criterion set for each simulation based on each simulation result stored in the EMC simulation result storage means 17, and 28 reports information determined as an error by the error analysis means 27 Is an error analysis result report means for outputting as.

FIG. 16 is a diagram showing guidelines for detecting an error and the contents of the error with respect to the waveform simulation result. In FIG. 16A, 40 is an overshoot reference value, 42 is an undershoot reference value, and 41 is an undershoot reference value. It is the waveform of the result of the waveform simulation.

Next, the procedure for detecting an error will be described. An error criterion for discriminating an error from the result of each simulation is input to the error analysis means 27 in advance. Then, the simulation as shown in the first to sixth embodiments is executed. The error analysis unit 27 includes the waveform simulation result storage unit 14, the timing simulation result storage unit 15, the thermal simulation result storage unit 16, and the EMC simulation result storage unit 1.
The execution result of each simulation input from 7 is analyzed. As the analysis result, the error analysis result reporting means 28 outputs a report of error information.

For example, in FIG. 16A, the waveform 41 as a result of the waveform simulation exceeds the overshoot reference value 40 and the undershoot reference value 42. For this reason, the error analysis means 27 determines the overshoot error and the undershoot error, and the error analysis result reporting means 28 uses FIG.
An error analysis report as shown in (b) is displayed.

As described above, according to this embodiment, it is possible to easily obtain information on the error of the simulation result by each simulator in the design of the wiring board, and to correct the portion which is determined as the error by the layout and wiring design means. Is effective.

Embodiment 8 FIG. In the eighth embodiment, the result analyzed by the simulator is analyzed, the error in the design of the wiring board is specified, and the place where the error occurs is displayed as an image, so that the designer intuitively recognizes the error part. It is characterized by that.

FIG. 17 is a block diagram of a wiring board designing apparatus according to the eighth embodiment. In the figure, 29 is the error analysis means 2
7 is an error analysis result image display means for displaying the design data of the printed wiring board determined to be an error by the image data.

FIG. 18 is a diagram in which the wiring judged to be an error by the error analysis means 27 is highlighted on the error analysis result image display means 29.

Next, a procedure for highlighting a wiring which has been determined to be an error will be described. First, the simulation as shown in the first to sixth embodiments is executed. Then, the error analysis unit 27 analyzes the execution result of each simulation and visually displays the detected error on the error analysis result image display unit 29. For example, FIG. 16 shows an example of the waveform simulation result and the error criterion,
The waveform 41 as a result of the waveform simulation has an overshoot reference value 40 and an undershoot reference value 42.
Is over. Therefore, the error analysis unit 27 determines an overshoot error and an undershoot error, and highlights the wiring determined to have an error on the error analysis result image display unit 29 as shown in FIG.

As described above, according to this embodiment, there is an effect that a portion determined to be an error by each simulation in the design of the wiring board can be easily visually recognized.

Embodiment 9 In the ninth embodiment, the result analyzed by the simulator is analyzed, and the appropriate countermeasure against the error in the design of the wiring board is displayed, so that the design quality is improved and the designer's problem avoidance judgment ability is improved. It is characterized by making it uniform without relying on it.

FIG. 19 is a block diagram of a wiring board designing apparatus according to the ninth embodiment. In the figure, 30 is an error analysis unit 2.
A navigation processing means 31 for instructing a correction method or a treatment method for the design data of the printed wiring board determined to be an error in 7 is a navigation result reporting means 31 for outputting the instruction result of the navigation processing means 30 as a report.

FIG. 20 shows an example of dealing with the overshoot and undershoot errors shown in FIG.

Next, a procedure for instructing a correction method or a remedy method for an error will be described. First, the first embodiment
6 to 6 are executed. Then, the error analysis unit 27 analyzes the execution result of each simulation to detect an error. Then, the navigation processing means 30 gives an instruction on how to deal with the detected error, and displays a report on the navigation result reporting means 31.

For example, the error analysis means 27 detects an overshoot and an undershoot error, the navigation processing means 30 determines a method for avoiding the overshoot and undershoot errors, and the navigation result reporting means determines the error avoiding method. A report as shown in FIG. 20 is displayed at 31.

As described above, according to this embodiment,
Even in a wiring board design, even a beginner of wiring board design can easily and surely correct the placement / wiring information for a portion determined to be an error by each simulation and deal with the error.

[0082]

According to the first aspect of the present invention, any one of a plurality of simulators and an analysis preparation data storage means for storing power consumption parameters of electronic parts or electrical characteristic information parameters required by a plurality of simulators. And an analysis data processing means for changing the parameters stored in the analysis preparation data storage means, based on the simulation result, and each of the plurality of simulators inputs the parameters changed by the analysis data processing means. Since the simulation is executed again, highly accurate simulation is possible.

According to the second invention, as the simulator, a waveform simulator for analyzing a signal transmission waveform, a timing simulator for verifying correctness at a signal change point, a thermal simulator for analyzing a heat distribution of a wiring board, or a wiring board. Since the EMC simulator for analyzing the electromagnetic radiation noise is included, it is possible to simulate waveforms, heat, timing, electromagnetic radiation, and the like.

According to the third aspect of the present invention, since the time lapse control means for causing the plurality of simulators to repeatedly perform the simulation is provided until the electronic components are stably operated, the electronic components and the ambient environment parameters are brought to a steady state. It is possible to detect a malfunction in the process of.

According to the fourth invention, the analysis result history storage means for storing the simulation results of the plurality of simulators together with the simulation time, and the analysis result for extracting and displaying the simulation result at the designated time from the analysis result history storage means. Since the history display means is provided, it is possible to detect the operation failure in the process of reaching the steady state in detail.

According to the fifth aspect of the present invention, the layout and wiring design means for designing the layout and wiring of the electronic components, and whether or not the layout and wiring design means has moved, rotated or changed the wiring information of the electronic components. Operation monitoring means for monitoring,
Since the operation monitoring means includes the real-time control means for causing a plurality of simulators to execute the simulation when the change is detected, it is possible to optimize the placement and routing data while observing the simulation result.

According to the sixth aspect of the invention, when the operation monitoring means detects a change, the analysis difference data extracting means extracts the analysis data of only the changed portion, and before storing the analysis data before the change. The analysis data storage means and the analysis data synthesis means for synthesizing the analysis data extracted by the analysis difference data extraction means and the analysis data before the change stored in the pre-analysis data storage means are provided. Therefore, when the design data is changed, only the changed data needs to be extracted, and the data amount of the analysis data and the extraction time can be shortened.

According to the seventh aspect of the invention, there is provided critical path storage means for storing a critical path such as a bus or a high speed signal, and the operation monitoring means determines whether or not the critical path stored in the critical path storage means has been changed. The analysis differential data extraction means extracts the analysis data of only the changed part of the critical path when the critical path is changed, so that the data amount of the analysis data can be reduced and the extraction time can be shortened. It is possible.

According to the eighth invention, an error criterion for determining whether or not there is an error in the simulation results of a plurality of simulators is stored, and an error for specifying an error in the simulation result based on the error criterion is stored. Since the analysis means is provided, there is an effect that information regarding an error in the simulation result can be easily obtained.

According to the ninth invention, since the error analysis result report means for displaying the error specified by the error analysis means is provided, there is an effect that the error location can be corrected efficiently.

According to the tenth aspect of the invention, since the error analysis result image display means for displaying the image of the location where the error specified by the error analysis means has occurred is provided, the location determined to be an error can be visually recognized. effective.

According to the eleventh aspect of the invention, since the navigation processing means for displaying the method for avoiding the error specified by the error analysis means is provided, the placement / wiring information is corrected and the error is dealt with for the portion judged to be in error. Can be performed easily and reliably.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a wiring board design device according to a first embodiment.

FIG. 2 is a diagram showing images of various simulation results.

FIG. 3 is a configuration diagram showing a wiring board design device according to a second embodiment.

FIG. 4 is a diagram showing layout and wiring design data.

FIG. 5 is a diagram showing an image of an execution result of a simulation using the layout and wiring data of FIG.

FIG. 6 is a diagram showing placement and routing data obtained by moving a part A in the placement and routing data of FIG.

7 is a diagram showing an image of an execution result of a simulation using the layout and wiring data of FIG.

FIG. 8 is a configuration diagram showing a wiring board design device according to a third embodiment.

FIG. 9 is a diagram showing an image of an execution result of a simulation by the wiring board designing device according to the third embodiment.

FIG. 10 is a diagram showing an image of a result of execution of a simulation by the wiring board designing apparatus according to the third embodiment.

FIG. 11 is a diagram showing an image of an execution result of a simulation by the wiring board design device according to the third embodiment.

FIG. 12 is a configuration diagram showing a wiring board design device according to a fourth embodiment.

FIG. 13 is a configuration diagram showing a wiring board design device according to a fifth embodiment.

FIG. 14 is a configuration diagram showing a wiring board design device according to a sixth embodiment.

FIG. 15 is a configuration diagram showing a wiring board design device according to a seventh embodiment.

FIG. 16 is a diagram showing an error detection guideline and error contents for a waveform simulation result.

FIG. 17 is a configuration diagram showing a wiring board design device according to an eighth embodiment.

FIG. 18 is a diagram in which wiring that is determined to be in error is highlighted.

FIG. 19 is a configuration diagram showing a wiring board design device according to a ninth embodiment.

FIG. 20 is a diagram showing an example of coping with overshoot and undershoot errors.

FIG. 21 is a configuration diagram of a conventional printed wiring board design device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 input means, 2 operation monitoring means, 3 design preparation data storage means, 4 layout wiring design means, 5 design data storage means, 6 analysis data extraction means, 7 analysis data synthesis means, 8 analysis preparation data storage means , 9 data processing means for analysis, 10 waveform simulator, 11 timing simulator, 12 thermal simulator, 13 E
MC simulator, 14 waveform simulation result storage means, 15 timing simulation result storage means, 16 thermal simulation result storage means, 17 E
MC simulation result storage means, 18 simulation result display means, 19 analysis mode determination means, 20
Analysis cooperation control means, 21 Real-time control means, 22
Time-lapse control means, 23 Analysis difference data extraction means, 2
4 pre-analysis data storage means, 25 critical path storage means, 26 analysis result history display means, 27 error analysis means, 28 error analysis result report means, 29 error analysis result image display means, 30 navigation processing means, 31 navigation result report Means, 32
Analysis result history storage means

Front page continued (72) Inventor Eiji Yamamoto 2-3-3 Marunouchi, Chiyoda-ku, Tokyo Sanryo Electric Co., Ltd. (72) Inventor Toshiro Uchiyama 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Sanryo Electric Co., Ltd. In-house (72) Inventor Kiyoharu Fujimoto 2-3-3 Marunouchi, Chiyoda-ku, Tokyo Sanryo Electric Co., Ltd.

Claims (11)

[Claims] 1. A wiring board designing device for designing a printed wiring board or a multi-chip module board on which electronic components are arranged, and a plurality of simulators for executing simulations for supporting the design of the arrangement and wiring of the electronic components. An analysis preparation data storage means for storing power consumption parameters or electric characteristic information parameters of the electronic components required by the plurality of simulators, and the analysis based on a simulation result of any one of the plurality of simulators. Preparation data storage means for changing the parameters stored in the analysis data processing means, the plurality of simulators respectively input the parameters changed by the analysis data processing means, the simulation again. Wiring board installation characterized by carrying out Apparatus. 2. The above-mentioned simulator is a waveform simulator for analyzing a signal transmission waveform, a timing simulator for verifying correctness at a signal change point,
The wiring board design apparatus according to claim 1, wherein the wiring board design apparatus is a thermal simulator for analyzing a heat distribution of the wiring board or an EMC simulator for analyzing electromagnetic radiation noise of the wiring board. 3. The wiring board design apparatus according to claim 1, further comprising: a time-lapse control unit that causes the plurality of simulators to repeatedly perform the simulation until the electronic component operates stably. 4. An analysis result history storage means for storing simulation results of the plurality of simulators together with a simulation time, and an analysis result history display means for extracting and displaying the simulation results at a designated time from the analysis result history storage means. 4. The wiring board design device according to claim 3, further comprising: 5. A wiring board designing apparatus for designing a printed wiring board or a multi-chip module board on which electronic parts are arranged, inputs analysis data for simulation, and supports designing for arrangement and wiring of the electronic parts. A plurality of simulators for executing a simulation to perform the above, a layout and wiring design means for designing the layout and wiring of the electronic parts, and whether the electronic parts are moved, rotated, or the wiring information is changed by the layout and wiring design means. A wiring board designing device comprising: an operation monitoring means for monitoring whether or not there is any; and a real-time control means for causing the plurality of simulators to execute the simulation when the change is detected by the operation monitoring means. 6. An analysis differential data extracting means for extracting the analysis data of only a changed portion when the change is detected by the operation monitoring means, and a pre-analysis for storing the analysis data before the change. A data storage unit, and an analysis data composition unit that combines the analysis data extracted by the analysis difference data extraction unit and the pre-change analysis data stored in the pre-analysis data storage unit. The wiring board design apparatus according to claim 5, further comprising: 7. A critical path storage means for storing a critical path such as a bus or a high speed signal is provided, and the operation monitoring means monitors whether or not the critical path stored in the critical path storage means has been changed. 7. The wiring board design apparatus according to claim 6, wherein the analysis difference data extracting means extracts the analysis data of only a changed portion of the critical path when the critical path is changed. 8. An error analysis means for storing an error criterion for determining whether or not there is an error in the simulation results of the plurality of simulators, and for specifying an error in the simulation result based on the error criterion. The wiring board design device according to claim 1, wherein the wiring board design device is a wiring board design device. 9. The wiring board design apparatus according to claim 8, further comprising error analysis result report means for displaying the error identified by the error analysis means. 10. The wiring board design apparatus according to claim 8, further comprising an error analysis result image display means for displaying an image of the location where the error specified by the error analysis means has occurred. 11. The wiring board design apparatus according to claim 8, further comprising navigation processing means for displaying a method for avoiding the error identified by the error analysis means.