JPH09244776A - Signal transmitting method and semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the floating of a signal due to coupling capacity between adjacent wirings and to speedily transmit the signal at low amplitude by providing MOSFET for equalization between the adjacent signal wirings, turning on a precharge period and shorting a signal line. SOLUTION: A precharge circuit 40 and an equalizing circuit 50 are provided in the middle of a bus 30 constituted of signal lines B1-Bn connecting a driver circuit 10 on a transmission-side and a receiver circuit 29 on a reception-side. The precharge circuit 40 is constituted of NMOSQ1-Qn connected between power voltage Vcc and the respective signal lines B1-Bn and it off-controls MOSFET Q1-Qn at a clock Φ1. The equalizing circuit 50 is constituted of P channel-type MOSFET Q11-Q1n connected between the signal lines B1-Bn and a common drain line CDL. MOSFET Q11-Q1n are on/off-controlled with a clock-Φ whose phase opposite to the clock Φ1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal transmission technique and a technique effective when applied to signal transmission via a bus, and is effective when applied to a semiconductor integrated circuit having a bus such as a microcomputer. Regarding technology.

[0002]

2. Description of the Related Art Conventionally, as a technique for speeding up signal transmission in a logic circuit, for example, as described in "VLSI System Design" pp175-pp191 issued by Maruzen Co., Ltd., (1) signal amplitude is reduced. And (2) precharging the operating point to the high gain region of the receiver circuit.

[0003]

As a result of studying the above signal transmission techniques, the present inventors have found that each of the above techniques has the following problems.
That is, regarding the method (1) for reducing the amplitude of the signal, the circuit on the driver side is an N-channel MOSFE
Drive only by T (hereinafter referred to as NMOS) or N
There is a method of lowering the high level of the transmission signal by the threshold voltage of the MOSFET than the power supply voltage by configuring the MOS to be precharged. However, in a system in which signal lines are close to each other like a bus, a signal becomes higher than a preset high level (Vcc-Vth) via a coupling capacitance between adjacent lines, and changes to a low level. However, there is a problem that the speed becomes slow and the speed cannot be sufficiently increased.

On the other hand, in the method of precharging the operating point (2) to the high gain region of the receiver circuit, a level such as Vcc / 2 is selected as the precharge level, but the level of Vcc / 2 is selected. It is difficult to precharge accurately, and overshoot and undershoot occur to increase the signal propagation delay time. When CMOS logic gates are used in the precharge circuit and the receiver circuit, the signal line becomes Vcc / 2. While such a level is set, there is a problem that a through current flows through the logic gate, resulting in a large amount of wasted current consumption.

An object of the present invention is to provide a signal transmission technique which prevents signal floating due to coupling capacitance between adjacent wirings and enables high-speed signal transmission with low amplitude.

Another object of the present invention is to precharge an operating point in a high gain region of a receiver circuit and transmit a signal, thereby preventing a through current in the precharge circuit or the receiver circuit and reducing the current consumption. It is to provide a signal transmission technology that enables high-speed signal transmission.

Still another object of the present invention is to enable signal to be accurately precharged to Vcc / 2 level in a system in which an operating point is precharged to a high gain region of a receiver circuit and a signal is transmitted. It is to provide a signal transmission technology that reduces high frequency and enables high-speed signal transmission.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, an equalizing MOSFET is provided between adjacent signal lines such as bus signal lines, and the M
By turning on the OSFET during the precharge period to short-circuit the signal line, floating of the signal due to the coupling capacitance between the adjacent wirings is prevented and high-speed signal transmission with low amplitude is enabled.

Alternatively, by connecting a clamp element to each signal line so as to prevent the level from rising above a preset level, it is possible to prevent the signal from floating due to the coupling capacitance between the adjacent wirings and to suppress the low amplitude. Enables high-speed signal transmission.

Further, in the method of transmitting a signal by precharging the operating point to the high gain region of the receiver circuit, the optimum pulse width considering the time required to precharge the signal line without depending on the clock cycle. A pulse generation circuit for forming a pulse having a pulse width is provided to control the transmission gate on the output side of the precharge circuit to prevent a shoot-through current in the precharge circuit and the receiver circuit, thereby reducing the current consumption and increasing the speed. Enables signal transmission.

Further, in a system in which an operating point is precharged in a high gain region of a receiver circuit and a signal is transmitted, a logic threshold value of a logic gate for detecting a level of a signal line is set so as to deviate from a precharge level. The precharge end signal is generated earlier so that the signal can be accurately precharged to a desired level, the signal propagation delay time is reduced, and high-speed signal transmission is enabled.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention. In this embodiment, the driver circuit 1 on the transmission side
A precharge circuit 40 and an equalize circuit 50 are provided in the middle of a bus 30 composed of signal lines B1, B2, B3 to Bn connecting 0 and the receiver circuit 20 on the receiving side. The precharge circuit 40 has a power supply voltage Vcc.
And NMOSs Q1, Q2, Q3 to Qn connected between the signal lines B1, B2 and B3 to Bn, respectively,
These MOSFETs Q1 to Qn are configured to be on / off controlled by a clock φ1. In addition, the equalizer circuit 50 includes the signal lines B1 and B1.
2, P3 MOSFETs Q11, Q12 to Q1 connected between B3 to Bn and the common drain line CDL
n, and these MOSFETs Q11 to Q1n are configured to be on / off controlled by a clock / φ1 having a phase opposite to that of the clock φ1.

On the other hand, the output stage of the driver circuit 10 is constituted by an NMOS Q21 connected between the signal lines B1, B2, B3 to Bn and the ground point, and the output NMOS Q21 outputs the clock signal. It is configured to be driven by an AND gate 12 which receives a signal φ to be transmitted and a clock φ2 having a substantially opposite phase formed so that the high level does not overlap with φ1.

Next, the operation of the circuit of this embodiment will be described with reference to the timing chart of FIG. In this embodiment, the high level period of the clock φ1 corresponds to the precharge period of the bus 30, and the high level period of the clock φ2 corresponds to the bus drive period. FIG. 2 shows a state in which the signal lines B1 and B3 of the bus are in the low level state and the signal line B2 is in the high level state until the next signal is output to the bus.

When the clock φ1 changes to the high level at the timing t1, the NMOSs Q1 to Qn are turned on and the precharge of the signal lines B1 to Bn is started. At this time, since the precharge MOSFET is an N-channel type, if its threshold voltage is Vth, the signal lines B1 and B3 are charged from the low level state to Vcc-Vth. Since the signal line B2 is originally in the high level state, if the equalizing circuit 50 is not provided, as shown by the dotted line in FIG. 2, the coupling capacitance Cs parasitic between the adjacent signal lines B1 and B3 is eliminated. Via the influence of the change of B1 and B3 to the high level, the voltage rises to near Vcc.

However, in this embodiment, at the same time when the MOS Q1 to Qn of the precharge circuit 40 are turned on, the MOSFETs Q11 to Q of the equalize circuit 50 are simultaneously turned on.
Since 1n is turned on and each signal line is short-circuited,
The signal line B2, which is originally in the high level state without being affected by the coupling capacitance, remains at the high level as shown by the solid line in FIG. 2 to prevent the level from rising. Moreover, since the MOSFETs Q11 to Q1n are turned on and the signal lines are short-circuited, charge flows from the signal line at the high level to the signal line at the low level due to charge sharing, so that the bus pre- There is an advantage that the time required for charging is also shortened.

In the embodiment of FIG. 1, the equalizing MOSFETs Q11 to Q1n are connected to the signal lines B1 to Bn.
However, the equalizing MOSFETs may be connected between the signal lines.

FIG. 3 shows a second embodiment of the present invention. In this embodiment, a clamp circuit 60 is provided instead of the equalizing circuit 50 in the embodiment of FIG. The clamp circuit 60 includes signal lines B1, B2, B
3 ... and P-channel MOSFETs Q31, Q32, Q33, ... Connected between the ground point and the MOSFE connected in series between the power supply voltage Vcc and the ground point.
Comprised of T Q41, Q42 and Q43
A constant voltage generating circuit 61 for applying a constant voltage Vx to the gate terminals of TQ31, Q32, Q33 ,.

In this embodiment, the MOSFET Q4
From the constant voltage generating circuit 61 including 1 to Q43, Vcc-
A constant voltage Vx such as Vth is applied to MOSFETs Q31, Q
32, Q33 ... Are applied to the gates. As a result, for example, as shown in FIG. 4, the signal lines B1 and B3 of the bus are changed from the low level state to the signal line B2.
Considering the case where the precharge is performed from the state of high level, the level of the signal line B2 is Vcc or more due to the coupling capacitance Cs as the signal lines B1 and B3 change from low level to high level. The above MOSFETs Q31, Q32, Q33
The corresponding MOSFET among the ... Turns on to release the charges on the signal line to the ground point, thereby operating to clamp the level of the signal line. As a result, the amplitude of the signal transmitted from the driver circuit 10 to the receiver circuit 20 via the bus can be reduced and the speed can be increased.

FIG. 5 shows a third embodiment of the present invention. In this embodiment, the driver circuit 1 on the transmission side
In the middle of the signal line B connecting 0 and the receiver circuit 20 on the receiving side, a half precharge circuit 70 for precharging the signal line to approximately Vcc / 2 which is the high gain region of the receiver circuit 20 is provided. It is a thing.

The half precharge circuit 70 includes an inverter G1 having an input terminal connected to the signal line B and a second inverter G connected to the output terminal of the inverter G1.
2 and PMOS MP5, NMOS constituting a third inverter G3 connected to the output terminal of the inverter G2
MN2, the gate of the PMOS MP5 and the power supply voltage V
cc and a gate connected to the output terminal of the inverter G1 connected to the PMOS MP4 and the NMOS
An NMOS M connected between the gate of MN2 and the ground point, and connected to the output terminal of the inverter G1 at the gate
N1 and PMOS MP5 and NMO which form the output terminal of the second inverter G2 and the third inverter G3.
By P-channel type transmission gate MOS MP1 and MP2 respectively connected to the gate of S MN2 and N-channel type transmission gate MOS MN3 connected to the output node Nx of the third inverter G3. It is configured.

Then, the transmission gate MOS MP1,
At the gates of MP2 and MN3, an inverted clock of the clock φ0 corresponding to the clock φ1 in the first embodiment /
φ0 is applied. The high level period of the inverted clock / φ0 corresponds to the precharge period of the bus, and the low level corresponds to the drive period of the bus. The half precharge circuit 70 outputs the output node N during the bus driving period (/ φ0 is at a low level).
It is configured such that x has a level opposite to the level of the signal line B. However, at this time, since the transmission gate MOS MN3 on the output node Nx side is turned off, the level of the signal line B is not affected by the level of the output node Nx.

The half precharge circuit 70 starts charging up or discharging of the output node Nx from a level opposite to the level of the signal line when the precharge is started and reaches the level of Vcc / 2 when it reaches the level of Vcc / 2. Three
Inverter G3's PMOS MP5 and NMO
Both S MN2 are turned off and are configured to hold their level for the rest of the precharge.

Next, the operation of the circuit of this embodiment will be described with reference to the timing chart of FIG. FIG. 6 shows a state in which the precharge is started from the state where the signal line B of the bus is at the low level and the next signal is output to the bus. Therefore, the initial state (period T1) of the output node Nx of the half precharge circuit 70 is at high level. At this time, the output of the inverter G1 is at the high level, the output of the second inverter G2 is at the low level, and the transmission gate MOS MP1 and MP2 are turned on, the output of the third inverter G3 is at the high level. It is a level.

When the clock / φ0 changes to the high level at the timing t1, the transmission gate MOS MN2 is turned on, the precharge of the signal line B is started by the inverter G3, and the level of the signal line B gradually rises (period T2. ). The level of the signal line B changes to the inverter G1.
Exceeds the logic threshold value of Vcc / 2, the output of G1 is inverted from the high level to the low level, and the MOSFET
MN1 transitions from on to off and MOSFET MP4 transitions from off to on. This allows the inverter G
The third PMOS MP5 is turned off. On the other hand, NMOS
MN1 changes from on to off, but by that time the transmission gate MOS MP2 has been turned off by the clock / φ0, so the gate of the NMOS MN2 of the inverter G3 holds the previous low level, and thus the MOSFET MP5 forming the inverter G3. , MN2 are both turned off. As a result, the output node Nx and the signal line B are brought into a high impedance state while maintaining the level of Vcc / 2 (period T3).

After that, at the timing t2, the clock / φ0
When the signal changes to the low level, the transmission gate MOS MP3 is turned off, and when the driver circuit 10 on the transmission side starts output, the signal line B changes to the high level or the low level according to the signal (period T4). When the precharge is started from the state where the signal line of the bus is at the high level, the signal line B is Vcc due to the reverse operation of the PMOS and NMOS constituting the half precharge circuit 70.
Is once discharged to Vcc / 2.

As described above, in this embodiment, since the signal line is precharged to Vcc / 2 by the half precharge circuit 70 and then the signal line is driven to the high level or the low level by the driver circuit 10, the signal line is driven. The time until the level changes is shortened, and high-speed signal transmission becomes possible.

In this embodiment, unlike the first and second embodiments, the driver circuit 10 needs to be able to drive the signal line even in the high level direction. Therefore, the output stage of the driver circuit 10 of this embodiment has an NMOS Q21 connected between the signal line B and the ground point and a PMOS Q connected between the signal line B and the power supply voltage Vcc.
22 and the MO of these
NAN having clock φ0 or / φ0 and signal E to be transmitted as input signals for driving S Q21 and Q22
A D gate 13 and a NOR gate 14 are provided.

FIG. 7 shows a fourth embodiment of the present invention. In this embodiment, the transmission gate MOS MP1 and M
A pulse generation circuit 80 for forming a clock Y for controlling P2 and MN3 is provided. In the embodiment of FIG. 5, the period T3 during which the signal line is in the floating state during the precharge period depends on the cycle of clock / φ0, and the longer the period, the longer the floating period, and the half precharge circuit 70 during that period. There is a problem that a through current flows through the first-stage inverter G1 of the above.
Therefore, in this embodiment, the clock Y having the optimum pulse width in consideration of the time required for precharging the signal line without depending on the cycle of clock / φ0 is clock / φ0.
A pulse generating circuit 80 formed on the basis of the above is provided to supply to the transmission gates MOS MP1, MP2 and MN3. As a result, the through current flowing through the inverter G1 can be reduced and the current consumption can be reduced.

FIG. 8 shows a timing chart of the fourth embodiment. As is clear from comparison with FIG. 6, according to this embodiment, the period T3 during which the signal line is in the floating state during the precharge period can be shortened as compared with the third embodiment, and the through current of the inverter G1 can be reduced. Can be reduced. Moreover, as the pulse generation circuit 80, by utilizing the gate delay time of the logic gate circuit, for example, the clock / φ0 is provided to one input terminal of the OR gate and the clock / φ0 is provided to the other input terminal of the OR gate. By using a one-shot pulse generation circuit configured to generate a pulse whose total delay time of the logic gate array matches the pulse width by inputting a delayed signal through a plurality of logic gate arrays connected in series. Then, the pulse width of the clock Y can be a clock having a constant pulse width that does not depend on the cycle of the clock / φ0.

By doing so, there is an advantage that the effect of reducing the consumption current becomes great especially in a system in which the frequency of the reference clock is low. Moreover, when the power supply voltage of the circuit drops, the driving force of the signal line B by the half precharge circuit 70 also drops and the time required for precharging becomes long. However, pulse generation using the delay time of the logic gate as described above occurs. According to the circuit, there is an advantage that it is very convenient because the delay time of the logic gate becomes longer and the pulse width of the generated pulse becomes wider as the power supply voltage decreases.

FIG. 9 shows a half precharge circuit according to the fifth embodiment of the present invention. The half precharge circuit 70 of this embodiment includes a pair of inverters G11 and G12 each having an input terminal connected to a signal line B forming a bus.
A NAND gate G13 and a NOR gate G1 which use the outputs of these inverters G11 and G12 as input signals, respectively.
4 and the NAND gate G13 and NOR gate G1 connected in series between the power supply voltage Vcc and the ground point.
PMOS MP whose gates are respectively driven by 4
11 and NMOS MN11 and the PMOS MP1
1 and the transmission gate MOS MN12 connected between the connection node Nx of the NMOS MN11 and the signal line B.
And the pair of inverters G11 and G12 on the input side are designed to have different logic threshold values.

Specifically, the logic threshold value of the inverter G11 is set to a value VLTH slightly higher than Vcc / 2, and the logic threshold value of the inverter G12 is set to a value VLTL slightly lower than Vcc / 2. There is.

The half precharge circuit 70 of this embodiment
As shown in FIG. 10A, when the level of the signal line B before starting the precharge is low level, the PMOS M
P11 is turned on to raise the level of the signal line B to Vc
When c / 2 is reached, the PMOS MP11 is turned off (NMOS MN11 remains off) to precharge the signal line B to the level of Vcc / 2, and then the driver circuit 10 sets the signal line B to the high level. Or drive to low level.

On the other hand, as shown in FIG. 10B, when the level of the signal line B before starting the precharge is high level, the NMOS MN11 is turned on to lower the level of the signal line B to Vcc / 2. Reaches the NMOS MN1
The signal line B is discharged to the level of Vcc / 2 by turning off 1 (the PMOS MP11 remains off), and then the signal line B is discharged by the driver circuit 10.
Is driven to high level or low level.

By the way, as can be inferred from the circuit configuration of FIG. 9, the signal line B and the PMOS MP11 for driving it are provided.
And two logic gates G11, G13 and G12, G14 are respectively interposed between the gate terminal of the NMOS MN11 and the gate terminal of the NMOS MN11. Therefore, if the first stage inverter G
Assuming that the logic thresholds of 11 and G12 are just Vcc / 2, the PMOS MP11 or NM depends on the delay time of these logic gates G11 to G14.
The timing of turning off the OS MN11 is delayed, and the signal line B is precharged to a level at which Vcc / 2 is overshooted or undershot. Therefore, in the embodiment of FIG. 9, the logic threshold value of the inverter G11 is a value VLTH slightly higher than Vcc / 2, and the logic threshold value of the inverter G12 is a value VLTL slightly lower than Vcc / 2. Since it is set, before the signal line B is precharged to a level that overshoots or undershoots Vcc / 2, the PMOS
The MP11 or the NMOS MN11 is turned off, and the signal line B is precharged to Vcc / 2.

FIG. 11 shows a half precharge circuit according to the sixth embodiment of the present invention. In the embodiment of FIG. 9, the bus drive period (φ0 high level period)
Since the potential of the signal line B is introduced into the half precharge circuit 70, the through current flows through the first-stage inverters G11 and G12 especially at the beginning of the drive period. Therefore, the half precharge circuit 70 of this embodiment has N inverters instead of the inverters G11 and G12 in the embodiment of FIG.
The AND gate G21 and the NOR gate G22 are used, the signal line B is commonly connected to one input terminal of these gate circuits, and the clocks / φ0, φ are connected to the other input terminal.
It is designed to input 0. by this,
It is possible to prevent a through current from flowing through the first-stage logic gate during the drive period. Note that, also in this embodiment, the NAND gates G21 and N, which are the first-stage logic gates,
The logical threshold value of the OR gate G22 is set to a value VLTH slightly higher than Vcc / 2 and a value VLTL slightly lower than Vcc / 2.

FIG. 13 shows an embodiment of a receiver circuit 20 suitable for use when the precharge method of the first and second embodiments is used. The receiver circuit 20 of this embodiment has a transmission gate MOSFET MN3.
A latch circuit 21 composed of a pair of inverters G31 and G32 whose input and output terminals are coupled to each other can be connected to the signal lines B1, B2 and B3 via 1, MN32 and MN33.

Transmission gate MOSFETs MN31 to MN
When the latch circuit is directly connected to the signal line without passing through 33, even if the signal line is precharged to Vcc-Vth by the precharge circuit 40, the output of the inverter G32 of the latch circuit is set to the Vcc level. Therefore, at that time, a current flows from the latch circuit 21 side toward the signal.

However, as described above, the transmission gate MOS
By connecting the receiver circuit via the FETs MN31 to MN33, even if the inverter G32 outputs a high level, the transmission gate MOSFETs MN31 to MN
Since there is a voltage drop of 33 at the threshold voltage, no current flows from the receiver circuit 20 toward the signal lines B1 to B3. Moreover, the receiver circuit 20 of this embodiment is
Multiple (three in the figure) transmission gate MOSFETs MN3
1, MN32, MN33 through a plurality of signal lines B1-B
3, the receiver circuit 20 is selectively connected to a desired signal line by setting any one of the control signals Tn1, Tn2 and Tn3 supplied to their gate terminals to a high level. Can also be used as a selector circuit to be connected to. G33 is an inverter for waveform shaping.

FIG. 13 shows the third, fourth, fifth and sixth.
An example of a receiver circuit 20 suitable for application when the half precharge method of the embodiment is used is shown. The receiver circuit 20 of this embodiment includes a transmission gate MO.
Through the SFETs MN31, MN32, MN33, a latch circuit 21 composed of a modified inverter G31 ′ whose input and output terminals are coupled to each other and a feedback inverter G32 can be connected to the signal lines B1, B2, B3.

In this embodiment, the inverter G31 'forming the latch circuit 21 is the original PMOS MP4.
1 and NMOS MN41, power supply voltage Vcc and PM
It is configured to have an NMOS MN42 connected between it and the OSMP41. This NMOS MN42 is
Since its gate is coupled to the drain and acts as a diode, one of the transmission gate MOSFETs is in a state where the signal lines B1 to B3 are precharged to Vcc / 2.
MN31, MN32, MN33 are turned on and PMOS
Even if MP41 and NMOS MN41 are turned on, NMO
When S MN42 is turned off, the inverter G31 '
It makes it difficult for the through current to flow. Furthermore, the NMO
Since the S MN41 is provided, the inverter G31 '
Since the high level of the output of the inverter does not rise to Vcc and a through current may flow to the output inverter G33, the PMOS MP42 controlled by the output of the feedback inverter G32 causes the output terminal of the inverter G31 ′ and the power supply voltage Vcc to be different from each other. Is connected in between. This PMO
When SMP42 is turned on, the next-stage inverter G33
Since the input of will be raised to Vcc, G33
A through current is prevented from flowing in.

Further, the receiver circuit 20 of this embodiment is
Transmission gate MOSFET MN31, MN32, MN3
Inverter G32 to V when any of 3 is turned on
In order to prevent the current from flowing toward the cc / 2 level signal line, when any one of the control signals Tn1, Tn2 and Tn3 is at the high level, the feedback path is cut off and the control signals Tn1, Tn2 and Tn3 are cut off. Is set to a low level and the receiver circuit 20 is fed back only when the receiver circuit 20 is completely disconnected from the signal line, so that the signal can be latched and the transmission gate M can be latched.
The OSFET MN40 is connected between the output terminal of the inverter G32 and the input terminal of the inverter G31.

FIG. 15 is a block diagram of a microcomputer as an example of a semiconductor integrated circuit device to which the signal transmission system of the present invention is preferably applied.

In the figure, 110 is a microprocessor, 120 is a RAM (random access memory),
130 is a read only memory (ROM), 140 is a DMA controller for controlling data transfer, 150 is an address decoder, which is a microprocessor 110 and a RAM.
120, ROM 130, and DMA controller 140 are connected to each other via a data bus 160 and an address bus 170.

Further, the microprocessor 110, R
AM120, ROM130 and DMA controller 1
40 is a driver circuit 10 and a receiver circuit 2 respectively.
0, which enables bidirectional signal transmission via the bus 30. In FIG. 15, reference numerals TG11 to TG11 to
The transfer gate MOSFE shown in FIGS. 13 and 14 is shown by TG14 and TG21 to TG24.
These gates correspond to TMN31, MN32, and MN33, and these gates select signals CS1 to CS1 formed by the address decoder 150 decoding the address output from the microprocessor 110 or the DMA controller 140 onto the address bus 170. CS
It is configured to be controlled to be opened and closed by 4.

As described above, in the above embodiment, the equalizing MOSFET is provided between the signal lines of the bus, and the M
Since the OSFET is turned on during the precharge period to short-circuit the signal line, the floating of the signal due to the coupling capacitance between the adjacent signal lines is prevented, and the high-speed signal transmission with the low amplitude can be achieved. .

Further, since the clamp element for clamping is connected to each signal line so that the level does not rise above a preset level, the signal floating due to the coupling capacitance between the adjacent signal lines is prevented. This has the effect of enabling high-speed signal transmission with low amplitude.

Further, in the method of transmitting a signal by precharging the operating point to the high gain region of the receiver circuit, the optimum pulse width considering the time required for precharging the signal line does not depend on the clock cycle. Since a pulse generation circuit for forming a pulse having a pulse width is provided to control the transmission gate on the output side of the precharge circuit, a through current in the precharge circuit or the receiver circuit is prevented, and low current consumption and high speed are achieved. This has the effect of enabling signal transmission.

Further, in the system for transmitting a signal by precharging the operating point to the high gain region of the receiver circuit, the logic threshold value of the logic gate for detecting the level of the signal line is set to Vc.
Since the precharge end signal is generated earlier by shifting from c / 2, it is possible to accurately precharge to the Vcc / 2 level, which reduces the signal propagation delay time and enables high-speed signal transmission. The effect is that it will be possible.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in the above embodiment, the selection gate is provided only on the receiver circuit 20 side, but as shown in FIG. 15, the selection gates TG21 and TG22 may be provided on the driver circuit 10 side as well.

In the above description, the case where the invention made by the present inventor is mainly applied to signal transmission through a bus, which is the field of application of the background, has been described, but the present invention is not limited thereto. , Signal transmission can be generally used.

[0056]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the present invention prevents the signal from floating due to the coupling capacitance between the adjacent wirings,
High-speed signal transmission with low amplitude can be enabled.

Further, in the system in which the operating point is precharged in the high gain region of the receiver circuit and the signal is transmitted, the through current in the precharge circuit and the receiver circuit is prevented, and the high speed signal transmission with the low current consumption becomes possible. In addition, the signal line can be accurately precharged to the Vcc / 2 level, the signal propagation delay time is reduced, and high-speed signal transmission becomes possible.

[Brief description of drawings]

FIG. 1 is a first example in which the present invention is applied to signal transmission via a bus.
2 is a circuit configuration diagram showing an embodiment of FIG.

FIG. 2 is a time chart showing the timing of the first embodiment.

FIG. 3 is a second example in which the present invention is applied to signal transmission via a bus.
2 is a circuit configuration diagram showing an embodiment of FIG.

FIG. 4 is a time chart showing the timing of the second embodiment.

FIG. 5 is a circuit configuration diagram showing an example of a half precharge circuit according to a third embodiment of the present invention.

FIG. 6 is a time chart showing the timing of the third embodiment.

FIG. 7 is a circuit configuration diagram showing an example of a half precharge circuit according to a fourth embodiment of the present invention.

FIG. 8 is a time chart showing the timing of the fourth embodiment.

FIG. 9 is a circuit configuration diagram showing an example of a half precharge circuit according to a fifth embodiment of the present invention.

FIG. 10 is a time chart showing the timing of the fifth embodiment.

FIG. 11 is a circuit configuration diagram showing an example of a half precharge circuit according to a sixth embodiment of the present invention.

FIG. 12 is a time chart showing the timing of the sixth embodiment.

FIG. 13 is a circuit configuration diagram showing an embodiment of a receiver circuit suitable for application when the precharge method of the first and second embodiments is used.

FIG. 14 is a circuit configuration diagram showing an embodiment of a receiver circuit suitable for application when the half precharge method of the third to sixth embodiments is used.

FIG. 15 is a block diagram showing the configuration of a microcomputer as an example of a semiconductor integrated circuit device to which the signal transmission system of the present invention is applied.

[Explanation of symbols]

 10 Driver Circuit 20 Receiver Circuit 30 Bus 40 Precharge Circuit 50 Equalize Circuit 60 Clamp Circuit 70 Half Precharge Circuit 80 Pulse Generation Circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takayuki Kuchiki 5-22-1 Kamimizuhoncho, Kodaira-shi, Tokyo Inside Hitachi Microcomputer System Co., Ltd. (72) Inventor Yutaka Shinagawa 5-chome, Mizumizuhoncho, Kodaira-shi, Tokyo 22-1 No.1 Hitachi Microcomputer System Co., Ltd. (72) Inventor Takanaga Yamazaki 5-20-1 Kamisuihonmachi, Kodaira-shi, Tokyo Inside Semiconductor Division, Hitachi, Ltd.

Claims (6)

[Claims] 1. A signal transmitting side circuit and a receiving side circuit are connected by a signal line, the signal line is precharged to a predetermined level in advance, and then the signal line is driven by the transmitting side circuit. In the signal transmission method, an equalizing MOSFET is provided between adjacent signal wirings, and the MOSFET is turned on during a precharge period to short-circuit the signal line. 2. A signal transmitting side circuit and a receiving side circuit are connected by a signal line, the signal line is precharged to a predetermined level in advance, and then the signal line is driven by the transmitting side circuit. In the signal transmission method, a clamp element is connected to each signal line to clamp the signal line so that the level of the signal line does not rise above a preset level during precharge. 3. A method for transmitting a signal by precharging an operating point to a high gain region of a circuit on the receiving side, which is optimal in consideration of the time required to precharge the signal line without depending on the clock cycle. A signal transmission method characterized in that a pulse generation circuit for forming a pulse having a pulse width is provided to control a transmission gate on an output side of a precharge circuit. 4. In a method of transmitting a signal by precharging an operating point to a high gain region of a circuit on the receiving side, the logic threshold value of a logic gate for detecting the level of a signal line is deviated from the precharge level and set. A signal transmission method characterized in that a precharge end signal is generated earlier so as to accurately precharge to a desired level. 5. A circuit on the signal transmitting side and a circuit on the receiving side are connected by a signal line, the signal line is precharged to a predetermined level in advance, and then the signal line is driven by the circuit on the transmitting side. In the signal transmission method, a gate means capable of connecting / disconnecting the signal line and the receiving circuit is provided between the signal receiving side circuit and the signal line, and the gate means is connected to the gate means during a precharge period of the signal line. A signal transmission method characterized in that a receiving circuit is cut off from a signal line. 6. A semiconductor integrated circuit having a plurality of functional blocks including a circuit for signal transmission and a circuit for signal reception, wherein the functional blocks are connected by a bus. Is connected in advance with a precharge circuit for precharging to a predetermined level, and the signal transmission between the functional blocks is performed by the signal transmission method according to any one of claims 1 to 5. Integrated circuit.