JPH09244593A - Liquid crystal driving circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal driving circuit which can display adequate gradation even if the number of gradation levels using a frame thinning method increases. SOLUTION: In this circuit, a liquid crystal display panel 7 is driven by a scanning signal and a display signal, the prescribed number of frames is made one period, gradation display of display data is performed by thinning display of frames corresponding to the number of display gradations of display data for each period. Display data of four gradations are stored in three frame memories of a frame memory 4, and a timing control circuit 2 controls scanning signal generation timing in displaying each frame based on time data stored in time registers T1-T3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal driving circuit, and more particularly, to a frame thinning method FRC (Frame Rate Co
The present invention relates to a liquid crystal drive circuit that performs gradation display by using the control.

[0002]

2. Description of the Related Art Recently, liquid crystal display devices perform not only binary display of white and black but also multi-gradation display for displaying an intermediate state between "white" and "black" with the spread of liquid crystal. This improves the sense of reality.

It is called the number of gradations whether this intermediate state is divided into several levels. The larger the number of gradations, the more various images can be represented.

For such high gradation display, conventionally, for example, when an STN (Super Twisted Nematic) type liquid crystal cell is used, the liquid crystal is displayed when one display data is displayed with a plurality of frames as one cycle. Frame decimation method FRC which expresses gradation by changing the number of times of lighting
(Frame Rate Control) is used.

In the frame thinning method, for example, assuming that the number of frames is 3, 0 times out of 3 frames,
By changing the number of selections according to the number of gradation levels, such as once, twice, and three times, the effective voltage applied to the pixel is changed to perform gradation display.

That is, according to the frame thinning method, when m frames are used as one unit, n times (0 ≦ n ≦ m) are selected when m times of scanning when a certain display pixel is focused. Thus, it is possible to realize a maximum m + 1 gradation display.

[0007]

However, in the above-described frame thinning method, the effective voltage difference in each gradation is equal, but the liquid crystal generally has a transmitted light characteristic with respect to the driving effective voltage as shown in FIG. Is non-linear, as the number of gray levels increases, this non-linearity makes the difference in transmitted light ratio between each gradation non-uniform and, in part, reduces the difference between each gradation. However, there is a problem that it becomes difficult to distinguish the difference in brightness.

Therefore, the present invention has been made to solve the above problems, and in a liquid crystal drive circuit using a frame thinning method, a liquid crystal capable of displaying an appropriate gradation even if the number of gradation levels is increased. An object is to provide a driving circuit.

[0009]

According to a first aspect of the present invention, there is provided a liquid crystal drive circuit, wherein a liquid crystal display panel is driven by a scanning signal and a display signal, a predetermined number of frames are set as one cycle, and a display floor of display data is displayed in each cycle. It is a liquid crystal drive circuit that performs gradation display of display data by thinning out the display of frames corresponding to the number of tones, and stores a plurality of frame memories that store display data that is responsible for display signals and time data that corresponds to each frame. It is characterized by comprising time data storage means for storing and timing control means for controlling scanning signal generation timing when displaying each frame based on the time data stored in the time data storage means.

That is, according to the liquid crystal drive circuit of the first aspect, the liquid crystal display panel is driven by the scanning signal and the display signal, and a predetermined number of frames are set as one cycle, and the number of display gradations of display data is set for each cycle. Is a liquid crystal drive circuit for thinning out the display of the frames corresponding to, and displaying the gradation of the display data. The display data is stored in a plurality of frame memories and the time data corresponding to each frame is stored in the time data storage means. The timing control means controls the scanning signal generation timing when displaying each frame based on the time data stored in the time data storage means.

Therefore, in the frame thinning method, the selection time per pixel of each frame can be controlled,
By setting an appropriate selection time for each frame,
It is possible to avoid the phenomenon that the difference in brightness between the gradations becomes small due to the nonlinear characteristic of the driving effective voltage of the liquid crystal and the light transmittance, and it is possible to display the gradation of the liquid crystal properly.

Further, in this case, as in the invention described in claim 2, the timing control means is set with the time data stored in the time data storage means, and the time data is down-counted to a predetermined number. Corresponding to a scanning timing signal generating means for outputting a scanning timing signal every time counting, a frame number designating means for counting the scanning timing signal and designating a frame number, and a frame number designated by the frame number designating means. It is effective to provide time data setting means for selecting time data to be stored from the time data storage means and setting it in the scanning timing signal generation means.

That is, according to the liquid crystal display circuit of the second aspect, the timing control means includes the scanning timing signal generating means, the frame number designating means, and the time data setting means, and the scanning timing signal generating means. Whenever the time data stored in the time data storage means is set and the time data is down-counted and a predetermined number is counted, a scanning timing signal is output, and the frame number designating means counts the scanning timing signal. Then, the frame number is designated, and the time data setting means selects the time data corresponding to the frame number designated by the frame number designating means from the time data storing means and sets it in the scanning timing signal generating means.

Therefore, in addition to the effect of the invention described in claim 1, proper gradation display of liquid crystal can be performed with a simple circuit configuration.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. 1 to 3 are diagrams for explaining a liquid crystal drive circuit according to an embodiment of the present invention.

First, the structure will be described.

FIG. 1 is a block diagram showing the configuration of the liquid crystal drive circuit 1, showing a liquid crystal drive circuit for displaying gray scales by the frame thinning method. In this embodiment,
An example is shown in which display data of four gradations is displayed with three frames as one cycle. FIG. 2 is a timing chart of signals of each part of the liquid crystal drive circuit 1, and FIG. 3 is a combination diagram of each frame in the case of performing 4-gradation display.

In FIG. 1, the liquid crystal drive circuit 1 is composed of a timing control circuit 2, a data read circuit 3, a frame memory 4, a scan electrode drive circuit 5, a signal electrode drive circuit 6, a liquid crystal display panel 7, and the like. Further, the timing control circuit 2 includes a timing signal generation circuit 21, a counter 22, a line counter 23, an FLM generation circuit 24,
It is composed of an FLM number circuit 25, a selector 26, and time registers T1 to T3.

As the liquid crystal display panel 7, a simple matrix type liquid crystal display panel is used here, and a plurality of scanning electrodes (common electrodes) X1 to Xm and a plurality of signal electrodes (segment electrodes) Y1 to Yn are used. STN (Super Twis
ted Nematic) are arranged opposite to each other with a liquid crystal layer in between, and are arranged in a matrix. And the liquid crystal display panel 7
Is a scan (common) signal and a display (segment) signal supplied from a scan electrode (common electrode) drive circuit 5 and a signal electrode (segment electrode) drive circuit 6 described later,
The scanning electrodes X1 to Xm and the signal electrodes Y1 to Yn are selectively driven, and gradation display according to display data is performed with three frames as one cycle.

The scan electrode drive circuit 5 sequentially outputs scan signals based on the scan timing signal CL1 as shown in FIG. 2B and the frame timing signal FLM as shown in FIG. 2A, which are supplied from the timing control circuit 2. Scan electrode X1
By outputting to Xm, the scan electrodes X1 to Xm are sequentially selected and driven.

The signal electrode drive circuit 6 is composed of, for example, a binary level driver, and is supplied from the data read circuit 3 based on the clock signal CL2 as shown in FIG. Of the display data, and a display signal corresponding to the acquired data is supplied to the signal electrodes Y1 to Yn.

The timing control circuit 2 generates various timing signals for controlling the display of the liquid crystal display panel 7 and supplies them to the data reading circuit 3, the scan electrode driving circuit 5 and the signal electrode driving circuit 6.

Specifically, the timing signal generation circuit 21
Generates the basic clock CK and supplies it to the counter 22, and also generates the clock signal CL2 as shown in FIG. 2C and supplies it to the data read circuit 3 and the signal electrode drive circuit 6.

The counter 22 comprises a synchronous down counter with a data loading function, down counts the time data supplied from the selector 26 in synchronization with the basic clock CK supplied from the timing signal generation circuit 21, and counts. Every time the value becomes “0”, the scan timing signal CL1 as shown in FIG. 2B is supplied to the scan electrode drive circuit 5 and the data read circuit 3. This scanning timing signal C
The selection time of the scan electrode of each frame is set based on the cycle of L1.

The line counter 23 supplies the scanning timing signal CL1 supplied from the counter 22 as shown in FIG.
A timing signal is supplied to the FLM generation circuit 24 every time a predetermined number (the number m of scanning electrodes of the liquid crystal panel 7) is counted.

The FLM generation circuit 24 uses the line counter 2
2 based on the timing signal supplied from FIG.
The frame timing signal FLM as shown in (A) is generated and supplied to the scan electrode driving circuit 5, the data reading circuit 3, and the frame number circuit 25. That is, the frame timing signal FLM is output when the displayed frame is switched. Here, the frame timing signal F
When LM is output, the counter value of the line counter 23 is reset and set to "0".

The FLM number circuit 25 sequentially selects the frame numbers 1 to 3 and supplies them to the selector 26 every time the frame timing signal FLM as shown in FIG. 2A supplied from the frame generation circuit 24 is supplied. . That is, the FLM number circuit 25 receives the frame numbers 1, 2, 3, 1, 2, 3, 1 ... each time the frame timing signal FLM is supplied.
... are sequentially supplied to the selector 26.

The selector 26 is responsive to the frame number supplied from the FLM number circuit 25 to select the time register T1.
Time data is selected from ~ T3 and the selected time data is supplied to the counter 22. That is, the selector 26
When the frame numbers 1, 2, 3 are supplied from the FLM number circuit 25, the counter 22 sets the time data stored in the time registers T1, T2, T3, respectively.

The time registers T1 to T3 are registers for storing time data of the selected time for driving the scan electrodes of each frame (frame numbers 1 to 3), and are associated with frame numbers 1, 2, 3 respectively. , Time register T1,
Time data is set in T2 and T3. The time registers T1 to T3 are selected by the selector 26 according to the frame number supplied from the frame number circuit 25. The time data set corresponding to this frame number becomes the drive time of one scan electrode in each frame.

The frame memory 4 has first, second and third frames.
3 frame memories, each of which stores data corresponding to a pixel of the liquid crystal display panel 7. This frame memory stores the display data of four gradations stored in an image memory (not shown) in three frame memories (first to third frame memories) in binary (1 bit) data unit. For example, as shown in FIG. 3, display data of four gradations (2 bits) of white, light grey, dark grey, and black as display colors is stored in each frame (first to third frames) for each pixel. The data is stored in binary (1 bit) data units, and the display data is combined and displayed with these three frames as one cycle.

The data read circuit 3 is supplied from the timing control circuit 2 with the scan timing signal CL1 as shown in FIG. 2B, the clock signal CL2 as shown in FIG. 2C, and the frame timing as shown in FIG. 2A. Corresponding frame memories 1 to 3 of the frame memory 4 according to the signal FLM.
The binary data is read out from and supplied to the signal electrode drive circuit 6.

Next, the operation of this liquid crystal drive circuit will be described. The description starts from the point where the frame timing signal FLM is output and the display is switched to frame 1 (see FIG. 2).

When the frame timing signal FLM is output from the FLM generation circuit 24, the data read circuit 3 is switched to read data from the frame 1,
One line of display data (segment signal data) corresponding to the scan electrode X1 is sent to the signal electrode drive circuit 6 according to the clock CL2.

On the other hand, the FLM number circuit 25 includes a selector 26.
Since the frame number 1 is given to the counter, the time data stored in the time register T1 is set in the counter 23 via the selector 26. Then, the counter 22 outputs the scanning timing signal CL1 when counting the set time, and the output of the scanning timing signal CL1 causes the signal electrode driving circuit 6 to capture the display data of one line corresponding to the next scanning electrode X2. It will be. That is, the cycle of the scanning timing signal CL1 becomes one scanning time, and the output of the scanning timing signal CL1 specifies the timing of fetching the display data of the next one line.

When the display processing up to the scanning electrode Xm is performed in this way, a signal is output from the line counter 23 and F
The LM generation circuit 24 outputs the frame timing signal FLM. As a result, the display is switched to the frame 2 next, the time data of the time register T2 is set in the counter 22, and the display processing is performed on the data stored in the frame 2 by the same operation as described above.

Then, when the display of the frame 2 is completed, the display data of the frame 3 is similarly displayed based on the storage time of the time register T3. When the display of the frame 3 is finished, the process returns to the frame 1 and these processes are repeated thereafter.

As described above, in the present embodiment,
In a liquid crystal drive circuit that performs gradation display by the frame thinning method, display data is stored in a plurality of frame memories in binary data units, and time data corresponding to each frame is stored in a time register to display each frame. In doing so, the scan electrodes are driven for a selection time corresponding to this time data, and gradation display according to the display data is performed with a plurality of frames as one cycle.

As a result, the selection time per pixel of each frame in the frame thinning method can be controlled,
By setting an appropriate selection time for each frame,
It is possible to avoid the phenomenon that the difference in brightness between the gradations due to the nonlinear characteristics of the driving effective voltage of the liquid crystal and the light transmittance becomes small, and it is possible to display an appropriate gradation.

In the above embodiment, 3 frames are used as one cycle to display the display data of 4 gradations, but the present invention is not limited to this.
In order to display display data of 8 gradations or 16 gradations, 7
Frames or 15 frames may be displayed as one cycle.

In the above embodiment, the STN liquid crystal is used as the liquid crystal, but the present invention is not limited to this, and for example, TN (Twisted Nematic) liquid crystal may be used.

Further, in the above-described embodiment, an example of monochrome display has been described, but it goes without saying that the present invention is also applicable to color display.

Further, in the above-mentioned embodiment, a temperature detecting means may be further provided to automatically correct the temperature change of the light transmittance of the liquid crystal.

[0043]

According to the liquid crystal drive device of the first aspect,
In a liquid crystal driving device that performs gradation display by the frame thinning control method, display data is stored in a plurality of frame memories, and time data corresponding to each frame is stored. The scanning electrode is selected for a time corresponding to. as a result,
It becomes possible to control the selection time per pixel of each frame in the frame thinning method, and by setting an appropriate selection time for each frame, the brightness between gradations due to the nonlinear characteristics of the liquid crystal drive effective voltage and light transmittance can be controlled. It is possible to avoid the phenomenon that the difference between the two becomes small, and it is possible to display an appropriate gradation.

According to the liquid crystal driving device of the second aspect, in addition to the effect of the first aspect of the invention, it is possible to perform proper liquid crystal gradation display with a simple circuit configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a liquid crystal drive circuit according to an embodiment.

FIG. 2 is a timing chart of signals at various parts of the liquid crystal drive circuit of FIG.

FIG. 3 is a combination diagram of each frame when performing 4-gradation display.

FIG. 4 is a diagram showing transmitted light characteristics with respect to a driving effective voltage of liquid crystal.

[Explanation of symbols]

 1 Liquid Crystal Driving Device 2 Timing Generating Circuit 21 Timing Signal Generating Circuit 22 Line Counter 24 FLM Generating Circuit 25 FLM Number Circuit 26 Selector T1 Time Register T2 Time Register T3 Time Register 3 Data Reading Circuit 4 Frame Memory 5 Scan Electrode Driving Circuit 6 Signal Electrode Drive circuit 7 Liquid crystal display panel

Claims (2)

[Claims] 1. A liquid crystal display panel is driven by a scanning signal and a display signal, a predetermined number of frames is set as one cycle, and the display of the display data is reduced by thinning out the display of the frame corresponding to the number of display gradations of the display data for each cycle. A liquid crystal drive circuit for performing gradation display, comprising a plurality of frame memories for storing display data for display signals, time data storage means for storing time data corresponding to each frame, and the time data storage means. A liquid crystal drive circuit, comprising: timing control means for controlling a scanning signal generation timing at the time of displaying each frame based on the stored time data. 2. A scan which outputs a scan timing signal every time the time data stored in the time data storage means is set and the time data is down-counted and counted by a predetermined number. Timing signal generation means, frame number designating means for designating a frame number by counting the scanning timing signal, and time data corresponding to the frame number designated by the frame number designating means, selected from the time data storage means. 2. The liquid crystal drive circuit according to claim 1, further comprising: time data setting means for setting the scanning timing signal generating means in the scanning timing signal generating means.