JPH09244053A - Production of liquid crystal display device and liquid crystal display device - Google Patents

Production of liquid crystal display device and liquid crystal display device

Info

Publication number
JPH09244053A
JPH09244053A JP5168496A JP5168496A JPH09244053A JP H09244053 A JPH09244053 A JP H09244053A JP 5168496 A JP5168496 A JP 5168496A JP 5168496 A JP5168496 A JP 5168496A JP H09244053 A JPH09244053 A JP H09244053A
Authority
JP
Japan
Prior art keywords
substrate
liquid crystal
display device
crystal display
conductive adhesive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5168496A
Other languages
Japanese (ja)
Inventor
Kazuhiro Matsumoto
一宏 松本
Atsushi Hanari
淳 羽成
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP5168496A priority Critical patent/JPH09244053A/en
Publication of JPH09244053A publication Critical patent/JPH09244053A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/12Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
    • H05K3/1241Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by ink-jet printing or drawing by dispensing
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/36Assembling printed circuits with other printed circuits
    • H05K3/368Assembling printed circuits with other printed circuits parallel to each other

Landscapes

  • Liquid Crystal (AREA)

Abstract

PROBLEM TO BE SOLVED: To inexpensively produce a liquid crystal display device which is small in size and has high image quality and high reliability while having a large capacity by alternately superposing substrates formed with wiring patterns at both ends and spacers to form a laminate and applying a conductive adhesive on this laminate. SOLUTION: The array substrates 2 formed with electrodes consisting of ITO, TFTs, etc., and the hollow spacers 17 having approximately the same outer peripheries as the outer peripheries of the array substrates 2 are alternately superposed on each other to form the laminate 18. Next, the conductive adhesive 31 is dropped on the connecting positions of the lead lines and branch lines of the array substrates 2 by a dispenser 20 while the laminate 18 is moved back and forth in a lamination direction. As a result, the required number of pieces of the line-like conductive adhesives 21 of the min. width of 110μm are acquired on the laminate 18. The spacers 17 are thereafter removed from the laminate 18 and the array substrates 2 are heated to thermoset the conductive adhesives 21, by which the adhesive parts are formed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、液晶表示装置に係
り、特に基板の額縁領域に設けられる配線パターンの接
続部を改良する液晶表示装置の製造方法及び液晶表示装
置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a method of manufacturing a liquid crystal display device and a liquid crystal display device for improving a connection portion of a wiring pattern provided in a frame region of a substrate.

【0002】[0002]

【従来の技術】近年、大容量且つ高速性、高精細を得る
液晶表示装置の実用化に伴い、ガラス基板上にマトリク
状に配列される薄膜トランジスタ(以下TFTと略称す
る。)を駆動素子とする液晶表示装置(以下TFT−L
CDと略称する。)が用いられ、最近では対角10イン
チクラス以上の大型のTFT−LCDが実用化されてい
る。
2. Description of the Related Art In recent years, with the practical use of a liquid crystal display device having a large capacity, high speed and high definition, thin film transistors (hereinafter abbreviated as TFT) arranged in a matrix on a glass substrate are used as driving elements. Liquid crystal display device (hereinafter TFT-L
Abbreviated as CD. ) Is used, and recently, a large TFT-LCD having a diagonal size of 10 inches or more has been put into practical use.

【0003】このTFT−LCDにあっては、従来よ
り、TFTを駆動するための液晶駆動用半導体集積回路
素子(以下ドライバICと略称する。)の実装に、80
μmピッチ程度の狭ピッチでの接続が可能であり、実装
領域の縮小化を図れる、TAB(Tape−Autom
ated−Bonding)が多用されていた。
In this TFT-LCD, a liquid crystal driving semiconductor integrated circuit element (hereinafter referred to as a driver IC) for driving the TFT has been conventionally mounted in 80.
TAB (Tape-Autom) that enables connection at a narrow pitch of about μm pitch and can reduce the mounting area.
aged-bonding) was frequently used.

【0004】しかしながら、TFT−LCDのより一層
の大型化に伴う多画素化により、駆動用信号線が増大す
る傾向にあり、ドライバICの入出力端子も300端子
以上と、多端子化する傾向にあった。このため、これ等
多端子のドライバICをTAB化すると、TABテープ
が幅広となるが、TABテープは幅広になれば成るほど
テープ精度の面から作成が困難になると共に、TABの
接続ピッチの微細化にも限界を生じ、ひいては実装領域
が増大され大容量TFT−LCDの小型化の妨げとなっ
ていた。
However, due to the increase in the number of pixels associated with the further increase in size of the TFT-LCD, the number of driving signal lines tends to increase, and the number of input / output terminals of the driver IC tends to increase to 300 terminals or more. there were. For this reason, if a TAB is used for a multi-terminal driver IC, the width of the TAB tape becomes wider. However, the wider the TAB tape becomes, the more difficult it is to make the tape in terms of tape accuracy and the finer the TAB connection pitch. There is a limit to the size reduction, and the mounting area is increased, which hinders the miniaturization of the large capacity TFT-LCD.

【0005】これに対し、ドライバICをICチップの
まま直接基板上に搭載するチップオングラス(COG)
と呼ばれる実装方式が開発されている。このCOGは
実装面積がドライバICの大きさである事から、TAB
に比し基板上の表示領域周囲の額縁領域をより縮小出来
ると共に、テープキャリア等の部材を必要としない事か
ら、TABに比し低コスト化を図れるという利点を有し
ている。
On the other hand, a chip-on-glass (COG) in which a driver IC is directly mounted on a substrate as an IC chip
The implementation method called is developed. The COG is,
Since the mounting area is the size of the driver IC, TAB
In comparison with TAB, the frame area around the display area on the substrate can be further reduced, and since members such as a tape carrier are not required, the cost can be reduced as compared with TAB.

【0006】このCOGにあっては、ドライバICへの
配線をフレキシブル・プリント基板(FPC)等の外部
基板に行なう場合と、ガラス基板上に直接行なう場合と
あるが、前者にあっては外部基板を必要とする上に、ガ
ラス基板と外部基板との接続が必要とされ、コストが増
大すると共に、外部基板を配置する分、額縁領域が拡大
され小型化が妨げられるという問題を有している。一方
後者にあっては、従来ガラス基板上に薄膜フォトリソグ
ラフィ技術を用いて行なっていた画素部のTFT製造工
程と同時に、ドライバICへの配線を高精細に形成出来
る事から、コストの増大を押さえられると共に、配線領
域も小さくて済むという利点を有している。
In this COG, wiring to the driver IC may be performed on an external substrate such as a flexible printed circuit (FPC) or directly on a glass substrate. In the former case, the external substrate is used. In addition to the above, the glass substrate and the external substrate are required to be connected to each other, resulting in an increase in cost and a problem that the frame region is enlarged and the miniaturization is prevented because the external substrate is arranged. . On the other hand, in the latter case, the wiring to the driver IC can be formed with high precision at the same time as the TFT manufacturing process of the pixel portion, which is conventionally performed by using the thin film photolithography technique on the glass substrate, so that the cost increase can be suppressed. In addition, there is an advantage that the wiring area can be small.

【0007】しかしながら、後者のガラス基板上への配
線は、膜厚が1μm以下と非常に薄いため、配線抵抗が
大きくなり、ドライバICに誤動作を生じ、表示むらや
階調不良を生じてしまい、特に大型のTFT−LCDに
あっては配線抵抗の増大による画質の劣化が顕著となる
という新たな問題を生じていた。
However, since the latter wiring on the glass substrate has a very thin film thickness of 1 μm or less, the wiring resistance becomes large, the driver IC malfunctions, and the display unevenness and the gradation defect occur. Particularly in a large TFT-LCD, there is a new problem that the deterioration of image quality due to an increase in wiring resistance becomes remarkable.

【0008】このため例えば、特開平5−5900号公
報に開示されるように、ガラス基板の一方の面にドライ
バICを搭載し、この搭載面の反対面にバスラインを形
成し、額縁領域を増大する事なく配線幅の拡大を図り、
配線抵抗を低減する装置の開発も成されている。そして
この様な装置にあっては、ガラス基板のドライバIC搭
載面に配線されるリード線と反対面に配線されるバスラ
インとの接続部の信頼性が要求されるが、実際にはこれ
等リード線とバスラインとを接続するため、ガラス基板
1枚毎に、ディスペンサにより、その側面に導電性接着
剤を塗布していた。
Therefore, for example, as disclosed in Japanese Patent Laid-Open No. 5900/1993, a driver IC is mounted on one surface of a glass substrate, a bus line is formed on the surface opposite to the mounting surface, and a frame region is formed. The wiring width is expanded without increasing,
A device for reducing wiring resistance has also been developed. In such a device, the reliability of the connecting portion between the lead wire wired on the driver IC mounting surface of the glass substrate and the bus line wired on the opposite surface is required. In order to connect the lead wire and the bus line, a conductive adhesive was applied to the side surface of each glass substrate by a dispenser.

【0009】[0009]

【発明が解決しようとする課題】しかしながらガラス基
板1枚毎に導電性接着剤を塗布し、ガラス基板両面に形
成される配線を電気的に接続する方法にあっては、ガラ
ス基板毎に導電性接着剤の塗布量が異なり、導電性接着
剤が切れたり膜厚が不均一となり、配線抵抗にばらつき
を生じ画質が体かされたりひいては、導通不能になると
いう問題を有していた。しかも導電性接着剤の塗布に時
間を要し、ひいてはコスト上昇を招くという問題も生じ
ていた。
However, in the method of applying the conductive adhesive to each glass substrate and electrically connecting the wirings formed on both surfaces of the glass substrate, the conductivity of each glass substrate is increased. There is a problem that the coating amount of the adhesive is different, the conductive adhesive is cut off or the film thickness becomes non-uniform, the wiring resistance varies, the image quality is deteriorated, and the electrical continuity becomes impossible. Moreover, there is a problem in that it takes time to apply the conductive adhesive, which eventually leads to an increase in cost.

【0010】そこで本発明は上記課題を除去するもの
で、ガラス基板両面に形成される配線パターンを、電気
的に確実且つ均一に接続すると共に、製造コストの低減
を図る事により、大容量でありながら小型且つ高画質で
信頼性の高い液晶表示装置を安価に製造する事を目的と
する。
Therefore, the present invention eliminates the above-mentioned problems and provides a large capacity by electrically and reliably connecting wiring patterns formed on both surfaces of a glass substrate and reducing the manufacturing cost. However, it is an object of the present invention to manufacture a liquid crystal display device that is small in size, high in image quality, and highly reliable at low cost.

【0011】[0011]

【課題を解決するための手段】本発明は上記課題を解決
するために、電極を有し液晶組成物を挾持する一対の基
板と、この一対の基板の少なくとも一方の基板の両面に
形成される配線パターンと、この配線パターンを有する
基板側面に設けられ前記基板の両面に形成される配線パ
ターンを電気的に接続する接続手段とを具備する液晶表
示装置の製造方法において、前記基板及び、外周が前記
基板と同一又は前記基板より若干小さいスペーサを交互
に複数枚重ねて積層体を形成する工程と、導電性接着剤
を、前記積層体の積層方向にライン状に滴下し前記基板
側面に前記接続手段を形成する工程と、を実施するもの
である。
In order to solve the above problems, the present invention is formed on a pair of substrates having electrodes and holding a liquid crystal composition, and on both surfaces of at least one of the substrates. In a method of manufacturing a liquid crystal display device, comprising: a wiring pattern; and a connecting means which is provided on a side surface of the substrate having the wiring pattern and electrically connects the wiring patterns formed on both surfaces of the substrate, Forming a laminated body by alternately stacking a plurality of spacers which are the same as or slightly smaller than the substrate, and a conductive adhesive is dropped linearly in the laminating direction of the laminated body to connect to the side surface of the substrate. And a step of forming means.

【0012】又本発明は上記課題を解決するために、電
極を有し液晶組成物を挾持する一対の基板と、この一対
の基板の少なくとも一方の基板の両面に形成される配線
パターンと、この配線パターンを有する前記基板及び、
外周が前記基板と同一又は前記基板より少し小さいスペ
ーサを、交互に複数枚重ね合わせ積層体を形成し、前記
積層体の積層方向に導電性接着剤或いは熱硬化型導電性
接着剤をライン状に滴下してなり、前記基板側面にて前
記基板の両面に形成される配線パターンを電気的に接続
する接続手段と、を設けるものである。
In order to solve the above problems, the present invention provides a pair of substrates having electrodes and holding a liquid crystal composition, a wiring pattern formed on both surfaces of at least one of the substrates, The substrate having a wiring pattern,
A plurality of spacers whose outer circumference is the same as or slightly smaller than that of the substrate are alternately stacked to form a laminated body, and a conductive adhesive or a thermosetting conductive adhesive is linearly formed in the laminating direction of the laminated body. Connection means for electrically connecting wiring patterns formed on both sides of the substrate on the side surface of the substrate.

【0013】そしてこの様な構成により本発明は、基板
両面に形成される配線パターンを基板側面にて接続する
ための導電性接着剤を、均一且つ高速に形成する事によ
り、両配線パターン間に断線を生じたり、配線抵抗のば
らつきを生じる事がなく、大容量でありながら高精細な
画質を有する液晶表示装置の小型化を図り且つ安価に製
造可能とするものである。
According to the present invention having such a structure, the conductive adhesive for connecting the wiring patterns formed on both sides of the substrate on the side surfaces of the substrate is formed uniformly and at high speed so that the wiring patterns can be formed between both wiring patterns. It is possible to reduce the size of a liquid crystal display device having a large capacity and a high definition image quality and to be manufactured at low cost without causing disconnection or variation in wiring resistance.

【0014】[0014]

【発明の実施の形態】以下、本発明の第1の実施の形態
を図1乃至図6を参照して説明する。図1は、TFT
(図示せず)がマトリクス状に配列されるアレイ基板2
と対向基板3間に液晶組成物4を有してなる液晶表示装
置1の平面図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. Figure 1 shows a TFT
Array substrate 2 in which (not shown) are arranged in a matrix
FIG. 3 is a plan view of a liquid crystal display device 1 including a liquid crystal composition 4 between a substrate 3 and a counter substrate 3.

【0015】アレイ基板2の表示領域[A]周囲の額縁
領域[B]の第1面2aには、フェースダウン方式にて
実装されるドライバIC6への入力を行なう配線パター
ンであるリード線7がフォトリソグラフィ技術により配
線され、ドライバIC6の搭載面と反対面である額縁領
域[B]の第2面2bには、フレキシブルプリント基板
9により外部からの制御信号が入力される配線パターン
であるバスライン8及びその分岐線8aがフォトリソグ
ラフィ技術により配線されている。このバスライン8と
分岐線8aとの間には絶縁膜10が成膜され、絶縁膜1
0に設けられるビアホール10aを介して電気的に接続
している。
On the first surface 2a of the frame area [B] around the display area [A] of the array substrate 2, the lead wire 7 which is a wiring pattern for inputting to the driver IC 6 mounted by the face-down method is provided. A bus line, which is a wiring pattern to which a control signal from the outside is input by the flexible printed board 9, is provided on the second surface 2b of the frame area [B] which is the surface opposite to the mounting surface of the driver IC 6 and which is wired by the photolithography technique. 8 and its branch line 8a are wired by the photolithography technique. An insulating film 10 is formed between the bus line 8 and the branch line 8a.
They are electrically connected via a via hole 10a provided at 0.

【0016】尚リード線7及びバスライン8等の配線は
アルミニウム(Al)やIndium−Tin−Oxi
de(以下ITOと略称する。)等からなり、その配線
本数は、例えば、ドライバIC6が256階調であると
すると、各画素のRGB階調データとして24本(8×
3本)、クロックやコントロール信号として約5本、中
間調補正用基準電圧として約9本必要で、更に電源・グ
ランドを加えると、合計約40本となる。更に11はT
FTの走査線端子であり、12はTFTの信号線端子で
ある。
The wires such as the lead wire 7 and the bus line 8 are made of aluminum (Al) or Indium-Tin-Oxi.
de (hereinafter abbreviated as ITO) or the like, and the number of wirings thereof is, for example, assuming that the driver IC 6 has 256 gradations, 24 (8 × 8 × 8) RGB gradation data of each pixel.
3), about 5 clocks and control signals, and about 9 reference voltages for halftone correction are required. If power and ground are added, the total will be about 40. 11 is T
Reference numeral 12 is a scanning line terminal of the FT, and 12 is a signal line terminal of the TFT.

【0017】又、ドライバIC6は、リード線7とバン
プ13aを介して接続され、走査線端子11及び信号線
端子12とバンプ13bを介して接続されている。尚各
バンプ13a、13bと、配線7、11、12との接続
は、異方性導電膜(ACF)を用いたり、ハンダ等を溶
融したり、金属間の固相接合を用いる等して行なってい
る。
The driver IC 6 is connected to the lead wire 7 via the bump 13a, and is connected to the scanning line terminal 11 and the signal line terminal 12 via the bump 13b. The bumps 13a and 13b are connected to the wirings 7, 11 and 12 by using an anisotropic conductive film (ACF), melting solder or the like, or solid phase bonding between metals. ing.

【0018】そして額縁領域[B]の第1面2aに形成
されるリード線7端部7bと、第2面2bに形成される
バスライン8の分岐線8a端部8bは図3に示すように
幅広に形成され、アレイ基板2側面に設けられる導電性
接着剤であり銀(Ag)、ニッケル(Ni)、金(A
u)等の導電性微小粒子を混合したエポキシ樹脂からな
る熱硬化型の導電性接着剤21から形成される接着部1
6により導通されている。
The end portion 7b of the lead wire 7 formed on the first surface 2a of the frame area [B] and the end portion 8b of the branch line 8a of the bus line 8 formed on the second surface 2b are shown in FIG. Is a conductive adhesive that is formed wide on the side surface of the array substrate 2 and is silver (Ag), nickel (Ni), gold (A).
u) Adhesive part 1 formed from thermosetting conductive adhesive 21 made of epoxy resin mixed with conductive fine particles
6 is conducted.

【0019】次にアレイ基板2の接着部16の製造方法
について述べる。先ず、ITOからなる電極、TFT及
びその配線11、12と共に、リード線7、バスライン
8及びその分岐線8aが形成されたアレイ基板2と、こ
のアレイ基板2と略同じ外周を有する中空のスペーサ1
7とを交互に重ねて、積層体18を形成する。次に積層
体18を積層方向に往復動する間に、ディスペンサ20
により、アレイ基板2のリード線7と分岐線8aの接続
位置上に導電性接着剤21を滴下する。これにより積層
体18上に最少100μm幅のライン状の導電性接着剤
21が必要本数取着される。
Next, a method of manufacturing the adhesive portion 16 of the array substrate 2 will be described. First, an array substrate 2 on which an electrode made of ITO, a TFT and wirings 11 and 12 thereof, a lead wire 7, a bus line 8 and a branch line 8a thereof are formed, and a hollow spacer having a substantially same outer periphery as the array substrate 2 1
7 are alternately stacked to form a laminated body 18. Next, while reciprocating the laminated body 18 in the laminating direction, the dispenser 20
Thus, the conductive adhesive 21 is dropped on the connection position of the lead wire 7 and the branch wire 8a of the array substrate 2. As a result, the required number of line-shaped conductive adhesives 21 having a minimum width of 100 μm are attached onto the laminate 18.

【0020】この後、積層体18からスペーサ17を抜
き取り、アレイ基板2を加熱し、導電性接着剤21を熱
硬化させ接着部16を形成する。一方、スペーサ17
は、再使用のためエタノール等により接着部16を洗浄
される。
After this, the spacers 17 are removed from the laminated body 18, the array substrate 2 is heated, and the conductive adhesive 21 is thermally cured to form the adhesive portion 16. On the other hand, the spacer 17
The adhesive 16 is washed with ethanol or the like for reuse.

【0021】この様に構成すれば、1度の塗布工程によ
り、複数個のアレイ基板2に接着部16を均一かつ高速
に塗布出来、リード線7及び分岐線8a間に、断線を生
じたり、配線抵抗にばらつきを生じる事の無い良好な接
続を得られ、大容量でありながら額縁領域が小さく、高
精細な画質を有する液晶表示装置を得られる。しかも接
着部16を大量に一括生産出来、形成時間の短縮を図れ
る事からアレイ基板2製造時の、製造コストも低減され
る。
According to this structure, the adhesive portions 16 can be applied uniformly and at high speed to the plurality of array substrates 2 by a single applying process, and disconnection may occur between the lead wire 7 and the branch wire 8a. It is possible to obtain a good connection without variation in wiring resistance, and to obtain a liquid crystal display device having a large capacity, a small frame area, and high definition image quality. Moreover, since the adhesive portions 16 can be mass-produced in a large amount and the formation time can be shortened, the manufacturing cost at the time of manufacturing the array substrate 2 is also reduced.

【0022】次に本発明の第2の実施の形態を説明す
る。尚この第2の実施の形態は、第1の実施の形態にお
ける積層体18への接着部16の塗布をディスペンサに
て行なうこと無く、スクリーン印刷法により行なうもの
であり、他は第1の実施の形態と同様とするものであ
り、第1の実施の形態と同一部分については同一符号を
付しその説明を省略する。即ちこの第2の実施の形態に
あっては、アレイ基板2及びスペーサ17を交互に重ね
た積層体18形成後、積層体18側面にパターニングさ
れたマスク上から導電性接着剤21を印刷塗布し、更に
アレイ基板2を加熱し導電性接着剤21を硬化させ接着
部16を形成するものである。
Next, a second embodiment of the present invention will be described. In the second embodiment, the application of the adhesive portion 16 to the laminated body 18 according to the first embodiment is performed by a screen printing method without using a dispenser, and the others are performed in the first embodiment. The same parts as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted. That is, in the second embodiment, after forming the laminated body 18 in which the array substrate 2 and the spacer 17 are alternately stacked, the conductive adhesive 21 is applied by printing on the patterned mask on the side surface of the laminated body 18. Further, the array substrate 2 is further heated to cure the conductive adhesive 21 to form the adhesive portion 16.

【0023】このように構成すれば第1の実施の形態と
同様、リード線及び分岐線8aを均一高精細かつ高速に
て接続導通出来る。
With this structure, as in the first embodiment, the lead wire and the branch wire 8a can be connected and conducted uniformly with high precision and at high speed.

【0024】次に本発明の第3の実施の形態を図7を用
いて説明する。第3の実施の形態は、第1の実施の形態
におけるスペーサ17の形状が異なるものの、他は第1
の実施の形態と同様とするものであり、第1の実施の形
態と同一部分については同一符号を付しその説明を省略
する。
Next, a third embodiment of the present invention will be described with reference to FIG. In the third embodiment, the shape of the spacer 17 in the first embodiment is different, but the others are the first.
The same parts as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted.

【0025】即ちこの第3の実施の形態にあっては、デ
ィスペンサ20に滴下される導電性接着剤21の幅を規
制するため、アレイ基板2と交互に積層するスペーサ2
2の側面に接着部16と同等幅の切り欠き22aを形成
するものである。
That is, in the third embodiment, in order to regulate the width of the conductive adhesive 21 dropped on the dispenser 20, the spacers 2 alternately stacked with the array substrate 2 are arranged.
The notch 22a having the same width as that of the adhesive portion 16 is formed on the side surface of No. 2.

【0026】この様なスペーサ22を用い積層体23に
導電性接着剤21をライン状に滴下すると、スペーサ2
2の切り欠き22aがマスクの作用をし、アレイ基板2
側面での導電性接着剤21のはみだしが無くなり、接着
部16の均一性がより向上され、リード線及び分岐線8
aの接続精度がより向上される。
When the conductive adhesive 21 is dropped in a line on the laminate 23 using the spacer 22 as described above, the spacer 2
The two notches 22a act as a mask, and the array substrate 2
The protrusion of the conductive adhesive 21 on the side surface is eliminated, the uniformity of the adhesive portion 16 is further improved, and the lead wire and the branch wire 8 are provided.
The connection accuracy of a is further improved.

【0027】次に本発明の第4の実施の形態を図8を用
いて説明する。第4の実施の形態は、第1の実施の形態
におけるアレイ基板2側面の接着部16形成部分に接着
部16と同等幅の突起24を設けるものであり、第1の
実施の形態と同一部分については同一符号を付しその説
明を省略する。
Next, a fourth embodiment of the present invention will be described with reference to FIG. In the fourth embodiment, a protrusion 24 having the same width as that of the adhesive portion 16 is provided in the portion where the adhesive portion 16 is formed on the side surface of the array substrate 2 in the first embodiment, and the same portion as that of the first embodiment. Are denoted by the same reference numerals, and description thereof will be omitted.

【0028】即ち突起24を有するアレイ基板2と、ス
ペーサ17とを交互に重ねて積層体26を形成し、この
積層体26を往復移動する間に、突起24位置にて導電
性接着剤21をライン状に滴下し、更にアレイ基板2を
加熱して導電性接着剤21を加熱硬化して接続部16を
形成するものである。
That is, the array substrate 2 having the projections 24 and the spacers 17 are alternately stacked to form a laminated body 26, and the conductive adhesive 21 is applied at the positions of the protrusions 24 while reciprocating the laminated body 26. It is dropped in a line shape, and the array substrate 2 is further heated to heat and cure the conductive adhesive 21 to form the connection portion 16.

【0029】このように構成すれば、接着部16の均一
性がより向上され、リード線及び分岐線8aの接続を確
実にしかも高精度に行なえる。
According to this structure, the uniformity of the adhesive portion 16 is further improved, and the lead wire and the branch wire 8a can be connected reliably and highly accurately.

【0030】次に本発明の第5の実施の形態を図9及び
図10を用いて説明する。第5の実施の形態は、第1の
実施の形態におけるバスライン8及び分岐線8aをアレ
イ基板2の額縁領域[B]の第1面27aに設けるもの
であり、第1の実施の形態と同一部分については同一符
号を付しその説明を省略する。
Next, a fifth embodiment of the present invention will be described with reference to FIGS. 9 and 10. In the fifth embodiment, the bus line 8 and the branch line 8a in the first embodiment are provided on the first surface 27a of the frame region [B] of the array substrate 2, which is different from the first embodiment. The same parts are designated by the same reference numerals and the description thereof will be omitted.

【0031】即ちアレイ基板27は、その額縁領域
[B]の第1面27aにバスライン28及び分岐線28
aを配線し、更にバスライン28のうちの特に低抵抗化
が要求される電源系等の配線に対して、額縁領域[B]
の第2面27bに低抵抗化するための補助配線30を形
成してなるものである。そしてこの様なアレイ基板27
とスペーサ17とを交互に重ねた積層体(図示せず)を
形成し、この積層体を往復移動する間に、アレイ基板2
7の分岐線28aと補助配線30の接続位置上に導電性
接着剤(図示せず)をライン状に滴下し、更にアレイ基
板27を加熱し、分岐線28aと補助配線30とを導通
する接続部31を形成するものである。
That is, the array substrate 27 has the bus line 28 and the branch line 28 on the first surface 27a of the frame region [B].
In addition, the frame region [B] is provided for the wiring of the power supply system or the like, in which the wiring line a is further wired and the resistance of the bus line 28 is particularly required to be low.
The auxiliary wiring 30 for reducing the resistance is formed on the second surface 27b. And such an array substrate 27
And a spacer 17 are alternately stacked to form a laminated body (not shown), and while the laminated body is reciprocally moved, the array substrate 2
A conductive adhesive (not shown) is linearly dropped on the connection position between the branch line 28a and the auxiliary wiring 30 of No. 7, and the array substrate 27 is further heated to connect the branch line 28a and the auxiliary wiring 30. The part 31 is formed.

【0032】このように構成すれば、分岐線28aと補
助配線30とを接続部31にて均一高精細に接続可能で
ある事から、例えば補助配線30が電源線を低抵抗化す
るための電源配線であるとすると、補助配線30を第2
面27bに設ける事により額縁領域[B]を増大する事
無くドライバIC6に供給される電源の電源線の配線抵
抗による電圧降下を縮小出来、ドライバIC6の誤動作
を防止出来、しかも補助配線30が幅広に配線可能であ
る事から、インダクタンスが小さくなり、電源系統の誘
導性ノイズの低減も図れ、高精細で良好な画像を得られ
る。
According to this structure, the branch line 28a and the auxiliary wiring 30 can be uniformly and precisely connected at the connecting portion 31, so that the auxiliary wiring 30 can be used as a power source for reducing the resistance of the power source line. If it is wiring, the auxiliary wiring 30
By providing the surface 27b, the voltage drop due to the wiring resistance of the power supply line of the power supply supplied to the driver IC 6 can be reduced without increasing the frame area [B], the malfunction of the driver IC 6 can be prevented, and the auxiliary wiring 30 is wide. Since it can be wired, the inductance is reduced, the inductive noise of the power supply system can be reduced, and a high-definition and good image can be obtained.

【0033】次に本発明の第6の実施の形態を図11及
び図12を用いて説明する。第6の実施の形態は第5の
実施の形態と同様、第1の実施の形態におけるバスライ
ン8及び分岐線8aをアレイ基板2の額縁領域[B]の
第1面2aに設けるものであり、第1の実施の形態及び
第5の実施の形態と同一部分については同一符号を付し
その説明を省略する。
Next, a sixth embodiment of the present invention will be described with reference to FIGS. 11 and 12. In the sixth embodiment, as in the fifth embodiment, the bus line 8 and the branch line 8a in the first embodiment are provided on the first surface 2a of the frame region [B] of the array substrate 2. The same parts as those in the first and fifth embodiments are designated by the same reference numerals and the description thereof will be omitted.

【0034】即ちアレイ基板27の額縁領域[B]の第
1面27aにバスライン28及び分岐線28aを配線
し、更にバスライン28のうちの特に低抵抗化を要求さ
れる補助電源配線32を額縁領域[B]の第2面27b
に形成すると共に、補助グランド配線33を形成し、電
源デカップリング用のコンデンサ34を搭載している。
そしてアレイ基板27とスペーサ17とを交互に重ねた
積層体(図示せず)を往復移動する間に、アレイ基板2
7の分岐線28aと補助電源配線32或いは補助グラン
ド配線33とを接続する位置にて導電性接着剤(図示せ
ず)をライン状に滴下し、更にアレイ基板27を加熱
し、分岐線28aと補助電源配線32或いは補助フラン
ド配線33とを導通する接続部36を形成するものであ
る。
That is, the bus line 28 and the branch line 28a are wired on the first surface 27a of the frame region [B] of the array substrate 27, and the auxiliary power supply wiring 32 of the bus line 28 which is required to have a particularly low resistance. Second surface 27b of frame area [B]
In addition to the above, the auxiliary ground wiring 33 is formed and the capacitor 34 for power supply decoupling is mounted.
The array substrate 2 and the spacer 17 are alternately stacked while the laminate (not shown) is reciprocally moved.
A conductive adhesive (not shown) is linearly dropped at a position where the branch line 28a of 7 and the auxiliary power supply line 32 or the auxiliary ground line 33 are connected, and the array substrate 27 is further heated to form the branch line 28a. The connection portion 36 is formed to conduct the auxiliary power supply wiring 32 or the auxiliary ground wiring 33.

【0035】このように構成すれば、分岐線28aと補
助電源配線32或いは補助グランド配線33とを接続部
36にて均一高精細に接続可能であり、更にコンデンサ
34を第2面27bに設ける事により、額縁領域[B]
の第1面27aにおけるコンデンサ34用のスペースが
不要となり、額縁領域[B]の小型化或いは、第1面2
7a上の他の配線の幅の拡大が可能となる。又、第2面
27bにて幅広に形成される補助電源配線32にコンデ
ンサ34を搭載する事により、電源系のインピーダンス
をより低減出来、耐ノイズ性の向上により良好な画像を
得られる。
According to this structure, the branch line 28a and the auxiliary power supply wiring 32 or the auxiliary ground wiring 33 can be uniformly and precisely connected at the connecting portion 36, and the capacitor 34 is provided on the second surface 27b. The frame area [B]
The space for the capacitor 34 on the first surface 27a of the first surface 27a is unnecessary, and the frame area [B] can be downsized, or
It is possible to increase the width of other wiring on 7a. Further, by mounting the capacitor 34 on the auxiliary power supply wiring 32 formed wide on the second surface 27b, the impedance of the power supply system can be further reduced, and a good image can be obtained by improving the noise resistance.

【0036】次に本発明の第7の実施の形態を図13を
用いて説明する。第7の実施の形態は第5の実施の形態
と同様、第1の実施の形態におけるバスライン8及び分
岐線8aをアレイ基板2の額縁領域[B]の第1面2a
に設けるものであり、第1の実施の形態及び第2の実施
の形態と同一部分については同一符号を付しその説明を
省略する。
Next, a seventh embodiment of the present invention will be described with reference to FIG. In the seventh embodiment, as in the fifth embodiment, the bus line 8 and the branch line 8a in the first embodiment are connected to the first surface 2a of the frame region [B] of the array substrate 2.
The same parts as those of the first and second embodiments are designated by the same reference numerals and the description thereof will be omitted.

【0037】即ちアレイ基板27の額縁領域[B]の第
1面27aに非透光性のアルミニウム(Al)からなる
バスライン28及び分岐線28aを配線し、更に額縁領
域[B]の第2面27bに低抵抗化するための補助配線
37を形成する。この補助配線37は第1面27aに搭
載されるドライバIC6の背面を被覆するよう幅広に形
成されている。この様な配線を有するアレイ基板27と
スペーサ17とを交互に重ねた積層体(図示せず)を往
復移動する間に、アレイ基板27の分岐線28aと補助
配線37を接続する位置にて導電性接着剤(図示せず)
をライン状に滴下し、更にアレイ基板27を加熱し、分
岐線28aと補助配線37とを導通する接続部38を形
成するものである。
That is, the bus line 28 and the branch line 28a made of non-translucent aluminum (Al) are laid on the first surface 27a of the frame region [B] of the array substrate 27, and the second line of the frame region [B] is further provided. An auxiliary wiring 37 for reducing the resistance is formed on the surface 27b. The auxiliary wiring 37 is formed wide so as to cover the back surface of the driver IC 6 mounted on the first surface 27a. While reciprocating a laminated body (not shown) in which the array substrate 27 and the spacers 17 having such wirings are alternately stacked, electrical conductivity is provided at a position where the branch line 28a of the array substrate 27 and the auxiliary wiring 37 are connected. Adhesive (not shown)
Is dropped in a line shape, and the array substrate 27 is further heated to form a connecting portion 38 for electrically connecting the branch line 28a and the auxiliary wiring 37.

【0038】このように構成すれば、分岐線28aと補
助配線37とを接続部38にて均一高精細かつ高速で接
続可能である事から、配線の低抵抗化にかかわらず容易
かつ低価格にて額縁領域[B]の小型化を図れる。又ド
ライバIC6の背面に非透光性の補助配線37が形成さ
れており、バックライト(図示せず)からの光がドライ
バIC6に直接入射しないので、ドライバIC6のしき
い値の変動を防止出来、より良好な駆動を得られる。
According to this structure, the branch line 28a and the auxiliary wiring 37 can be uniformly and precisely connected at the connecting portion 38 at high speed, so that the wiring can be easily and inexpensively regardless of the resistance of the wiring. As a result, the frame area [B] can be downsized. Further, since the non-translucent auxiliary wiring 37 is formed on the back surface of the driver IC 6 and the light from the backlight (not shown) does not directly enter the driver IC 6, it is possible to prevent the threshold value of the driver IC 6 from changing. , Better drive can be obtained.

【0039】次に本発明の第8の実施の形態を図14を
用いて説明する。第8の実施の形態は第5の実施の形態
と同様、第1の実施の形態におけるバスライン8及び分
岐線8aをアレイ基板2の額縁領域[B]の第1面2a
に設けるものであり、第1の実施の形態及び第5の実施
の形態と同一部分については同一符号を付しその説明を
省略する。
Next, an eighth embodiment of the present invention will be described with reference to FIG. In the eighth embodiment, as in the fifth embodiment, the bus lines 8 and the branch lines 8a in the first embodiment are connected to the first surface 2a of the frame region [B] of the array substrate 2.
The same parts as those of the first and fifth embodiments are designated by the same reference numerals and the description thereof will be omitted.

【0040】即ちアレイ基板27の額縁領域[B]の第
1面27aにバスライン28及び分岐線28aを配線
し、更に額縁領域[B]の第2面27bに低抵抗化する
ための補助配線40を形成する。この様な配線を有する
アレイ基板27とスペーサ17とを交互に重ねた積層体
(図示せず)を往復移動する間に、アレイ基板27の所
定位置にて導電性接着剤をライン状に滴下し、更にアレ
イ基板27を加熱し、分岐線28aと補助配線40とを
導通する接続部41を形成する。更にこの接続部41に
チップコンデンサ42を搭載するものである。
That is, the bus line 28 and the branch line 28a are wired on the first surface 27a of the frame area [B] of the array substrate 27, and the auxiliary wiring for lowering the resistance on the second surface 27b of the frame area [B]. 40 is formed. While reciprocating a laminate (not shown) in which the array substrate 27 having such wiring and the spacers 17 are alternately stacked, a conductive adhesive is dropped in a line at a predetermined position of the array substrate 27. Then, the array substrate 27 is further heated to form the connection portion 41 that electrically connects the branch line 28a and the auxiliary wiring 40. Further, a chip capacitor 42 is mounted on this connecting portion 41.

【0041】このように構成すれば、接続部41を電極
としてチップコンデンサ42をアレイ基板27側面に設
ける事により、額縁領域[B]の第1面27aにおける
コンデンサ34用のスペースが不要となり、額縁領域
[B]の小型化或いは、第1面27a上の他の配線の幅
の拡大が可能となる。しかも接続部41を均一高精細か
つ高速にて形成出来、製造コストの低減も実現される。
According to this structure, by providing the chip capacitor 42 on the side surface of the array substrate 27 with the connecting portion 41 as an electrode, the space for the capacitor 34 in the first surface 27a of the frame region [B] is unnecessary, and the frame is formed. It is possible to reduce the size of the region [B] or increase the width of other wiring on the first surface 27a. In addition, the connection portion 41 can be formed uniformly with high precision and at high speed, and the manufacturing cost can be reduced.

【0042】次に本発明の第9の実施の形態を図15及
び図16を用いて説明する。第9の実施の形態は、第1
の実施の形態における接着部16に加え、アレイ基板2
側面に、フレキシブルプリント基板9からの制御信号を
入力するための入力端子を設けるものであり、第1の実
施の形態と同一部分については同一符号を付しその説明
を省略する。
Next, a ninth embodiment of the present invention will be described with reference to FIGS. The ninth embodiment is the first embodiment.
In addition to the adhesive portion 16 in the embodiment, the array substrate 2
An input terminal for inputting a control signal from the flexible printed circuit board 9 is provided on the side surface. The same parts as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted.

【0043】即ちアレイ基板43の額縁領域[B]の第
1面43aにドライバIC44をCODにて実装すると
共に、リード線46を配線する一方、額縁領域[B]の
第2面43bにバスライン47及びリード線46に接続
する分岐線47aを配線する。このようにしてなるアレ
イ基板43とスペーサ(図示せず)とを交互に重ねた積
層体(図示せず)を往復移動する間に、アレイ基板43
のリード線46と分岐線47aとを接続する位置及び、
外部からの制御信号を入力するフレキシブルプリント基
板51を接続する位置にて導電性接着剤(図示せず)を
ライン状に滴下する。
That is, the driver IC 44 is mounted by COD on the first surface 43a of the frame area [B] of the array substrate 43, and the lead wire 46 is wired, while the bus line is formed on the second surface 43b of the frame area [B]. The branch line 47a connected to the lead wire 47 and the lead wire 46 is wired. While the array body 43 and the spacers (not shown) formed in this way are reciprocally moved in a laminated body (not shown) in which they are alternately stacked,
And a position for connecting the lead wire 46 and the branch wire 47a of
A conductive adhesive (not shown) is dropped linearly at a position where the flexible printed circuit board 51 for inputting a control signal from the outside is connected.

【0044】そしてスペーサを抜いた後、アレイ基板4
3を加熱し、リ−ド線46と分岐線47aとを導通する
接続部50を形成すると共に、フレキシブルプリント基
板51を接続する入力端子部52を形成した後、入力端
子部52にフレキシブルプリント基板51を取着するも
のである。
After removing the spacers, the array substrate 4
3 is heated to form the connecting portion 50 for electrically connecting the lead wire 46 and the branch wire 47a, and the input terminal portion 52 for connecting the flexible printed circuit board 51 is formed, and then the input terminal portion 52 is provided with the flexible printed circuit board. 51 is attached.

【0045】このように構成すれば、リード線46及び
分岐線47aとを接続部50にて均一高精細かつ高速に
て接続すると共に、均一高精細な入出力端子部52を同
一工程にて形成出来、製造工程及びコストの増加を生じ
る事無く、フレキシブルプリント基板51との接続端子
である入力端子部52を形成出来、フレキシブルプリン
ト基板51をアレイ基板43に取り付ける際の自由度が
増し、装置の小型化の実現がより容易とされる。
According to this structure, the lead wire 46 and the branch wire 47a are connected at the connection portion 50 at a uniform and high precision and at a high speed, and the uniform and fine input / output terminal portion 52 is formed in the same step. It is possible to form the input terminal portion 52 which is a connection terminal with the flexible printed circuit board 51 without increasing the manufacturing process and the cost, and the flexibility in mounting the flexible printed circuit board 51 on the array substrate 43 is increased. Realization of miniaturization is made easier.

【0046】尚本発明は上記実施の形態に限られるもの
ではなく、その趣旨を変えない範囲での変更は可能であ
って、例えば基板に形成される配線の材料や構造等限定
されず、ITOやアルミニウム(Al)からなる配線の
上にニッケル(Ni)、銅(Cu)、クロム(Cr)、
金(Au)等を積層し配線のより一層の体抵抗化を図る
等しても良い。又配線の本数や配線幅も任意である。
又、導電性接着剤の粘性及び積層体の移動速度等も、接
続手段の幅に応じて任意に選択可能である。
The present invention is not limited to the above-described embodiment, and modifications can be made without departing from the spirit of the invention. For example, the material and structure of the wiring formed on the substrate are not limited, and ITO is not limited. Nickel (Ni), copper (Cu), chromium (Cr), on the wiring made of aluminum or aluminum (Al),
It is also possible to stack gold (Au) or the like to further increase the body resistance of the wiring. The number of wirings and the wiring width are also arbitrary.
Further, the viscosity of the conductive adhesive, the moving speed of the laminated body, and the like can be arbitrarily selected according to the width of the connecting means.

【0047】更に基板上における液晶駆動用半導体素子
の取り付け面も限定されず、TFT等の液晶駆動素子が
形成される面と反対の面に取り取り付ける等しても良
い。
Further, the mounting surface of the liquid crystal driving semiconductor element on the substrate is not limited, and it may be mounted on the surface opposite to the surface on which the liquid crystal driving element such as TFT is formed.

【0048】更に接続手段形成時、スペーサと交互に重
ねられ側面に接続手段を形成される基板は、基板単体で
あっても良いし、一対の基板を対向して組み立てたセル
基板或いはセル基板中に液晶組成物を注入した液晶注入
済みのセル基板であっても良い。
Further, when forming the connecting means, the substrate on which the connecting means is alternately laminated with the spacers to form the connecting means on the side surface may be a single substrate, or a cell substrate or a cell substrate in which a pair of substrates are assembled facing each other. It may be a cell substrate in which a liquid crystal composition has been injected into a liquid crystal.

【0049】[0049]

【発明の効果】以上説明したように本発明によれば、両
面に配線パターンが形成される基板と、スペーサとを交
互に重ね合わせて積層体を形成し、この積層体に導電性
接着剤を塗布する事により、大容量でありながら額縁領
域が小さく装置の小型化の実現を図る基板の側面に、基
板両面の配線パターンを電気的に接続する接続手段を一
括して均一且つ高速にて形成出来る。従って、従来の様
に基板両面の配線間が断線することが無く配線間の接続
の信頼性が向上されると共に、配線抵抗の均一化が図ら
れ、ひいては大容量かつ装置の小型化を実現するもので
ありながら、高精度の配線パターンにより高精細な画像
を得られる。しかも複数の基板に一括して接続手段を形
成出来、従来に比し接続手段の形成時間の短縮を図れ、
製造コストも著しく低減可能となる。
As described above, according to the present invention, a substrate on which wiring patterns are formed on both surfaces and spacers are alternately laminated to form a laminated body, and a conductive adhesive is applied to the laminated body. By coating, the frame area is small but the frame area is small, and the size of the device is reduced. On the side surface of the substrate, the connecting means for electrically connecting the wiring patterns on both sides of the substrate are collectively and uniformly formed at high speed. I can. Therefore, unlike the conventional case, there is no disconnection between the wirings on both sides of the substrate, the reliability of the connection between the wirings is improved, the wiring resistance is made uniform, and the large capacity and the miniaturization of the device are realized. However, it is possible to obtain a high-definition image by a highly accurate wiring pattern. Moreover, the connecting means can be collectively formed on a plurality of substrates, and the forming time of the connecting means can be shortened as compared with the conventional one.
The manufacturing cost can be significantly reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施の形態の液晶表示装置を示
す平面図である。
FIG. 1 is a plan view showing a liquid crystal display device according to a first embodiment of the present invention.

【図2】本発明の第1の実施の形態の液晶表示装置の一
部側面図である。
FIG. 2 is a partial side view of the liquid crystal display device according to the first embodiment of the present invention.

【図3】本発明の第1の実施の形態のバスライン及び分
岐線を示す平面図である。
FIG. 3 is a plan view showing bus lines and branch lines according to the first embodiment of this invention.

【図4】本発明の第1の実施の形態の液晶表示装置の額
縁領域[B]を示す一部斜視図である。
FIG. 4 is a partial perspective view showing a frame region [B] of the liquid crystal display device according to the first embodiment of the present invention.

【図5】本発明の第1の実施の形態の積層体のアレイ基
板及びスペーサの配置を展開して示す説明図である。
FIG. 5 is an explanatory diagram showing the arrangement of the array substrate and the spacer of the laminated body according to the first embodiment of the present invention in a developed state.

【図6】本発明の第1の実施の形態の積層体への導電性
接着剤の滴下を示す概略斜視図である。
FIG. 6 is a schematic perspective view showing dropping of a conductive adhesive onto the laminated body according to the first embodiment of the present invention.

【図7】本発明の第3の実施の形態の積層体を示す概略
斜視図である。
FIG. 7 is a schematic perspective view showing a laminated body according to a third embodiment of the present invention.

【図8】本発明の第4の実施の形態の積層体を示す概略
斜視図である。
FIG. 8 is a schematic perspective view showing a laminated body according to a fourth embodiment of the present invention.

【図9】本発明の第5の実施の形態の額縁領域[B]を
示す一部側面図である。
FIG. 9 is a partial side view showing a frame region [B] according to a fifth embodiment of the present invention.

【図10】本発明の第5の実施の形態の補助配線を示す
平面図である。
FIG. 10 is a plan view showing an auxiliary wiring according to a fifth embodiment of the present invention.

【図11】本発明の第6の実施の形態の額縁領域[B]
を示す一部側面図である。
FIG. 11 is a frame area [B] of the sixth embodiment of the present invention.
It is a partial side view which shows.

【図12】本発明の第6の実施の形態の補助電源配線を
示す平面図である。
FIG. 12 is a plan view showing an auxiliary power supply wire according to a sixth embodiment of the present invention.

【図13】本発明の第7の実施の形態の補助配線を示す
平面図である。
FIG. 13 is a plan view showing an auxiliary wiring according to a seventh embodiment of the present invention.

【図14】本発明の第8の実施の形態のアレイ基板を示
す一部斜視図である。
FIG. 14 is a partial perspective view showing an array substrate according to an eighth embodiment of the present invention.

【図15】本発明の第9の実施の形態を示す一部平面図
である。
FIG. 15 is a partial plan view showing a ninth embodiment of the present invention.

【図16】本発明の第9の実施の形態を示す一部側面図
である。
FIG. 16 is a partial side view showing a ninth embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1…液晶表示装置 2…アレイ基板 3…対向基板 A…表示領域 B…額縁領域 6…ドライバIC 7…リード線 8…バスライン 8a…分岐線 16…接着部 17…スペーサ 18…積層体 DESCRIPTION OF SYMBOLS 1 ... Liquid crystal display device 2 ... Array substrate 3 ... Counter substrate A ... Display area B ... Frame area 6 ... Driver IC 7 ... Lead wire 8 ... Bus line 8a ... Branch line 16 ... Adhesive part 17 ... Spacer 18 ... Laminated body

Claims (12)

【特許請求の範囲】[Claims] 【請求項1】 電極を有し液晶組成物を挾持する一対の
基板と、この一対の基板の少なくとも一方の基板の両面
に形成される配線パターンと、この配線パターンを有す
る基板側面に設けられ前記基板の両面に形成される配線
パターンを電気的に接続する接続手段とを具備する液晶
表示装置の製造方法において、 前記基板及び、外周が前記基板と同一又は前記基板より
若干小さいスペーサを、交互に複数枚重ねて積層体を形
成する工程と、 導電性接着剤を、前記積層体の積層方向にライン状に滴
下し前記基板側面に前記接続手段を形成する工程と、 を具備する事を特徴とする液晶表示装置の製造方法。
1. A pair of substrates having electrodes and holding a liquid crystal composition, wiring patterns formed on both surfaces of at least one of the pair of substrates, and a wiring pattern provided on a side surface of the substrate having the wiring pattern. In a method for manufacturing a liquid crystal display device, which comprises a connecting means for electrically connecting wiring patterns formed on both surfaces of a substrate, the substrate and spacers whose outer circumference is the same as or slightly smaller than the substrate are alternately formed. A step of stacking a plurality of sheets to form a laminated body; and a step of dropping a conductive adhesive in a line shape in the laminating direction of the laminated body to form the connecting means on the side surface of the substrate. Method for manufacturing liquid crystal display device.
【請求項2】 電極を有し液晶組成物を挾持する一対の
基板と、この一対の基板の少なくとも一方の基板の両面
に形成される配線パターンと、この配線パターンを有す
る基板側面に設けられ前記基板の両面に形成される配線
パターンを電気的に接続する接続手段とを具備する液晶
表示装置の製造方法において、 前記基板及び、外周が前記基板と同一又は前記基板より
若干小さいスペーサを、交互に複数枚重ねて積層体を形
成する工程と、 熱硬化型導電性接着剤を、前記積層体の積層方向にライ
ン状に滴下し前記基板側面に前記熱硬化型導電性接着剤
を取着する工程と、 前記積層体より前記基板を取り外し、前記熱硬化型導電
性接着剤を加熱硬化し前記基板側面に前記接続手段を形
成する工程と、 を具備する事を特徴とする液晶表示装置の製造方法。
2. A pair of substrates having electrodes and holding a liquid crystal composition, wiring patterns formed on both surfaces of at least one substrate of the pair of substrates, and a wiring pattern provided on a side surface of the substrate having the wiring pattern. In a method for manufacturing a liquid crystal display device, which comprises a connecting means for electrically connecting wiring patterns formed on both surfaces of a substrate, the substrate and spacers whose outer circumference is the same as or slightly smaller than the substrate are alternately formed. A step of stacking a plurality of sheets to form a laminated body, and a step of dropping a thermosetting conductive adhesive in a line shape in the laminating direction of the laminated body and attaching the thermosetting conductive adhesive to the side surface of the substrate. And a step of removing the substrate from the laminate, heat-curing the thermosetting conductive adhesive to form the connecting means on the side surface of the substrate, and manufacturing the liquid crystal display device. Method.
【請求項3】 電極を有し液晶組成物を挾持する一対の
基板と、この一対の基板の少なくとも一方の基板の両面
に形成される配線パターンと、この配線パターンを有す
る基板側面に設けられ前記基板の両面に形成される配線
パターンを電気的に接続する接続手段とを具備する液晶
表示装置の製造方法において、 前記基板及び、外周が前記基板と同一又は前記基板より
若干小さいスペーサを交互に複数枚重ねて積層体を形成
する工程と、 導電性接着剤を、印刷法にて前記積層体の積層方向にラ
イン状に配置し前記基板側面に前記接続手段を形成する
工程と、 を具備する事を特徴とする液晶表示装置の製造方法。
3. A pair of substrates having electrodes and holding a liquid crystal composition, wiring patterns formed on both surfaces of at least one substrate of the pair of substrates, and a wiring pattern provided on a side surface of the substrate having the wiring pattern. A method of manufacturing a liquid crystal display device, comprising: a connecting means for electrically connecting wiring patterns formed on both surfaces of a substrate, wherein a plurality of the substrates and spacers whose outer circumference is the same as or slightly smaller than the substrate are alternately arranged. A step of forming a laminated body by stacking sheets, and a step of arranging a conductive adhesive in a line shape in the laminating direction of the laminated body by a printing method to form the connecting means on the side surface of the substrate. A method for manufacturing a liquid crystal display device, comprising:
【請求項4】 電極を有し液晶組成物を挾持する一対の
基板と、この一対の基板の少なくとも一方の基板の両面
に形成される配線パターンと、この配線パターンを有す
る基板側面に設けられ前記基板の両面に形成される配線
パターンを電気的に接続する接続手段とを具備する液晶
表示装置の製造方法において、 前記基板及び、外周が前記基板と同一又は前記基板より
若干小さいスペーサを交互に複数枚重ねて積層体を形成
する工程と、 熱硬化型導電性接着剤を、印刷法にて前記積層体の積層
方向にライン状に配置し前記基板側面に前記熱硬化型導
電性接着剤を取着する工程と、 前記積層体より前記基板を取り外し前記熱硬化型導電性
接着剤を加熱硬化し前記基板側面に前記接続手段を形成
する工程と、 を具備する事を特徴とする液晶表示装置の製造方法。
4. A pair of substrates having electrodes and holding a liquid crystal composition, wiring patterns formed on both surfaces of at least one of the pair of substrates, and a wiring pattern provided on a side surface of the substrate having the wiring pattern. A method of manufacturing a liquid crystal display device, comprising: a connecting means for electrically connecting wiring patterns formed on both surfaces of a substrate, wherein a plurality of the substrates and spacers whose outer circumference is the same as or slightly smaller than the substrate are alternately arranged. A step of stacking the sheets to form a laminated body, and a thermosetting conductive adhesive is arranged in a line in the laminating direction of the laminated body by a printing method, and the thermosetting conductive adhesive is attached to the side surface of the substrate. And a step of removing the substrate from the laminate and heat-curing the thermosetting conductive adhesive to form the connecting means on the side surface of the substrate. The method of production.
【請求項5】 基板が、フェースダウン方式にて搭載さ
れる液晶駆動用半導体素子を更に具備する事を特徴とす
る請求項1乃至請求項4のいずれかに記載の液晶表示装
置の製造方法。
5. The method of manufacturing a liquid crystal display device according to claim 1, wherein the substrate further comprises a liquid crystal driving semiconductor element mounted by a face-down method.
【請求項6】 スペーサ外周が、導電性接着剤又は熱硬
化型導電性接着剤を導く切り欠き部を有する事を特徴と
する請求項1乃至請求項5のいずれかに記載の液晶表示
装置の製造方法。
6. The liquid crystal display device according to claim 1, wherein the outer periphery of the spacer has a cutout portion for guiding a conductive adhesive or a thermosetting conductive adhesive. Production method.
【請求項7】 基板側面が、導電性接着剤又は熱硬化型
導電性接着剤を導く凸部を有する事を特徴とする請求項
1乃至請求項5のいずれかに記載の液晶表示装置の製造
方法。
7. The liquid crystal display device according to claim 1, wherein a side surface of the substrate has a convex portion for guiding a conductive adhesive or a thermosetting conductive adhesive. Method.
【請求項8】 電極を有し液晶組成物を挾持する一対の
基板と、 この一対の基板の少なくとも一方の基板の両面に形成さ
れる配線パターンと、 この配線パターンを有する前記基板及び、外周が前記基
板と同一又は前記基板より少し小さいスペーサを、交互
に複数枚重ね合わせ積層体を形成し、前記積層体の積層
方向に導電性接着剤或いは熱硬化型導電性接着剤をライ
ン状に滴下してなり、前記基板側面にて前記基板の両面
に形成される配線パターンを電気的に接続する接続手段
と、 を具備する事を特徴とする液晶表示装置。
8. A pair of substrates having electrodes and holding a liquid crystal composition, wiring patterns formed on both surfaces of at least one substrate of the pair of substrates, the substrate having the wiring pattern, and the outer periphery. A plurality of spacers that are the same as or slightly smaller than the substrate are alternately stacked to form a laminated body, and a conductive adhesive or a thermosetting conductive adhesive is dripped in a line shape in the laminating direction of the laminated body. A liquid crystal display device, comprising: a connection unit that electrically connects wiring patterns formed on both sides of the substrate on the side surface of the substrate.
【請求項9】 基板に、フェースダウン方式にて搭載さ
れる液晶駆動用半導体素子を更に具備する事を特徴とす
る請求項8に記載の液晶表示装置。
9. The liquid crystal display device according to claim 8, further comprising a liquid crystal driving semiconductor element mounted on the substrate in a face-down manner.
【請求項10】 基板の第1の面上に、フェースダウン
方式にて搭載される液晶駆動用半導体素子を更に具備
し、前記基板の第2の面上に形成される配線パターンが
非透光性部材からなり、前記液晶駆動用半導体素子背面
を被覆する事を特徴とする請求項8に記載の液晶表示装
置。
10. A semiconductor device for driving a liquid crystal, which is mounted by a face-down method, is further provided on the first surface of the substrate, and a wiring pattern formed on the second surface of the substrate is non-translucent. 9. The liquid crystal display device according to claim 8, wherein the liquid crystal display device comprises a conductive member and covers the back surface of the liquid crystal driving semiconductor element.
【請求項11】 前記基板側面に搭載される受動部品を
更に具備する事を特徴とする請求項8に記載の液晶表示
装置。
11. The liquid crystal display device according to claim 8, further comprising a passive component mounted on the side surface of the substrate.
【請求項12】 接続手段が、配線パターンへの入力端
子である事を特徴とする請求項8に記載の液晶表示装
置。
12. The liquid crystal display device according to claim 8, wherein the connecting means is an input terminal to the wiring pattern.
JP5168496A 1996-03-08 1996-03-08 Production of liquid crystal display device and liquid crystal display device Pending JPH09244053A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5168496A JPH09244053A (en) 1996-03-08 1996-03-08 Production of liquid crystal display device and liquid crystal display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5168496A JPH09244053A (en) 1996-03-08 1996-03-08 Production of liquid crystal display device and liquid crystal display device

Publications (1)

Publication Number Publication Date
JPH09244053A true JPH09244053A (en) 1997-09-19

Family

ID=12893727

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5168496A Pending JPH09244053A (en) 1996-03-08 1996-03-08 Production of liquid crystal display device and liquid crystal display device

Country Status (1)

Country Link
JP (1) JPH09244053A (en)

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