JPH09244047A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the residual rate of conductive particles under bumps and to improve the reliability of connection by providing the device with means for suppressing the outflow of conductive particles from under the bumps at the time of pressurization under heating. SOLUTION: Packaging of an IC for driving is executed by connecting plural pieces of the bumps BUMPs on the rear surface of the IC for driving via anisotropic conductive films ACFs by thermal press bonding onto wirings d1 consisting of the ITO films formed on the surface of a transparent insulating substrate SUB1 constituting an LCD. At this time, there are end parts on the side inner than the external shape lines of the bumps BUMPs and the binder BD of the anisotropic conductive films ACFs is melted at the time of thermal press bonding of the anisotropic conductive films ACFs, by which the conductive particles EPs in the anisotropic conductive films ACFs are made to flow out from under the bumps BUMPs. The outflow is suppressed by the walls consisting of the passivation films PSVs 1 formed on the circumferences of the wirings d1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display having a flip-chip type liquid crystal display element in which a driving IC is directly mounted on one of two transparent insulating substrates which are stacked via a liquid crystal layer. Regarding the device.

[0002]

2. Description of the Related Art For example, in order to mount a driving IC on one transparent insulating substrate of a liquid crystal display element (liquid crystal display panel), outer leads of a tape carrier package (TCP) mounted with the driving IC and a liquid crystal display panel. The upper wiring pattern is electrically connected using an anisotropic conductive film. This anisotropic conductive film is a film-shaped thermosetting adhesive in which fine conductive particles are uniformly dispersed, and is heated and pressed to connect the outer lead and the wiring pattern, which face each other, to make the TCP part transparent. It can be fixed to an insulating substrate.

However, in recent years, due to the demand for higher density liquid crystal display elements and the desire to reduce the module outer shape as much as possible, TCP components are not used, and bump electrodes of the driving IC and one of the liquid crystal display elements are not used. A method of directly connecting with a wiring pattern on a transparent insulating substrate has been considered. Such a mounting method is called a flip-chip (FCA) method, or a chip-on-glass (COG) mounting method because a driving IC is mounted on a transparent insulating substrate.

Although not a publicly known example, the same applicant applies to a flip-chip type liquid crystal display device.
There is a prior application regarding the module mounting method (Japanese Patent Application No. 6-2
56426).

This flip-chip connection method is shown in FIG.
This will be described with reference to FIG. First, as shown in FIG. 15A, bumps BUMP (protruding electrodes) are formed on the driving IC, and the bumps BUMP (projection electrodes) are held on the pressure surface of the bonding head HEAD by vacuum suction or the like. A wiring pattern DTM (GTM) to be joined to the bump BUMP is formed on the transparent insulating substrate SUB1. Furthermore, an anisotropic conductive film ACF is previously attached on the wiring pattern DTM (GTM).

The bump BUMP and the wiring pattern DTM
(GTM) is an imaging camera CAM arranged below the transparent insulating substrate SUB1 with the imaging surface FACE facing upward.
The transparent insulating substrate SUB1 based on the signal from ERA
Are driven in the XY directions to align the bump BUMP with the wiring pattern DTM (GTM).

Then, as shown in FIG. 15 (b), the bonding head HEAD is driven downward to bring the bump BUMP into contact with the upper surface of the anisotropic conductive film ACF, temporarily attach the same, and surely again. It is confirmed by the imaging camera CAMERA whether or not it is positioned, and if it is good, it is heated and pressure-bonded by the bonding head HEAD.

In this way, the conductive particles in the anisotropic conductive film ACF are crushed between the bump BUMP and the wiring pattern DTM, and electrical connection is possible.

Further, although not shown in FIG. 15, a flexible substrate (FPC) electrically connected to an input wiring pattern to the driving IC is also subjected to a similar bonding method by a wiring pattern on the flexible substrate. (Normally, the copper pattern is plated with gold.) And the wiring pattern (Td) on the transparent insulating substrate SUB1 can be electrically connected by the anisotropic conductive film ACF.

[0010]

As described above, in the flip-chip mounting method, the bumps on the lower surface of the driving IC and the wiring provided on the transparent insulating substrate surface are heated via the anisotropic conductive film. Direct connection is made by applying pressure, and the driving IC is mounted on the surface of the transparent insulating substrate. The anisotropic conductive film is composed of, for example, conductive particles that are electrical connection means formed by plating nickel and gold on the surface of spherical plastic beads, and epoxy resin that is a binder. By the way, when the bumps and the wiring of the transparent insulating substrate are heated and pressed to connect the anisotropic conductive film interposed between the two, the conductive particles under the bumps flow out from under the bumps to the outside. The number of conductive particles that contribute to electrical connection
There was a problem that the pressure was reduced to about 20 to 30% before the pressure bonding. As a countermeasure against this, an anisotropic conductive film having a large number of dispersed conductive particles, that is, a high dispersion density is used to maintain connection reliability. However, in this case,
An anisotropic conductive film having a high dispersion density is not only expensive, but also the number of conductive particles remaining under the bumps varies, and there is still a problem in connection reliability.

An object of the present invention is to provide a flip-chip type liquid crystal display device in which the number of conductive particles flowing out from under the bumps of the driving IC when the anisotropic conductive film is heated and pressed when the driving IC is mounted. It is to suppress the above, increase the remaining rate thereof, and improve the connection reliability.

[0012]

In order to solve the above problems, the present invention disperses a large number of fine conductive particles in bumps on the lower surface of a driving IC chip and wirings provided on the surface of a transparent insulating substrate. A flip-chip liquid crystal display device in which the driving IC chip is directly mounted on the surface of the transparent insulating substrate, which is connected by heating and pressing through an anisotropic conductive film.
A means for suppressing the conductive particles from flowing out from under the bump during the heating and pressing is provided.

Further, the present invention is characterized in that an end portion is provided inside the outline of the bump and a wall is provided to prevent the conductive particles from flowing out from under the bump during the heating and pressing.

In addition, an insulating material having an opening smaller than the size of the bump is provided under the bump, and an end portion of the opening suppresses the conductive particles from flowing out from under the bump during the heating and pressing. It is characterized in that a film is provided.

Further, the insulating film is a passivation film.

According to the present invention, when the anisotropic conductive film is melted by heating and pressurizing, the conductive particles can be prevented from flowing out from under the bumps, and the residual ratio of the conductive particles under the bumps can be increased. The connection reliability can be improved.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. In the drawings described below, components having the same function are designated by the same reference numeral, and repeated description thereof will be omitted.

<< Overall Structure of Liquid Crystal Display Module MDL >>
FIG. 8 is an exploded perspective view of the liquid crystal display module MDL.

SHD is a shield case made of a metal plate (also called a metal frame), WD is a display window, and SPC1
4 is an insulating spacer, FPCs 1 and 2 are multilayer flexible circuit boards (FPC 1 is a gate side circuit board, FPC 2 is a bent drain side circuit board), PCB is an interface circuit board, and ASB is an assembled liquid crystal display with a drive circuit board. The element PNL is a liquid crystal display element (also referred to as a liquid crystal display panel or LCD (liquid crystal display)) in which a driving IC is mounted on one of two transparent insulating substrates that are stacked, GC1 and GC.
2 is a rubber cushion, PRS is a prism sheet (2
Sheet), SPS is a diffusion sheet, GLB is a light guide plate, RFS is a reflection sheet, MCA is a lower case (molded case) formed by integral molding, LP is a fluorescent tube, LPC is a lamp cable, and LCT is a connection for an inverter. Connector, G
B is a rubber bush that supports the fluorescent tube LP, and the members are stacked in a vertical arrangement as shown in the figure to assemble the liquid crystal display module MDL.

<< Bending Mounting Method of Flexible Substrate FPC2 >> Next, a bending mounting method of the flexible substrate FPC2 will be described.

FIG. 9 is a perspective view showing a method of bending and mounting a multilayer flexible substrate. Drain driver board F
For connection between the PC2 and the gate driver board FPC1, a flat connector CT4 provided as a joiner at the tip of a convex portion JT2 formed of a flexible board integrated with the FPC2 is used, and the interface board PCB (FIG. 8) is bent.
Electrically connect to the connector (see).

Next, the double-sided tape BAT is provided on the surface of the flexible substrate FPC2 where the conductor layer portion FML is not mounted.
And then bend it at the conductor layer portion BNT using a jig.

As described above, the jig can be used to accurately fold the multilayer flexible substrate FPC2 and bond it to the surface of the transparent insulating substrate SUB1.

<< Mounting of the driving IC and the flexible substrate FPC on the transparent insulating substrate SUB1 >> FIG. 10 shows the driving IC.
1 is a sectional view showing a part of a manufacturing process according to the present invention in which the flexible substrate FPC and the flexible substrate FPC are mounted on the transparent insulating substrate SUB1.
FIG. 1 is a diagram showing the manufacturing flow thereof.

First, the anisotropic conductive film ACF2 is first attached to a plurality of driving IC portions arranged in a line. In this example, as shown in FIG. 3, a plurality of driving ICs arranged on each side
Commonly, one piece processed into a slender shape is attached, and there are a total of two pieces on the gate side and the drain side.

Next, the driving IC is bonded to the bonding head H.
Hold on the pressure surface of EAD and bump BUMP (projection electrode)
The position of is adjusted by the imaging camera CAMERA so as to have a predetermined relative positional relationship (FIG. 10A). In this example, the bumps BUMP are aligned so that the center thereof is exactly the center of the imaging surface FACE.

Next, the position of the alignment mark ALC on the transparent insulating substrate SUB1 is adjusted by the image pickup camera CAMERA so as to have a predetermined relative positional relationship (FIG. 10).
(B)). In this example, the alignment is performed so that the center of the alignment mark ALC is exactly the center of the imaging surface FACE.

Therefore, the relative positions of the bump BUMP and the alignment mark ALC are determined. The alignment mark ALC is, for example, a square pattern in which a transparent ITO film used as a material of a transparent pixel electrode is coated on an opaque aluminum AL used as a material of a gate wiring.

Next, the alignment mark A stored in advance
The XY stage is moved based on the relative position coordinates of the LC and the bonding portion of the wiring pattern, and the bonding portion of the wiring pattern is placed above the imaging surface FACE to detect the position. Normally, the mechanical movement accuracy of the XY stage is
Position correction is not performed in this step because it is much better than bonding accuracy.

Next, temporary attachment is performed for each driving IC (FIG. 10C).

Next, the bump BU is temporarily attached.
The relative positional relationship between the MP and the bonding portion of the wiring pattern is reconfirmed. In this step, if it is determined that the position is defective, the XY stage is finely moved again to correct the position because it is still temporarily attached.

Next, the bonding head HEAD is further lowered, and a plurality of driving ICs, which are normally arranged on one side, are collectively heat-pressed onto the transparent insulating substrate SUB1 to form the driving ICs. The bump BUMP and the wiring patterns DTM and Td of the transparent insulating substrate SUB1 are electrically connected by the anisotropic conductive film ACF2.

Next, the bonding head HEAD is raised, and the liquid crystal display panel on which the driving IC is mounted is once moved from the bonding step to the inspection step.

Next, in the inspection process, the connection state of the bumps BUMP and the operating state of the driving IC are tested from an inspection pad (not shown). If any defect is confirmed, repair work will be performed if possible.

Next, the anisotropic conductive film ACF1 is attached to the input wiring pattern portions for the plurality of driving ICs.
In the present example, as shown in FIG. 3, a plurality of driving ICs arranged on each side are processed into one elongated shape in common, and there are two in total.

Next, the liquid crystal display panel PNL and the flexible substrate FPC are roughly fixed by inserting the openings FHL opened at both ends of the flexible substrate FPC into the fixing pins. Further, in order to improve the alignment accuracy, the alignment mark ALMG (or ALMD; see FIG. 9) and the alignment mark ALC are aligned and position-corrected above the imaging surface FACE (FIG. 10 (d)).

Next, temporary attachment is performed (FIG. 10 (e)). Check the position again.

Finally, the bonding head HEAD is further lowered, the flexible substrate FPC is thermocompression bonded onto the transparent insulating substrate SUB1, and the flexible substrate FPC and the wiring pattern Td of the transparent insulating substrate SUB1 are anisotropically conductive film ACF1. Connect electrically.

<< Conductive Particles EP in Anisotropic Conductive Film ACF2
Prevention of outflow from under the bump BUMP of the driving IC >> FIG. 1 shows the bump BUMP of the driving IC and the transparent insulating substrate S.
FIG. 2 is a cross-sectional view of a main part showing a state in which the wiring of UB1 is connected by an anisotropic conductive film ACF (cross-sectional view taken along the line 1-1 in FIG. 2). It is a principal part top view which shows the surface of the board | substrate SUB1. FIG.
Then, the aluminum film g1 and the silicon oxide film SIO under the wiring d1 shown in FIG. 4 and FIGS.

To mount the driving IC, as described above, the wiring d1 made of, for example, an ITO (indium tin oxide) film formed on the surface of the transparent insulating substrate SUB1 which constitutes the liquid crystal display panel PNL (LCD). A plurality of bumps BUMP on the lower surface of the driving IC are mounted on the upper part by thermocompression bonding via the anisotropic conductive film ACF. The anisotropic conductive film ACF is configured, for example, by dispersing a large number of conductive particles EP, which are obtained by performing nickel plating and gold plating on the surface of spherical fine plastic beads, in a binder BD made of, for example, an epoxy resin. By heating and pressing, the conductive particles EP in the anisotropic conductive film ACF2 are crushed between the bump BUMP and the wiring d1, as shown in FIG.
The upper part of the conductive particles EP is embedded in the bump BUMP, and the bump BUMP and the wiring d1 are electrically connected.

In the present embodiment, as shown in FIGS. 1 and 2, the end portion is inside the outline of the bump BUMP, and the anisotropic conductive film AC is heated and pressed when the anisotropic conductive film ACF2 is pressure-bonded.
A wall made of a passivation film (protective film) PSV1 that suppresses the binder BD of F2 from melting and the conductive particles EP in the anisotropic conductive film ACF2 from flowing out from under the bump BUMP is provided. That is, under the bump BUMP,
An opening smaller than the size of the bump BUMP is provided, and a passivation film PSV1 for suppressing the outflow of the conductive particles EP during thermocompression bonding is provided on the wiring d1 by the end portion of the opening.

That is, in order to reduce the connection resistance, the terminal portion of the flip-chip type liquid crystal display element is usually formed with a low resistance metal film up to the vicinity of the ITO film d1 terminal to which the bump BUMP is connected. In order to prevent electrolytic corrosion of the metal film, for example, a transparent insulation film is formed by a passivation film PSV1 made of a silicon oxide film, a silicon nitride film, or the like formed by a plasma CVD apparatus, except for the ITO film d1 portion connected to the bump BUMP. The surface of the substrate SUB1 is covered. In this embodiment, the passivation film PSV1 is used to form a wall having a predetermined width higher than the wiring d1 around the wiring d1 to which the bump BUMP is connected.

In FIG. 1, each numerical value indicates a dimension, and the unit is μm. That is, as shown in the figure, the film thickness of the ITO film d1 is 0.14 μm, the film thickness of the passivation film PSV1 is 3 μm, and the film thickness of the passivation film PSV1 on the ITO film d1 (that is, the height of the outflow suppressing wall of the conductive particles EP is high. Is 3 μm, anisotropic conductive film AC
The thickness of F2 is 13 μm, the outer diameter of the conductive particles EP is 5 μm,
The outer diameter of the crushed conductive particles EP under the bump BUMP is 3 μm, the width of the ITO film d1 is 98 μm, the interval between the ITO films d1 is 43 μm, and the width of the bump BUMP is 70 μm.
m, the width on one side of the overlapping portion of the bump BUMP and the passivation film PSV1 is 5 μm, and the density of the conductive particles of the anisotropic conductive film ACF2 is 10,000 particles / 1 mm ² .

With such a structure, as shown in FIG. 10C, when the epoxy resin as the binder BD of the anisotropic conductive film ACF2 is melted and flows in the process of thermocompression bonding with the bonding head HEAD. As shown in FIG. 1, the conductive particles EP under the bumps BUMP of the driving IC chip are caught by the wall made of the passivation film PSV1 formed around the wiring d1 and flow out from under the bumps BUMP to the outside. Is suppressed. Therefore, the number of remaining conductive particles EP under the bump BUMP that contributes to electrical connection increases, that is, the remaining rate increases. Conventionally, it has been reduced to about 20 to 30%,
In this example, it could be suppressed to about 80%. Also, bump BUMP
Only on the wiring d1 connected to the passivation film PS
Since V1 is opened, it is effective in preventing electrolytic corrosion. As a result, the electrical connection reliability of the driving IC can be significantly improved. Further, since it is not necessary to use an expensive anisotropic conductive film having a high dispersion density of conductive particles, it is possible to suppress an increase in manufacturing cost.

<< Plane and Cross Sectional Structure in the Vicinity of the Driving IC Chip Mounting Portion >> FIG. 3 is a plan view showing a state in which the driving IC is mounted on the transparent insulating substrate SUB1 made of, for example, glass. Further, FIG. 4 shows a sectional view taken along the line AA. In FIG. 3, one transparent insulating substrate SUB2 is
As shown by the alternate long and short dash line, the liquid crystal LC is enclosed above the transparent insulating substrate SUB1 and includes the effective display portion (effective screen area) AR by the seal pattern SL. The electrode COM on the transparent insulating substrate SUB1 is a wiring electrically connected to the common electrode pattern on the transparent insulating substrate SUB2 side via conductive beads, silver paste, or the like. The wiring DTM (or GTM) supplies the output signal from the driving IC to the wiring in the effective display area AR.
The input wiring Td supplies an input signal to the driving IC. The anisotropic conductive film ACF has an elongated shape common to a plurality of driving IC parts arranged in a line AC
F2 and ACF1 having an elongated shape common to the input wiring pattern portions to the plurality of driving ICs are separately attached. Passivation film (protective film) PSV1,
As shown in FIG. 4, the PSV covers the wiring portion as much as possible and the exposed portion is covered with the anisotropic conductive film ACF1 to prevent electrolytic corrosion.
To cover.

Further, the periphery of the side surface of the driving IC is filled with epoxy resin or silicone resin SIL (see FIG. 4).
See), protection is multiplexed.

<< Method of Manufacturing Transparent Insulating Substrate SUB1 >> Next, the first transparent insulating substrate SUB of the liquid crystal display device described above.
The manufacturing method on the first side will be described with reference to FIGS. In the figure, the central character is an abbreviation for the process name, the left side shows the pixel portion, and the right side shows the processing flow as seen in the cross-sectional shape near the gate terminal. With the exception of steps B and D, the steps A to G are divided according to each photo (photo) process, and all the cross-sectional views of each process are the steps after processing after photo processing and removing photoresist. Is shown. In the present description, the photo (photo) processing means a series of operations from application of photoresist to selective exposure using a mask to development thereof.
Avoid repetitive explanations. Description will be given below according to the divided steps.

Step A, FIG. 12 After the silicon oxide films SIO are formed on both surfaces of the first transparent insulating substrate SUB1 made of 7059 glass (trade name) by dipping, baking is performed at 500 ° C. for 60 minutes. The SIO film is formed to reduce the surface irregularities of the transparent insulating substrate SUB1, but if the irregularities are small,
This is a process that can be omitted. Al-T with a film thickness of 2800Å
The first conductive film g1 made of a, Al-Ti-Ta, Al-Pd, or the like is provided by sputtering. After the photo-treatment, the first conductive film g1 is selectively etched with a mixed acid solution of phosphoric acid, nitric acid and glacial acetic acid.

Step B, FIG. 12 After directly drawing the resist (after forming the above-mentioned anodic oxidation pattern),
3% tartaric acid PH6.25 ± 0.05 by ammonia
The substrate SUB1 was dipped in an anodizing solution composed of a solution prepared by diluting the solution prepared in step 1 with ethylene glycol solution 1: 9,
The formation current density is adjusted to 0.5 mA / cm ² (constant current formation). Next, anodic oxidation (anodic formation) is performed until the formation voltage 125 V required to obtain a predetermined Al ₂ O ₃ film thickness is reached. After that, it is desirable to hold this state for several tens of minutes (constant voltage formation). This is a uniform A
This is important in obtaining an l ₂ O ₃ film. Thereby,
The conductive film g1 is anodized, and the film thickness is 1800Å in a self-aligned manner on and above the scanning signal line (gate line) GL.
Thin film transistor TF
It becomes a part of the T gate insulating film.

Step C, FIG. 12 A conductive film d1 made of an ITO film having a film thickness of 1400Å is provided by sputtering. After the photo process, the conductive film d1 is selectively etched with a mixed acid solution of hydrochloric acid and nitric acid as an etching solution to form the uppermost layer of the gate terminal GTM and the drain terminal DTM and the transparent pixel electrode ITO1.

Step D, FIG. 13 Ammonia gas, silane gas and nitrogen gas are introduced into the plasma CVD apparatus to provide a 2000 Å-thickness Si nitride film, and silane gas and hydrogen gas are introduced into the plasma CVD apparatus to reduce the film thickness. After the 2000 Å i-type amorphous Si film is formed, hydrogen gas and phosphine gas are introduced into the plasma CVD apparatus to form an N ⁺ -type amorphous Si film d0 having a film thickness of 300 Å. This film formation is continuously performed by changing the reaction chamber in the same CVD apparatus.

Step E, FIG. 13 After photo processing, SF ₆ and BC are used as dry etching gas.
N ⁺ type amorphous Si film d0, i type amorphous Si
The film AS is etched. Then, SF ₆ is used to etch the Si nitride film GI. Of course, the N ⁺ type amorphous Si film d0, the i type amorphous Si film AS and the nitrided Si film GI may be continuously etched with SF ₆ gas.

The feature of the manufacturing process of this embodiment is to continuously etch the three-layered CVD film with the gas containing SF ₆ as a main component in this manner. That is, the etching rate for the SF ₆ gas increases in the order of the N ⁺ type amorphous Si film d0, the i type amorphous Si film AS, and the Si nitride film GI. Therefore, when the N ⁺ -type amorphous Si film d0 is completely etched and the i-type amorphous Si film AS starts to be etched, the N ^{+ -type}
The type amorphous Si film d0 is side-etched, and as a result, the i type amorphous Si film AS is processed into a taper of about 70 degrees. Further, when the etching of the i-type amorphous Si film AS is completed and the etching of the silicon nitride film GI is started, side etching is performed on the upper N ⁺ -type amorphous Si film d0 and the i-type amorphous Si film AS in this order. As a result, the i-type amorphous Si film AS is about 50 degrees,
The silicon nitride film GI is tapered at 20 degrees. Due to the taper shape, the probability of disconnection is significantly reduced even when the source electrode SD1 is formed on the taper. The taper angle of the N ⁺ -type amorphous Si film d0 is close to 90 degrees, but since the thickness is as thin as 300 Å, the probability of disconnection at this step is very small. Therefore, the N ⁺ -type amorphous Si film d0, the i-type amorphous Si film AS, and the nitrided Si film GI are not exactly the same pattern in the plane pattern, and the cross section has a forward tapered shape. Therefore, the N ⁺ type amorphous Si film d0 and the i type amorphous Si film A
The pattern becomes larger in the order of S and the Si nitride film GI.

Step F, FIG. 14: A second conductive film d2 made of Cr having a film thickness of 600 Å is provided by sputtering.
A third conductive film d3 made of Pd, Al-Si, Al-Ta, Al-Ti-Ta or the like is provided by sputtering.
After the photo-treatment, the third conductive film d3 is etched with the same liquid as in step A, the second conductive film d2 is etched with a second cerium ammonium nitrate solution, and the video signal line DL, the source electrode SD1, and the drain electrode SD2 are etched. To form.

In this embodiment, as shown in step E, the N ⁺ type amorphous Si film d0, the i type amorphous Si film AS,
Since the Si nitride film GI is a normal taper, it is possible to form only the second conductive film d2 in a liquid crystal display device having a large tolerance of the resistance of the video signal line DL.

Next, SF ₆ and
By introducing BCl and etching the N ⁺ type amorphous Si film d0, the N ⁺ type semiconductor layer d0 between the source and the drain is selectively removed.

Step G, FIG. 14 Ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD apparatus to form a silicon nitride film having a thickness of 0.6 μm. After photo processing, SF _{6 is used} as a dry etching gas.
By etching using a protective film PSV1
To form As the protective film, not only an SiN film formed by CVD but also an organic material can be used.

<< Countermeasures against static electricity by short-circuit wiring SHc under the driving IC >> FIG. 5 is a plan view of the essential parts showing the periphery of the driving IC mounting portion of the transparent insulating substrate SUB1 and the vicinity of the cutting line CT1 of the substrate. .

As shown in FIG. 5, the drain driving I
Both the input and output of C are output from one side of the IC chip. Every other drain line DL extends in alternate directions, one extends beyond the cutting line CT1 and is short-circuited by being connected to the drain short-circuit wiring SHd extending in the y direction, and the other is shown in FIG. Thus, it extends beyond the cutting line CT1 through the short-circuit wiring SHc and the input wiring Td (to the drain line driving IC), is connected to the drain short-circuit wiring SHd, and is short-circuited. That is, every other drain line DL is connected to the short-circuit wiring SHc and short-circuited for each driving IC, and the short-circuit wiring SHc is connected to the two input wirings Td to the drain-line driving IC. It is short-circuited to the drain short-circuit wiring SHd via the book input wiring Td. In this way, the static electricity generated in each drain line DL and the input wiring Td is transferred to the short-circuit wiring SHc and the drain short-circuit wiring S.
It is designed to be dispersed through Hd. After the liquid crystal display element is completed, the drain short-circuit wiring SHd is cut off and discarded in the subsequent process, because it does not operate unless the short circuit is released.
It is formed on the surface of UB1. Drain short circuit wiring SHd
The short circuit release of the drain line DL directly connected to is performed by cutting the substrate SUB1 along the cutting line CT1. on the other hand,
Due to the existence of the short-circuit wiring SHc, the drain line DL connected to the drain short-circuit wiring SHd via the short-circuit wiring SHc and the input wiring Td is not released by cutting the substrate SUB1 along the cutting line CT1. This short circuit release will be described later.

On the other hand, of the formation region of each gate line GL,
In the region inside the cutting line CT1, the cutting line CT1 on the upper side in the drawing
An area for mounting the gate line driving IC is provided in a portion close to. Each gate line GL is a gate short-circuit wire (not shown) whose extension part beyond the cutting line CT1 on the side opposite to the mounting region in the extension direction doubles as an anodization wire extending in the y direction. Connected through. Note that after completion of the liquid crystal display element, it does not operate unless the short circuit is released. Therefore, the gate short-circuit wiring is cut and discarded in each subsequent step.
It is formed on the surface of UB1. In this example, unlike the drain line DL side, the short-circuit wiring SHc for each IC is not provided on the gate line GL side. This is because the gate line driving ICs are arranged on only one side, and the gate lines GL can be short-circuited to each other by the gate short-circuit wiring on the opposite side (the side on which the gate line driving ICs are not arranged). is there. However, when the gate line driving ICs are arranged on both sides or when the gate short-circuit wiring is not arranged, the gate line GL needs to be connected to the gate short-circuit wiring via the short-circuit wiring SHc.

As shown in FIGS. 5 and 6, the short-circuit wiring SHc and every other drain terminal DTM and the input wiring Td are provided before the driving IC is mounted on the surface of the substrate SUB1. The cutting line C1 is cut by laser or photo etching. Therefore, because of this disconnection, FIG.
As shown in, the area with the cutting line C1 (IC mounting area)
Is not formed with the passivation film PAS1 (that is, the protective film PSV1). In this example, the cutting line C1
The short circuit can be released easily with one cut in.

Since the wiring DTM at the cutting line C1 is formed of the transparent conductive film ITO which is less contaminated during laser cutting, contamination can be suppressed. Also,
This cutting may be performed by photoetching.

Although FIG. 5 shows the drain driving IC side, the structure having the short-circuit wiring SHc outputs and inputs from one side of the IC chip to the gate scanning driving IC side. It goes without saying that it can be applied to the case.

<< Opaque Film Pattern BAR for Detecting Driving IC Chip Deviation >> FIG. 6 is an enlarged detailed view of a main part (drain input side corner part) of FIG. 5, and FIG. 7 is a main part of FIG. 5 (drain output side corner part). ) Is an enlarged detailed view of FIG.

In FIGS. 5, 6 and 7, BAR is a pattern for detecting the positional deviation of the driving IC after mounting. That is, the wiring d1 connected to the bump BUMP of the driving IC
And on the surface of the substrate SUB1 near the bump BUMP,
A pattern BAR including an opaque film for detecting the displacement of the driving IC is provided. This misalignment detection pattern B
As shown in FIGS. 6 and 7, AR is a conductive film d1 made of an ITO film and a second conductive film d2 made of Cr, Al−, which are described in the above “Method for manufacturing transparent insulating substrate SUB1”.
The third conductive film d3 is made of Pd, Al-Si, Al-Ta, Al-Ti-Ta or the like, and the protective film PSV1. That is, it includes opaque films d2 and d3. Also,
The pattern BAR is provided at the same pitch as the wiring and the bump BUMP. In addition, the transparent insulating substrate SU
The wiring formed on the surface of the substrate SUB1 connected to the bumps made of gold (Au) or the like of the driving IC mounted on the surface B1 is conventionally formed of a single layer of the transparent conductive film d1.
Therefore, after mounting the driving IC, it was difficult to determine the mounting position deviation of the driving IC with respect to the wiring d1 from the transparent insulating substrate surface side opposite to the side on which the driving IC was mounted. In the structure, since the pattern BAR having the opaque film is provided, after the driving IC is mounted, the wiring is visually or visually observed from the transparent insulating substrate SUB1 surface side opposite to the side where the driving IC is mounted. It is possible to easily confirm the mounting position deviation of the driving IC with respect to d1. Therefore, as a result, the manufacturing yield and throughput can be improved. The uppermost protective film PSV1 of the pattern BAR
Is provided to prevent electrolytic corrosion of the conductive films d2 and d3.

The misregistration detection pattern BAR need only include at least one opaque film, and in addition to the conductive films d2 and d3, a colored film such as the i-type amorphous Si film AS. May be used.

<< Compatible with plural kinds of driving IC chips >>
In the transparent insulating substrate SUB1 shown in FIG. 1, the input and output terminals to which the input and output bumps of the driving IC are connected and their wiring are considered in advance so that a plurality of different types of driving IC chips can be mounted. It is arranged and formed on the SUB1. Reference numerals IC1 and IC2 in the figure indicate positions where two types of driving ICs having different widths in the x direction are mounted. That is, the input terminal IP to which the input bumps of the driving IC are connected and the wiring thereof are provided so as to include the dummy input terminal and the wiring thereof so as to correspond to different types of chips. That is, although the layout of bumps to which a predetermined signal or power is input differs depending on the type of chip, the input terminals and wiring are provided in advance so as to be compatible with the bump layout of a plurality of types of chips. Also, for driving I
The output wiring OL to which the bump of C is connected is formed in parallel over a predetermined length so that a plurality of types of driving ICs having different widths in the wiring extension direction (x direction in the drawing) can be mounted. . Conventionally, one type of transparent insulating substrate SU
Only one type of driving IC could be mounted on B1. Therefore, when the type of the driving IC chip is not available or for any other reason, it is necessary to change the wiring layout of the transparent insulating substrate on which the chip is mounted. Therefore, there is a problem that the manufacturing cost increases. However, in the substrate SUB1 shown in FIG. 5, wirings to which bumps of the chips are connected are arranged and formed on the substrate SUB1 so that different types of chips can be mounted. The SUB1 can be shared and the transparent insulating substrate SUB1 does not need to be changed even when the chip is changed. Therefore, the manufacturing cost can be reduced.

<< Alignment mark ALD between the driving IC and the substrate SUB1 >> On the surface of the transparent insulating substrate SUB1 shown in FIG. 5, in the region where the driving IC overlaps the substrate SUB1,
In other words, within the dotted line area with the reference symbols IC1 and IC2,
An alignment mark ALD with the driving IC is provided on the substrate SUB1. Further, the substrate SU of the driving IC
As shown in FIG. 6, a dummy bump BUMP as an alignment mark paired with the alignment mark ALD is provided on the surface facing B1. The bump BUMP is smaller than the alignment mark ALD and When a driving IC is mounted on the SUB1, the alignment mark ALD
Has a shape surrounding the bump BUMP. As is clear from FIG. 6, the alignment mark ALD includes the conductive film d1 made of an ITO film and the second conductive film d2, A made of Cr.
1-Pd, Al-Si, Al-Ta, Al-Ti-Ta
And a protective film PSV1 (see above << Method for Manufacturing Transparent Insulating Substrate SUB1 >>). Since the second conductive film d2 and the third conductive film d3 are opaque films, they can be easily identified. In addition, the uppermost protective film PSV1
Is for preventing electrolytic corrosion of the conductive films d2 and d3. As a result, the driving IC can be accurately positioned and the substrate SU
It can be electrically connected to the wiring pattern on B1.

Reference symbol ALC is a transparent insulating substrate SUB1.
Is a registration mark with the flexible substrate FPC provided on the substrate SUB1 in a region where the flexible substrate FPC overlaps with the substrate SUB1 on the surface. In addition, on the surface of the flexible substrate FPC facing the substrate SUB1,
An alignment mark (not shown) that is paired with the alignment mark ALC is provided, and the mark is larger than the alignment mark ALC, has a square shape, and has a substrate SUB1.
When the flexible board FPC is mounted on the upper side, the alignment mark ALC is surrounded by the mark. The alignment mark ALC is a square pattern in which a transparent ITO film used as a material of a transparent pixel electrode is coated on opaque aluminum Al used as a material of a gate wiring.

<< Relationship between the distance between the terminals DTM and GTM on the drain output side and the gate input side and the distance between the bumps BUMP >> The drain output side, that is, the drain driving I
At the output terminal DTM from C, as shown in FIG.
The distance L ₁ between the bumps BUMP connected to the terminals DTM is smaller than the distance L ₂ between the terminals DTM.
For example, L ₁ is 20 μm and L ₂ is 30 μm. Therefore, since the width of the bump BUMP is wider than the width of the terminal DTM, even if the displacement of the bump BUMP with respect to the terminal DTM occurs due to the displacement of the driving IC, the bump BUMP
Since the contact area between the terminal and the terminal DTM is secured, the resistance can be reduced. Further, the distance L ₂ between the terminals DTM can be made large, and the electrolytic corrosion of the terminal DTM formed of the transparent conductive film d1 which easily causes electrolytic corrosion can be suppressed. In addition, bump BUMP
Although they are close to each other, the bump BUMP is made of gold, which is unlikely to cause electrolytic corrosion, so there is no problem of electrolytic corrosion. Recently, in order to miniaturize the liquid crystal display module and the liquid crystal display element has become higher in definition, in the case of the one-sided extraction in which the drain driving ICs are arranged on only one side of the liquid crystal display element as in this example, Since the pitch of the input wiring to the driving IC is extremely reduced, the problem of electrolytic corrosion of the terminals cannot be ignored, and this configuration is very effective. As described above, it is possible to reduce the resistance between the driving IC and the wiring DTM on the transparent insulating substrate SUB1 and improve the electrolytic corrosion resistance of the terminal DTM.

Although the present invention has been specifically described above based on the embodiments, the present invention is not limited to the above embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention. is there. For example, a transparent insulating substrate SUB
The passivation film PSV1 formed on the surface of No. 1 was used to form a wall having a predetermined width and height around the wiring d1 to which the bump BUMP is connected. However, another film is used to suppress the outflow of the conductive particles. May be formed. Further, in the above-described embodiment, an example in which the invention is applied to the active matrix type liquid crystal display device is shown, but it is also applicable to a simple matrix type liquid crystal display device. Further, in the above-mentioned embodiment, the example applied to the liquid crystal display device of the flip chip type is shown, but it is also applicable to the liquid crystal display device of other types. Furthermore, the present invention can be applied to various products that use an anisotropic conductive film to make electrical connections.

[0072]

As described above, according to the present invention,
When mounting the driving IC, the conductive particles of the anisotropic conductive film can be prevented from flowing out from under the bump of the driving IC, the remaining ratio of the conductive particles under the bump is increased, and the connection reliability is improved. it can.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a main part (a cross-sectional view taken along a cutting line 1-1 of FIG. 2) showing a state in which a bump BUMP of a driving IC and a wiring of a transparent insulating substrate SUB1 are connected by an anisotropic conductive film ACF. is there.

FIG. 2 is a transparent insulating substrate SU corresponding to the portion shown in FIG.
It is a principal part top view which shows the surface of B1.

FIG. 3 is a plan view showing how a driving IC is mounted on a transparent insulating substrate SUB1.

FIG. 4 is a sectional view taken along line AA of FIG. 3;

FIG. 5 is a plan view of an essential part of a transparent insulating substrate SUB1 around a portion where a drain driving IC is mounted and in the vicinity of a cutting line CT1 of the substrate.

6 is an enlarged detailed view of a main part (drain input side corner part) of FIG. 5;

FIG. 7 is an enlarged detailed view of a main part (drain output side corner part) of FIG. 5;

FIG. 8 is an exploded perspective view of a liquid crystal display module MDL.

FIG. 9: A foldable multilayer flexible substrate FPC2
Bending mounting method and multilayer flexible substrate FPC1
FIG. 3 is a perspective view showing a connecting portion between the FPC2 and the FPC2.

FIG. 10 is a cross-sectional view showing a part of a manufacturing process according to the present invention in which a driving IC and a flexible substrate FPC are mounted on a transparent insulating substrate SUB1.

11 is a diagram showing a manufacturing flow of the manufacturing method shown in FIG.

FIG. 12 is a flow chart of a cross-sectional view of a pixel portion and a gate terminal portion showing a manufacturing process of steps A to C on the substrate SUB1 side.

FIG. 13 is a flow chart of a cross-sectional view of the pixel portion and the gate terminal portion showing the manufacturing steps of steps D to E on the substrate SUB1 side.

FIG. 14 is a flow chart of a cross-sectional view of the pixel portion and the gate terminal portion showing the manufacturing steps of steps F to G on the side of the substrate SUB1.

FIG. 15 is a diagram showing part of a manufacturing process in which a conventional driving IC is mounted on a transparent insulating substrate SUB1.

[Explanation of symbols]

SUB1 ... Transparent insulating substrate, d1 ... Wiring (ITO film), P
SV1 ... passivation film, ACF2 ... anisotropic conductive film, BD ... binder, EP ... conductive particles, BUMP ... bumps, IC ... driving IC.

Claims (4)

[Claims] 1. A bump on the lower surface of a driving IC chip and a wiring provided on the surface of a transparent insulating substrate are connected by heating and pressing through an anisotropic conductive film in which a large number of fine conductive particles are dispersed,
In a flip-chip type liquid crystal display device in which the driving IC chip is directly mounted on the surface of the transparent insulating substrate, a means for suppressing the conductive particles from flowing out from under the bumps at the time of heating and pressing is provided. Characteristic liquid crystal display device. 2. A bump on the lower surface of a driving IC chip and a wiring provided on the surface of a transparent insulating substrate are connected by heating and pressing through an anisotropic conductive film in which a large number of fine conductive particles are dispersed,
In a flip-chip type liquid crystal display device in which the driving IC chip is directly mounted on the surface of the transparent insulating substrate, an end portion is inside the outline of the bump, and the conductive particles are introduced from below the bump during the heating and pressing. A liquid crystal display device, wherein a wall is provided to prevent the liquid from flowing out. 3. The bumps on the lower surface of the driving IC chip and the wirings provided on the surface of the transparent insulating substrate are connected by heating and pressing through an anisotropic conductive film in which a large number of fine conductive particles are dispersed,
In a flip-chip type liquid crystal display device in which the driving IC chip is directly mounted on the transparent insulating substrate surface, an opening smaller than the size of the bump is provided under the bump, and the heating is performed by an end portion of the opening. A liquid crystal display device, wherein an insulating film is provided to prevent the conductive particles from flowing out from under the bumps when pressure is applied. 4. The liquid crystal display device according to claim 3, wherein the insulating film is a passivation film.