JPH09238195A - Speed matching device for common line signal device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain the speed matching device applicable to diversified applications through the control of a processor by facilitating the connection of a signal data link between a common line signal device of an electronic exchange and a signal terminal equipment. SOLUTION: A time switch matching section 1 applies signal conversion to data and a signal received from a time switch and sends the converted data to a speed matching device 2. The speed matching device 2 applies speed conversion to the data under the control of a processor and sends the result to a signal terminal matching section 3. The signal terminal matching section 3 receiving the data subject to speed conversion buffers the data and outputs the data to a signal terminal equipment. The data from the signal terminal equipment conversely are buffered by the signal terminal matching section 3 and subject to inverse speed conversion by the speed matching device 2 and inverse signal conversion by the time switch matching section 1 and outputted to the time switch. Thus, the connection of the signal data link between the time switch and the signal terminal equipment is facilitated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a speed matching device for a common line signaling device, and more particularly to a speed matching device applied to a signal terminal management device embodied in a common line signaling device of an electronic exchange.

[0002]

2. Description of the Related Art Generally, in a common line signaling device, it is important to connect a signaling data link between signaling terminal devices.

A conventional speed matching device for a common line signal device is constructed at a board level by utilizing a large number of TTL (Transistor Transistor Logic) elements.

[0004]

However, the conventional speed matching device for the common line signaling device has a problem that matching with the signaling terminal device is not easy for each fixed time slot.

Therefore, it is an object of the present invention to provide a speed matching device which facilitates connection of a signal data link between a common line signaling device and a signaling terminal device and can be applied in various ways under the control of a processor.

[0006]

SUMMARY OF THE INVENTION To achieve the above object, the present invention provides a signal conversion device for converting data and signals input from a time switch to output, or reverse signal conversion of input data to convert the time switch. Output to the time switch matching means, the data input from the time switch matching means is subjected to speed conversion under the control of the processor and transmitted, or the input data is reverse speed converted and output to the time switch matching means. And a signal terminal for buffering the output data of the speed matching means and outputting it to the signal terminal device, or for buffering the data input from the signal terminal device and outputting it to the speed matching device. It is characterized in that a matching means is provided.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 1 to 3 of the accompanying drawings.

FIG. 1 is a block diagram of a speed matching device according to an embodiment of the present invention, FIG. 2 is a detailed block diagram of a time switch matching unit of FIG. 1, and FIG. 3 is a signal terminal matching unit of FIG. It is a detailed block diagram of.

The present invention comprises a time switch matching unit 1, a speed matching unit 2 and a signal terminal matching unit 3 as shown in FIG.

In the time switch matching section 1, the RS-449 level signals RXD +, RDX-, F are output from the time switch.
Input S +, FS-, CLK +, CLK- and input TTL (T
ransistor Transistor Logic) Level signal FS, CL
Each speed matching unit 2 of the speed matching unit 2 by converting into K, RDX
Commonly output to 1 to 2-4.

Further, the time switch matching section 1 receives the transmission data TXD of the TTL level signal and the time slot enable signals / TSEN1 to 4 from each of the speed matchers 2-1 to 2-4 and activates the time slot enable signal. Only the transmission data TXD of the selected speed matching device is converted into transmission data TXD +, TXD- of the RS-449 level signal and output to the time switch.

The operation of the time switch matching section 1 will be described in more detail with reference to FIG.

As shown in FIG. 2, the RS-449 level signal is transmitted to the T
RS-449 / TTL data conversion chip (μA96175) for converting to TL level signal is used to receive data RXD + of RS-449 level signal from the time switch.
RXD-, frame synchronization signals FS +, FS-, and clock signals CLK +, CLK- are input and converted into TTL level signals, and the frame synchronization signal FS and clock signal CLK are input.
The received data RXD is sent to each speed matching unit 2-1 of the speed matching unit 2.
Output to 2 to 4 in common.

Further, the transmission data TXD output from each of the speed matching devices 2-1 to 2-4 is commonly input to the 3-terminal buffer (74LS125) as shown in FIG.

That is, the 3-terminal buffer (74LS
125) inputs the time slot enable signals / TSEN1 to 4 from each of the speed matchers 2-1 to 2-4 and outputs only the transmission data TXD of the speed matcher in which the time slot enable signals are activated to TTL / RS-. Input to the 449 data conversion chip (μA96174).

The TTL / RS-449 data conversion chip (μA96174) is a 3-terminal buffer (74LS1).
The transmission data TXD from 25) is converted into an RS-449 signal, and the converted transmission data TXD +, TXD- is output to the time switch.

In the present invention, four speed matching devices 2-1 to 2-
4 is used, the operation is performed by controlling the time slot enable signals / TSEN1 to 4 in which one frame period is divided into four.

First time slot enable signal / TSEN1
Is from the first speed matching unit 2-1, the second time slot enable signal / TSEN2 is from the second speed matching unit 2-2, and the third time slot enable signal / TSEN3 is from the third speed matching unit 2
-4, the fourth time slot enable signal / TSEN4 is output from the fourth speed matching unit 2-4, and the time slot enable signal output from each of the speed matching units 2-1 to 2-4 is controlled by the processor. Is output by.

In the signal terminal matching unit 3, the transmission data and the transmission / reception clock output from the speed matching unit 2 are buffered and output to the signal terminal device, and the reception data input from the signal terminal device is buffered to the speed matching unit. Perform the function of outputting to 2.

As the transmission / reception clock used in the present invention, the clock signal 2.048 Mbps input from the time switch via the time switch matching unit 1 is used for each speed matching unit 2.
64 kbps or 56 kbp divided by -1 to 2-4
s clock signal, 64 kbps or 56 kb above
The selection of the ps clock signal is performed by each speed matching device 2-1 to 2-4.
Is performed under the control of the processor.

Since one speed matching device occupies eight time slots, the transmission / reception data from the signal terminal device is also connected to the speed matching devices 2-1 to 2-4 in units of eight signal links.

As shown in FIG. 3, the signal terminal matching unit 3 includes a chip (74F2444) for buffering data.
Use the above chip (74F2) for each signal unit.
444) Three of them are connected to one speed matching device, and a total of 12 chips are used to buffer each signal.

The signal terminal matching unit 3 uses the three data buffers (74F2444) as one unit, and the first speed matching unit 2-1 and SRXD0-7, STXD0-7, SCLK.
0 to 7 signals are connected to the second speed matching unit 2-2 by SR.
XD8-15, STXD8-15, SCLK8-15 signals are connected, and the third speed matching unit 2-3 is SRXD16.
~ 23, STXD16-23, SCLK16-23 signals are connected, and the fourth speed matching unit 2-4 is SRXD24-.
31, STXD24 to 31, and SCLK24 to 31 signals are respectively connected.

The speed matching unit 2 includes four speed matching units 2-1 to 2-1.
2-4, and the speed matching device is configured using an ED8902C chip.

The speed matching unit 2 uses the time switch to transmit data to the signal terminal device.
Then, the received data RXD, the clock signal CLK, and the frame synchronization signal FS are input, the transmission clock signal is converted and output to the signal terminal matching unit 3.

When data is transmitted from the signal terminal device to the time switch, the data S from the signal terminal matching unit 3 is sent.
RXD0 to 31 are received, a clock signal is converted, and time slot enable signal / TSEN1 to 4 and transmission data T
XD is output to the time switch matching unit 1, and the speed matching units 2-1 to 2-4 operate under the control of the processor control signals.

Considering the control signal of the processor for controlling each of the speed matching devices 2-1 to 2-4, A (1 in FIG.
To 3) are speed matching devices 2-1 to 2-4 as address signals.
It is used to select internal resistors and is therefore input to each speed matcher 2-1 to 2-4.

D0 to 7 are data signals and the speed matching device 2 is used.
Used to write data to the internal resistor to control -1 to 2-4 and to read the internal data of the resistor to know the status of each speed matching device 2-1 to 2-4. Input / output is performed to the matching devices 2-1 to 2-4.

The / DS signal is used as a data strobe signal indicating that the data on the data bus is currently valid, and the processor writes data to the speed matching units 2-1 to 2-4 or the speed matching units 2-1 to 2-. It is generated when data is read out from No. 4 and is input to each speed matching device 2-1 to 2-4.

The / RW signal is output as active / high by the processor as a read / write control signal when the processor reads data from the speed matching units 2-1 to 2-4, and then is output to the speed matching units 2-1 to 2-4. When writing data, it is output to active low by the processor and input to each speed matching unit 2-1 to 2-4.

The / DTACK signal is used as a data transmission confirmation signal to notify the completion of the writing operation or the reading operation when the processor writes or reads data in the speed matching device 2-1-2-4. 2-1 to 2-4
Output to the processor.

The / RESET signal is a speed matching device 2-1 to 2-2.
-4 is input to each of the speed matching units 2-1 to 2-4 as a signal output from the processor.

The / RASEL1 to 4 signals are output by the processor 4
As signals for selecting and selecting each of the speed matching devices 2-1 to 2-4, / RASEL1 signal is sent to the first speed matching device 2-1 and / RASEL2 signal is sent to the second speed matching device 2-.
2, the / RASEL3 signal is sent to the third speed matching unit 2-3,
The / RASEL4 signal is input to the fourth speed matching unit 2-4.

The / RAINT1 to 4 signals are used as signals for interrupting the processors from the respective speed matching units 2-1 to 2-4, and the / RAINT1 signal is the first speed matching unit 2-1.
Then, the / RAINT2 signal is output by the second speed matching unit 2-2,
The RAINT3 signal is sent to the third speed matching unit 2-3,
The NT4 signal is generated by the fourth speed matching unit 2-4 and input to the processor. The interrupt is generated by the time switch matching unit 1 from the frame synchronization signal FS or the clock signal C.
If LK is not input for a fixed time, each speed matching device 2-
1 to 2-4.

Therefore, according to the present invention, the four speed matching devices 2-1 are used.
~ 2-4 can be used to process 32 time slots and is connected to 32 signaling links with the signaling terminal equipment.

That is, the present invention is a hardware device necessary for transmitting / receiving the common line signal data which has been subjected to the level 2 protocol processing in the common line signal device through the time switch from 64 kbps or 56 kbps from the signal terminal device.
Of each speed matching unit 2 in the speed matching unit 2
After converting the speed to 2.048 Mbps through 1 to 2-4, the time switch matching unit 1 adjusts the signal level and transmits it to the time switch.

The information received from the time switch is 2.
The 048 Mbps signal data is matched with the signal level in the time switch matching unit 1, the speed is converted to 64 kbps or 56 kbps through each of the speed matching units 2-1 to 2-4, and then transmitted to the signal terminal device.

[0038]

As described above, according to the present invention, in the common line signaling device of the electronic exchange, the signal data link between the time switch and the signaling terminal device can be easily connected, and various effects can be obtained by controlling the processor. is there.

[Brief description of drawings]

FIG. 1 is a block diagram of a speed matching device according to the present invention.

FIG. 2 is a detailed configuration diagram of a time switch matching unit in FIG.

FIG. 3 is a detailed configuration diagram of a signal terminal matching unit of FIG.

[Explanation of symbols]

 1 Time switch matching unit 2 Speed matching unit 3 Signal terminal matching unit

Front Page Continuation (72) Inventor Sung-Sob, Republic of Korea Jeongsuk Gajoong Dong 161 Electronics and Telecommunication Research Institute (72) Inventor Igu Uk Republic of Korea Jeongsuk Gajoong Dong 161 Electronics and Telecommunications Research Institute (72) Invention Investor Kim Jin-tae Republic of Korea Daejeon Swok Gajeong-dong 161 Electronics and Telecommunications Research Institute

Claims (5)

[Claims] 1. A time switch matching means for signal-converting data and signals input from a time switch and outputting the converted data and signals, and inverse-signal converting the input data to output to the time switch. Speed matching means for speed-converting and transmitting input data under the control of a processor, and reverse speed-converting input data for output to the time switch matching means, and output of the speed matching means A common line signal device comprising a signal terminal matching means for buffering data and outputting it to the signal terminal equipment, or buffering data inputted from the signal terminal equipment and outputting it to the speed matching means. Speed matching device. 2. The common line signal device according to claim 1, wherein the signal terminal matching means comprises a plurality of buffers for buffering each input / output signal in units of eight signals. Speed matching device. 3. The speed matching means according to claim 1, wherein a plurality of speed matching devices are used, and each of the speed matching devices comprises 8 speed matching devices.
A speed matching device for a common line signal device, which is configured to expropriate one time slot. 4. The speed matching means according to claim 1, wherein the time switch matching means converts the received data of the RS-449 level signal, the frame synchronization signal and the clock signal input from the time switch into a TTL level signal. The transmission data and the time slot enable signal are input from the speed matching means, and only the transmission data of the speed matcher in which the time slot enable signal is activated is converted to the RS-449 signal level and output to the time switch. A common line signaling device speed matching device. 5. The speed matching means according to claim 1, wherein the clock 2.048 Mbps signal input from the time switch matching means is clocked at 64 kbps or 56 kbp under the control of a processor.
s signal is speed-converted and the inputted data is output to the signal terminal matching means, and the data of the signal terminal matching means is converted from the clock 64 kbps or 56 kbps signal into the clock 2.048 Mbps signal and is sent to the time switch matching means. A speed matching device for a common line signal device, characterized in that it is configured to output.