JPH09237792A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH09237792A JPH09237792A JP4367096A JP4367096A JPH09237792A JP H09237792 A JPH09237792 A JP H09237792A JP 4367096 A JP4367096 A JP 4367096A JP 4367096 A JP4367096 A JP 4367096A JP H09237792 A JPH09237792 A JP H09237792A
- Authority
- JP
- Japan
- Prior art keywords
- base
- junction
- emitter
- semiconductor device
- covered
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Bipolar Transistors (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、トランジスタ等の
半導体装置における信頼性の向上に関する。TECHNICAL FIELD The present invention relates to improvement of reliability in a semiconductor device such as a transistor.
【0002】[0002]
【従来の技術】NPNトランジスタ、PNPトランジス
タなどの半導体装置では、電流増幅率(hFE)の経時的
劣化を防止するために、最終工程付近で酸素雰囲気中に
おけるベーキング処理を行い、シリコン基板と表面のシ
リコン酸化膜との界面準位を増大させて、前記hFEの変
動を防止している。2. Description of the Related Art In semiconductor devices such as NPN transistors and PNP transistors, a baking process in an oxygen atmosphere is performed near the final step in order to prevent the current amplification factor (hFE) from deteriorating with time, and the silicon substrate and the surface are subjected to a baking process. The interface state with the silicon oxide film is increased to prevent the fluctuation of hFE.
【0003】図2は従来の半導体装置を示す断面図であ
る。同図において、1はコレクタ層となり、裏面に高濃
度層を具備するN型の半導体基板、2はP型のベース領
域、3はN+型のエミッタ領域、4はシリコン酸化膜、
5はアルミ電極である。ベース領域2とエミッタ領域3
は基板1表面から選択拡散によって形成されており、故
に基板1表面にPN接合6が露出し表面をシリコン酸化
膜4で被覆するプレーナ型の半導体装置となる。FIG. 2 is a sectional view showing a conventional semiconductor device. In the figure, 1 is a collector layer, an N type semiconductor substrate having a high concentration layer on the back surface, 2 is a P type base region, 3 is an N + type emitter region, 4 is a silicon oxide film,
Reference numeral 5 is an aluminum electrode. Base region 2 and emitter region 3
Is formed by selective diffusion from the surface of the substrate 1, and therefore the PN junction 6 is exposed on the surface of the substrate 1 and the surface is covered with the silicon oxide film 4 to provide a planar semiconductor device.
【0004】そして、アルミ電極5の形成が終了した後
に、基板1全体を800℃、酸素雰囲気中の熱処理を1
00分程度行うことにより、hFEの変動を防止してい
る。After the formation of the aluminum electrode 5 is completed, the entire substrate 1 is heat treated at 800 ° C. in an oxygen atmosphere for 1 hour.
By performing the operation for about 100 minutes, the fluctuation of hFE is prevented.
【0005】[0005]
【発明が解決しようとする課題】しかしながら、酸素雰
囲気中のベーキングはベース・エミッタ接合に作用して
hFEの劣化防止という作用を生じるが、ベース・コレク
タ接合に作用するとベース・コレクタ接合の空乏層の広
がりを抑制するため、トランジスタのコレクタ・ベース
間耐圧が低下するという副作用が発生する欠点があっ
た。However, baking in an oxygen atmosphere acts on the base-emitter junction.
Although it has the effect of preventing hFE deterioration, it has the drawback that when it acts on the base-collector junction, it suppresses the expansion of the depletion layer at the base-collector junction, which causes the side-effect of lowering the collector-base breakdown voltage of the transistor. .
【0006】[0006]
【課題を解決するための手段】本発明は上記従来の課題
に鑑みなされたもので、トランジスタのベース・コレク
タ接合の上部をシリコン窒化膜で被覆し、エミッタ・ベ
ース接合にのみ酸素ベーキングを作用させることによ
り、耐圧の低下がなくしかも電流増幅率の経時変化を防
止できる半導体装置の製造方法を提供するものである。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art. The upper part of the base / collector junction of a transistor is covered with a silicon nitride film, and oxygen baking is applied only to the emitter / base junction. As a result, the present invention provides a method for manufacturing a semiconductor device, in which the breakdown voltage does not decrease and the current amplification factor can be prevented from changing over time.
【0007】[0007]
【発明の実施の形態】以下に本発明の一実施の形態を図
面を参照しながら詳細に説明する。図1は本発明の半導
体装置を示す断面図である。同図において、11はコレ
クタ層となり、裏面に高濃度層を具備するN型のシリコ
ン半導体基板、12はP型のベース領域、13はN+型
のエミッタ領域、14はシリコン酸化膜、15はアルミ
電極である。DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a sectional view showing a semiconductor device of the present invention. In the figure, 11 is a collector layer, an N-type silicon semiconductor substrate having a high concentration layer on the back surface, 12 is a P-type base region, 13 is an N + -type emitter region, 14 is a silicon oxide film, and 15 is aluminum. It is an electrode.
【0008】ベース領域12とエミッタ領域13は、基
板11表面に形成したシリコン酸化膜を通常のホトエッ
チング技術によって開口し、該酸化膜を選択マスクとし
た選択拡散により形成する。このようにしてベース拡
散、エミッタ拡散を行うと、ベース・コレクタ接合1
6、およびベース・エミッタ接合17が基板11の表面
で終端するプレーナ構造となる。The base region 12 and the emitter region 13 are formed by selectively diffusing the silicon oxide film formed on the surface of the substrate 11 by a normal photoetching technique and using the oxide film as a selective mask. When base diffusion and emitter diffusion are performed in this way, the base-collector junction 1
6, and the base-emitter junction 17 has a planar structure terminating at the surface of the substrate 11.
【0009】次いで、基板11表面のシリコン酸化膜1
4の上に、膜厚1000Å程度のシリコン窒化膜18を
CVD法により堆積し、ホトエッチングにより、ベース
・コレクタ接合16の上部を被覆し、ベース・エミッタ
接合の上部を被覆しないようにパターニングする。シリ
コン窒化膜18は少なくともベース・コレクタ接合17
の上部を被覆していればよく、コレクタとなる領域全て
を被覆する必要は必ずしも無い。Next, the silicon oxide film 1 on the surface of the substrate 11
4, a silicon nitride film 18 having a film thickness of about 1000 Å is deposited by the CVD method, and is patterned by photoetching so as to cover the upper portion of the base-collector junction 16 and not the upper portion of the base-emitter junction. The silicon nitride film 18 is at least the base-collector junction 17
It suffices that the upper part of the collector be covered, and it is not always necessary to cover the entire region that becomes the collector.
【0010】その後、ベース領域12上およびエミッタ
領域13上のシリコン酸化膜14を開口してコンタクト
ホールを形成し、アルミニウムまたはアルミニウム・シ
リコン合金をスパッタまたは蒸着手法により堆積し、こ
れをホトエッチングでパターニングする事によりベース
とエミッタの電極15を形成する。該工程で外部接続用
の電極パッドの形成も行う。Thereafter, the silicon oxide film 14 on the base region 12 and the emitter region 13 is opened to form a contact hole, and aluminum or aluminum-silicon alloy is deposited by sputtering or vapor deposition method, and this is patterned by photoetching. By doing so, the base and emitter electrodes 15 are formed. Electrode pads for external connection are also formed in this step.
【0011】そして、アルミ電極15のアニール(合金
化成長)を行った後、最終工程として、ウァハを酸素雰
囲気中、700〜800℃、約100分のベーキング処
理を行う。この工程で、ベース・エミッタ接合16付近
のシリコン・酸化膜界面では界面準位を増大させる。こ
の界面準位は、外的要因によるイオン電荷等をトラップ
して安定化させる作用を持ち、この準位を増大すること
で表面状態がより安定するので、電流増幅率hFEの経時
的劣化を防止できる。一方、ベース・コレクタ接合17
付近のシリコン・酸化膜界面ではシリコン窒化膜18が
酸素をブロッキングするので前記界面準位の増大が無
い。ベース・コレクタ接合17付近の界面準位は、ベー
ス・コレクタ接合に生じる空乏層の広がりを、界面付近
で抑制する方向の作用を示すので、該界面準位の増大を
抑制することにより、ベース・コレクタ間耐圧Vcbo
の低下を防止できる。After the aluminum electrode 15 is annealed (alloying growth), as a final step, the wafer is baked in an oxygen atmosphere at 700 to 800 ° C. for about 100 minutes. In this step, the interface state is increased at the silicon / oxide film interface near the base / emitter junction 16. This interface level has the function of trapping and stabilizing ionic charges due to external factors, and increasing the level stabilizes the surface state, preventing the current amplification factor hFE from deteriorating over time. it can. On the other hand, base-collector junction 17
Since the silicon nitride film 18 blocks oxygen at the nearby silicon / oxide film interface, the interface level does not increase. The interface level near the base-collector junction 17 acts to suppress the expansion of the depletion layer that occurs in the base-collector junction near the interface. Therefore, by suppressing the increase in the interface level, Inter-collector breakdown voltage Vcbo
Can be prevented.
【0012】[0012]
【発明の効果】以上に説明した通り、本発明によれば、
べース・エミッタ接合16にのみ酸素ベーキングを行う
ので、電流増幅率hFEの経時的劣化が無く、しかもベ
ーキングによる耐圧劣化のないトランジスタを製造する
ことができる。さらに、シリコン窒化膜18は製品化後
可動イオンの進入を防止するので、製品の信頼性を向上
できる。As described above, according to the present invention,
Since oxygen baking is performed only on the base-emitter junction 16, it is possible to manufacture a transistor in which the current amplification factor hFE is not deteriorated with time and the breakdown voltage is not deteriorated by baking. Furthermore, since the silicon nitride film 18 prevents mobile ions from entering after being manufactured, the reliability of the product can be improved.
【図1】本発明を説明するための段面図である。FIG. 1 is a step view for explaining the present invention.
【図2】従来例をを説明するための段面図である。FIG. 2 is a step view for explaining a conventional example.
Claims (1)
面に逆導電型のベース領域を形成し、該ベース領域の表
面に一導電型のエミッタ領域を形成し、最終工程付近で
酸素雰囲気中におけるベーキング処理を行う半導体装置
の製造方法において、 前記コレクタと前記ベース領域とのPN接合の上部をシ
リコン窒化膜で被覆し、前記ベース領域と前記エミッタ
領域とのPN接合の上部を前記シリコン窒化膜で被覆し
ない状態で前記ベーキング処理を行うことを特徴とする
半導体装置の製造方法。1. A reverse-conductivity-type base region is formed on the surface of a single-conductivity-type semiconductor layer to be a collector, and a single-conductivity-type emitter region is formed on the surface of the base region. In the method of manufacturing a semiconductor device, the upper part of the PN junction between the collector and the base region is covered with a silicon nitride film, and the upper part of the PN junction between the base region and the emitter region is covered with the silicon nitride film. A method of manufacturing a semiconductor device, wherein the baking process is performed in a state where the semiconductor device is not covered with.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4367096A JPH09237792A (en) | 1996-02-29 | 1996-02-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4367096A JPH09237792A (en) | 1996-02-29 | 1996-02-29 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH09237792A true JPH09237792A (en) | 1997-09-09 |
Family
ID=12670287
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4367096A Pending JPH09237792A (en) | 1996-02-29 | 1996-02-29 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH09237792A (en) |
-
1996
- 1996-02-29 JP JP4367096A patent/JPH09237792A/en active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS61180482A (en) | L-high speed manufacturing method for fast bipolar analog large integrated circuit | |
JPH0430534A (en) | Manufacture of semiconductor device | |
JPH09237792A (en) | Manufacture of semiconductor device | |
US3821779A (en) | Semiconductor device with high conductivity and high resistivity collector portions to prevent surface inversion | |
JPH0254662B2 (en) | ||
JP3877459B2 (en) | Manufacturing method of semiconductor device | |
JP3157203B2 (en) | High voltage semiconductor device | |
US3959810A (en) | Method for manufacturing a semiconductor device and the same | |
JPH0693459B2 (en) | High speed bipolar transistor and manufacturing method thereof | |
JPS60113967A (en) | Manufacture of semiconductor device | |
JP3302742B2 (en) | Method of manufacturing lateral PNP transistor | |
JPH0318738B2 (en) | ||
JPH0437581B2 (en) | ||
JPS6136935A (en) | Manufacture of semiconductor device | |
JPH0661237A (en) | Semiconductor device | |
JPS596574A (en) | Manufacture of semiconductor device | |
JPS61108169A (en) | Semiconductor device | |
JPH0376023B2 (en) | ||
JPH0745629A (en) | Semiconductor device | |
JPH10189786A (en) | Semiconductor integrated circuit device | |
JPH0611051B2 (en) | Method for manufacturing semiconductor device | |
JPS6136934A (en) | Manufacture of semiconductor device | |
JPH06181215A (en) | Semiconductor integrated circuit | |
JPH1154505A (en) | Manufacture of semiconductor device | |
JPH0469938A (en) | Semiconductor device and manufacture thereof |