JPH09237791A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a bad influence on a substrate and/or on transistor characteristics, also in case where insulating material side wall spacers for preventing short circuit are formed as to a semiconductor device including a bipolar transistor. SOLUTION: (1) Side wall spacers 25, 26 are formed between emitter wiring 29, 30 and base wiring 27 for insulating between them, and these spacers consist of a fourth insulating material film 26 (a nitride film) on the base wiring side and a fifth insulating film 25 (silicon dioxide) on the emitter wiring side, and the fourth insulating material film 26 consists of a material capable of taking an etching selection ratio with both of a substrate 11 and the fifth insulating film 25. (2) As to the spacers, the fourth insulating material film, capable of taking the etching selection ratio with the substrate, is formed on the substrate surface, and further the fifth insulating film, capable of taking the etching selection ratio with this, is formed thereon, and the fifth insulating film is selectively etched together with the fourth insulating material film in this state to form the spacers.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a semiconductor device including a bipolar transistor having a collector region, a base region and an emitter region and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, semiconductor devices have been required to operate at higher speed. Regarding the bipolar transistor, one of means for increasing the speed is to prevent formation of a parasitic element and reduce the influence of the parasitic element. As a concrete means thereof, miniaturization of a transistor is performed to reduce a portion unnecessary for transistor operation. For miniaturization, a pattern is made small and a self-alignment technique that does not require a margin for pattern alignment is used.

As an example of actually using the self-alignment technique for a bipolar transistor, there is a two-layer polysilicon self-alignment bipolar transistor as shown in FIG. The components similar to the reference numerals used in FIG. 1 and subsequent figures showing the embodiment of the invention are shown). This bipolar transistor
The sidewall spacer 2 which has a collector region, a base region, and an emitter region in the semiconductor substrate 11 and insulates the emitter wirings 29, 30 from the base wiring 27.
5 ′ is formed on the side wall of the base wiring 27. In the conventional structure, this sidewall spacer 25 'is
It is made of a silicon oxide film (SiO ₂ ).

That is, in the above bipolar transistor, when forming the structure, a short circuit between the polysilicon and the base wiring 27 is prevented when the polysilicon (polysilicon indicated by reference numeral 29) forming the emitter is formed. In order to protect the insulating film, a sidewall spacer 25 'is formed of an insulating oxide film after forming the emitter contact.

Conventionally, this sidewall spacer 2
During etching for forming 5 ', the spacer 2
Since the etching selectivity between the insulating oxide film for forming 5'and the substrate 11 is low, the substrate 11 is scraped by this etching, and the spacers 25 'are implanted to form the base in the step before forming. There is a problem that desired transistor characteristics may not be obtained because the impurities forming the intrinsic base are removed.

Even if the base implantation conditions are determined on the assumption of the amount of abrasion due to the above etching, the etching selectivity of the substrate varies within the wafer surface, so that the portion where the desired characteristics are obtained is limited within the wafer surface. Will end up.

[0007]

The present invention has solved the above-mentioned problems of the prior art and was able to prevent adverse effects on the substrate and transistor characteristics even when forming an insulating material sidewall spacer for preventing short circuits. An object is to provide a semiconductor device and a manufacturing method thereof.

[0008]

In order to achieve the above object of the present invention, a semiconductor device of the present invention is a semiconductor device including a bipolar transistor having a collector region, a base region and an emitter region in a semiconductor substrate. A side wall spacer for insulating the base wiring from each other is formed on the side wall of the base wiring, and the side wall spacer includes a fourth insulating material film on the base wiring side and a fifth insulating film on the emitter wiring side. And the fourth insulating film is made of a material having an etching selection ratio with both the semiconductor substrate and the fifth insulating film.

In order to achieve the above object of the present invention,
A method of manufacturing a semiconductor device according to the present invention is the method of manufacturing a semiconductor device including a bipolar transistor having a collector region, a base region, and an emitter region, and a step of forming a conductive film serving as a base wiring on the semiconductor substrate, Patterning step, forming a fourth insulating material film on the surface of the semiconductor substrate that has an etching selection ratio with the semiconductor substrate, and forming the fourth insulating material film on the surface of the fourth insulating material film. And a step of forming a fifth insulating film having an etching selectivity ratio, and the fifth insulating film is etched at a selective ratio with the fourth insulating material film to form a sidewall spacer on a sidewall of the conductive film. Take a configuration that includes steps.

According to the present invention, since the side wall spacer for insulating between the emitter wiring and the base wiring is composed of the fourth insulating material film on the base wiring side and the fifth insulating film on the emitter wiring side, The side wall spacer made of a single material in the related art has a higher insulation property, and reliable insulation between the emitter wiring and the base wiring can be achieved.

Further, according to the present invention, the sidewall spacer for insulating between the emitter wiring and the base wiring is the fourth insulating material film on the base wiring side and the fifth insulating material film on the emitter wiring side.
First insulating film is formed on the surface of the semiconductor substrate, a fourth insulating material film having an etching selection ratio with the semiconductor substrate is formed, and the fourth insulating material film is further formed on the surface of the fourth insulating material film. Forming a fifth insulating film having an etching selection ratio with that of the insulating material film, and in that state, selectively etching the fifth insulating film with the fourth insulating material film to form a sidewall of the conductive film. By forming the sidewall spacers, the semiconductor substrate is typified by the fact that the fourth insulating material film protects the substrate surface from etching and the impurities forming the intrinsic base are removed. Is prevented.

Therefore, according to the present invention, the problems of the prior art can be solved and the adverse effect on the substrate and the transistor characteristics can be prevented even when the insulating material side wall spacer for preventing the short circuit is formed. Provided are a semiconductor device in which the influence of parasitic elements is reduced and a method for manufacturing the same.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will be described below. However, as a matter of course, the present invention is not limited to the embodiments described below.

Embodiment 1 In this embodiment, in a two-layer polysilicon self-aligned bipolar transistor, a sidewall that insulates and separates a base and an emitter from each other when an emitter is formed inside an emitter contact portion in a self-aligned manner. By using a two-layer structure of a nitride insulating film and an insulating oxide film, a structure is adopted in which the withstand voltage between the emitter and the base can be secured and the digging of the substrate can be suppressed when the sidewall is formed.

The bipolar transistor of this example has the structure shown in FIG. That is, the bipolar transistor has a collector region, a base region, and an emitter region in a semiconductor substrate 11 (a silicon substrate in this example), and emitter wirings 29 and 30 (reference numeral 29 is a wiring portion made of polysilicon and reference numeral 30 is a silicide). Is formed of a so-called polycide structure in this example) and the base wiring 27, sidewall spacers 25 and 26 are formed on the side wall of the base wiring 27 to insulate the two. As shown, the sidewall spacers 25 and 26 are composed of a fourth insulating material film 26 on the base wiring 27 side and a fifth insulating film 25 on the emitter wiring 29, 30 side. The fourth insulating material film 26 is made of a material having an etching selection ratio with both the semiconductor substrate 11 and the fifth insulating film 25. Specifically, in this example, the fourth insulating material film 26 is a nitride film (silicon nitride) and the fifth insulating film 25 is an oxide film (silicon dioxide). Also,
In this example, an oxide film (silicon dioxide) is formed as the third insulating film 28 on the base wiring 27, so that the fourth insulating material film 26 (nitride film, particularly silicon nitride) is further formed. The third insulating film (oxide film, especially silicon dioxide) can also have an etching selection ratio. Since the third insulating film 28 on the base wiring 27 and the fourth insulating material film 26 have an etching selection ratio, the third insulating film 28 on the base wiring 27 can be thinned and flattened. It is advantageous in terms.

A specific procedure for forming the bipolar transistor in this example will be described below with reference to FIGS. As shown in FIG. 2, first, here, Sb is ion-implanted into the p-type silicon substrate 11 and diffused to form an N ⁺ diffusion layer 12, on which Si is epitaxially grown to have a thickness of 1 μm and a specific resistance of 1 Ω. A cm type n-type Si epitaxial layer 13 is formed. Next, a known selective oxidation method using Si ₃ N ₄ as a mask, for example, a thickness of 300 n is performed.
A thermal oxide film of m is formed and used as the element isolation region 14. The element isolation region 14 forms a first insulating film (here, an oxide film, particularly silicon dioxide).

As shown in FIG. 3, the collector lead-out portion 15
With respect to, the collector extraction layer 16 is formed by ion-implanting phosphorus into the Si epitaxial layer 13 of the collector extraction portion 15 using the photoresist as a mask.

After that, an insulating oxide film 17 which can be used together with the CMOS transistor process is formed on the entire surface of the substrate 11 to have a thickness of, for example, 140 nm. This insulating oxide film 17 forms a second insulating film (here, an oxide film, particularly silicon dioxide). Next, using the photoresist as a mask, the insulating oxide film 17 on the emitter contact portion 18 is removed by etching to expose the surface of the Si epitaxial layer 13 as shown in FIG.

Next, as shown in FIG. 4, a polysilicon layer 19 serving as a base wiring is formed on the entire surface of the substrate, for example, to a thickness of 130 nm, and an insulating oxide film 20 (SiO ₂ ) used for separation from the emitter wiring is formed on the entire surface. For example, a film having a thickness of 250 nm is formed. This insulating oxide film 20 constitutes the third insulating film.

Next, as shown in FIG. 5, the polysilicon layer 19 used for the base wiring is the Si epitaxial layer 13.
The insulating oxide film 20 and the polysilicon film 19 are etched using the photoresist as a mask to expose the surface of the Si epitaxial layer 13 so that the portion in contact with is left in the emitter contact portion 18. At this time, the portion of the base wiring forming polysilicon layer 19 in contact with the Si epitaxial layer 13 serves as a diffusion source of the graft base 22 shown in the figure. Subsequently, an oxide film 10 nm including the exposed surface of the Si epitaxial layer 13 is formed on the entire surface of the substrate, and using this as a mask, an impurity BF ₂ ⁺ for forming the intrinsic base 21 is ion-implanted. After the ion implantation, the oxide film mask is removed by etching. As described above, FIG.
Structure (oxide film SiO used as a mask for ion implantation)
₂ is not shown).

Next, as shown in FIG. 6, first, on the entire surface of the substrate, an insulating material 2 having an etching selection ratio with both the Si epitaxial layer 13 and the insulating oxide film 24 to be formed next.
For example, SiN is deposited to a thickness of 50 nm. Then, an insulating oxide film 24 (SiO ₂ ) is deposited to a thickness of 400 nm, for example.

Next, as shown in FIG. 7, a sidewall spacer 25 is formed on the sidewall of the emitter contact portion 18 by etching the entire surface of the insulating oxide film 24. At this time, since the underlying insulating material 23 (SiN) has an etching selection ratio with the insulating oxide film 24, it is possible to suppress the amount of abrasion of the underlying.

Then, as shown in FIG.
3 (SiN) is entirely etched to form insulating material portions 26 (SiN) below and beside the sidewall spacers 25.
To remove. At this time, the emitter contact portion 18
Since the sidewall spacers 25 and the underlying Si epitaxial layer 13 have an etching selection ratio with the insulating material 23 (SiN), even if the etching time is taken into consideration and the etching time is lengthened and overetching is performed, Spacer 25 and underlying Si
It is possible to suppress film loss and digging (cutting) of the epitaxial layer 13.

Further, when the insulating material 23 (SiN) capable of obtaining the etching selection ratio as in this example is the base of the insulating oxide film 24, the side wall spacer 25 is formed on the side wall of the emitter contact portion 18 and then the base is continuously formed. Insulation material 2
When 3 (SiN) is shaved to expose the surface of the Si epitaxial layer 13, the etching residue is eliminated as compared with the case where only the insulating oxide film (SiO ₂ ) is used as the film species forming the sidewall spacer 25. The amount of abrasion of the underlying Si epitaxial layer 13 at the time of over-etching is smaller than that of the thick insulating oxide film S
Since iN requires less over-etching amount,
The amount of abrasion of the underlying Si epitaxial layer 13 can be further suppressed, and the variation in the amount of digging in the wafer surface can be reduced unlike the conventional case.

Next, as shown in FIG. 9, the base wiring forming polysilicon layer 19 and the insulating oxide film 20 are etched with the photoresist used as a mask to leave the emitter contact portion 18, and thereby the base wiring 27 and the base wiring 27 are etched. An insulating film 28 (oxide film) to be laminated on the upper layer is formed.

Then, as shown in FIG. 10, a polysilicon film 29 having a thickness of, for example, 100 nm is formed on the entire surface of the substrate, and then WS.
The silicon compound 30 such as i is formed to have a thickness of 70 nm, for example.
From the polysilicon film 29 to the Si epitaxial layer 13
Impurities are thermally diffused into and form the emitter. In this example, the CMOS transistor process and the bipolar transistor process are commonly used for the processes after the formation of the polysilicon film 29 and the silicon compound 30, so that the two processes are matched with each other.

After that, as shown in FIG. 11, etching is performed using a photoresist in such a manner that the polysilicon film 29 and the silicon compound 30 in the portion to be the wiring of the emitter are left.

Further, the surface of the substrate is first flattened in order to obtain terminals for electrical characteristic evaluation. As shown in FIG. 1, after the interlayer insulating oxide film 37 is formed to a thickness of 150 nm, for example, BPSG is formed to a thickness of 600 nm as a planarization reflow film 38, and reflow is performed to planarize the film.

Finally, each contact hole of the emitter 31, the base 32, and the collector 33 is formed using a photoresist mask. After forming the barrier metal 34 by sputtering, a tungsten film is formed to a thickness of 800 nm, for example. Then, the entire surface of the substrate is etched to leave tungsten only in the contact portion to form the embedded plug 35. Then, an aluminum alloy film is formed, and etching is performed using a photoresist mask so that the aluminum alloy does not remain except the upper portion of the contact. As described above, the emitter electrode 36E and the base electrode 36 made of aluminum
B, collector electrode 36C, emitter 31, base 3
2, FIG. 1 formed on each collector 33.
Is obtained.

In this example, as described above, in the two-layer polysilicon self-aligned bipolar transistor, the insulating oxide film 24 and the substrate 11 are formed as the base of the insulating oxide film 24 which becomes the spacer 25 formed on the side wall of the emitter contact.
A nitride film is formed as the insulating material 23 capable of providing an etching selection ratio with both (especially the epitaxial layer 13) (FIG. 6).

When the sidewall spacers 25 are formed, the insulating oxide film 24 is first selectively etched to form the spacers 25 of the insulating oxide film 24 and leave the underlying nitride film insulating material 23 as described above. (Fig. 7). Next, the nitride film insulating material 23 exposed on the surface is removed by selective etching (FIG. 8). As a result, spacers are formed on the sidewalls of the emitter contacts 18 in a structure in which the nitride insulating material 26 is sandwiched between the insulating oxide spacer 25 and the emitter contact 18, and between the insulating oxide spacer 25 and the substrate 11. (FIG. 9 to FIG. 11, FIG. 1).

In this example, by applying the present invention as described above, in addition to the fact that the emitter can be formed in a self-aligned manner, the spacer 2 is formed on the emitter contact.
When forming 5, the nitride film insulating material 23 having an etching selection ratio with the substrate 11 is removed, so that the removal of impurities forming the base due to the digging of the substrate does not occur.

Further, even when the selection ratio of the nitride film insulating material 23 to the substrate 11 cannot be made large, a thin nitride film is used so that the underlying nitride film insulating material 23 remains when the spacer 25 of the insulating oxide film 24 is formed. For example, the nitride film can be made thinner than the insulating oxide film thickness required when the spacer 25 is formed only by the insulating oxide film 24. Therefore, even if there is a variation in the selection ratio with the substrate when removing the nitride film, variation in substrate digging is caused. Can be kept small.

Further, by applying the present invention, in the structure of this example, between the spacer 25 of the insulating oxide film and the emitter contact, the spacer 25 of the insulating oxide film and the substrate 11 are provided.
Since the nitride film insulating material 26 is sandwiched between and, a spacer consisting of two layers of a nitride film and an insulating oxide film is formed on the side wall of the emitter contact, and a good insulating property can be obtained. High insulation resistance between the wiring and the emitter wiring can be obtained.

[0035]

As described above in detail, according to the present invention,
With respect to a semiconductor device including a bipolar transistor, it is possible to provide a semiconductor device capable of preventing an adverse effect on a substrate and an adverse effect on transistor characteristics even when an insulating material sidewall spacer for preventing a short circuit is formed, and a manufacturing method thereof.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment.

2A to 2C are sectional views showing the steps of the first embodiment in order (1).

FIG. 3 is a sectional view sequentially showing the steps of the first embodiment (2).

FIG. 4 is a sectional view showing the steps of the first embodiment in order (3).

FIG. 5 is a cross-sectional view showing the steps of the first embodiment in order (4).

FIG. 6 is a sectional view showing the steps of the first embodiment in order (5).

FIG. 7 is a sectional view sequentially showing the steps of the first embodiment (6).

FIG. 8 is a sectional view sequentially showing the steps of the first embodiment (7).

FIG. 9 is a sectional view sequentially showing the steps of the first embodiment (8).

FIG. 10 is a sectional view showing the steps of the first embodiment in order (9).

FIG. 11 is a cross-sectional view showing the steps of the first embodiment in order (10).

FIG. 12 is a cross-sectional view showing a general structure of a two-layer polysilicon self-aligned bipolar transistor.

[Explanation of symbols]

11 ... Semiconductor substrate (silicon substrate), 12 ... Diffusion layer, 13 ... Epitaxial layer, 14 ... Element isolation region (first insulating film, LOCOS), 16 ... Collector extraction layer, 17 ... second insulating film, 18 ...
Emitter contact portion, 19 ... Polysilicon layer (for forming base wiring), 20 ... Insulating oxide film (third insulating film), 21 ... Genuine base, 22 ... Graft base, 23 ... Insulating material (fourth insulating material film, nitride film), 24 ... Insulating oxide film (fifth insulating material film), 2
5 ... Sidewall spacer composed of fifth insulating film (oxide film), 26 ... Sidewall spacer composed of fourth insulating material film (nitride film), 27
... Base wiring, 28 ... Insulating oxide film (on the base wiring) (insulating film composed of a third insulating film (oxide film)), 29 ... Polysilicon film (for forming emitter wiring) , 30 ... Silicon compound (silicide, (for forming emitter wiring), 31 ... Emitter contact, 3
2 ... Base contact, 34 ... Barrier metal,
35 ... Embedded plug (tungsten plug), 3
3 ... Collector contact, 36E ... Emitter electrode, 36B ... Base electrode, 36C ... Collector electrode.

Claims (6)

[Claims] 1. A semiconductor device including a bipolar transistor having a collector region, a base region and an emitter region on a semiconductor substrate, wherein a sidewall spacer for insulating between an emitter wiring and a base wiring is formed on a sidewall of the base wiring. At the same time, the sidewall spacer is composed of a fourth insulating material film on the base wiring side and a fifth insulating film on the emitter wiring side, and the fourth insulating material film includes a semiconductor substrate and a fifth insulating film. A semiconductor device characterized by being made of a material having an etching selection ratio with respect to both. 2. A third insulating film is formed on the base wiring, and the fourth insulating material film is made of a material having an etching selection ratio with the third insulating film. The semiconductor device according to claim 1. 3. The semiconductor device according to claim 1, wherein the semiconductor substrate is a silicon substrate, the fourth insulating material film is a nitride film, and the fifth insulating film is an oxide film. 4. A method of manufacturing a semiconductor device including a bipolar transistor having a collector region, a base region and an emitter region, a step of forming a conductive film as a base wiring on the semiconductor substrate, and a step of patterning the conductive film. A step of forming a fourth insulating material film on the surface of the semiconductor substrate that has an etching selectivity with the semiconductor substrate; and a step of forming an etching selectivity with the fourth insulating material film on the surface of the fourth insulating material film. A step of forming a removable fifth insulating film, and a step of selectively etching the fifth insulating film with the fourth insulating material film to form a sidewall spacer on the side wall of the conductive film. A method for manufacturing a characteristic semiconductor device. 5. A step of forming a collector of a bipolar transistor on one main surface of the semiconductor substrate, a step of forming a first insulating film on the main surface of the semiconductor substrate, and a surface of the first insulating film. A step of forming a second insulating film on the base, and a step of removing the first and second insulating films of the base contact portion which is a contact portion between the graft base formed around the intrinsic base and the base lead wiring. In a random order, and forming a first conductive film on one main surface of the semiconductor substrate and filling the base contact portion with a first conductive film; and forming a first conductive film on the surface of the first conductive film. A step of forming a third insulating film, and an emitter capacitor which is a contact portion between the emitter formed in the intrinsic base inside the base contact and the emitter lead wiring. Removing the third insulating film and the first conductive film in the active portion, introducing a first impurity serving as an intrinsic base from the emitter contact portion, and forming the semiconductor substrate on the surface of the semiconductor substrate. And a step of forming a fourth insulating material film having an etching selectivity ratio, and a step of forming a fifth insulating film having an etching selection ratio with the fourth insulating material film on the surface of the fourth insulating material film. And a step of forming a sidewall spacer by etching the fifth insulating film in a selective ratio with the fourth insulating material film; and selectively etching the fourth insulating material film with the semiconductor substrate. A step of forming the emitter contact, a step of removing the third insulating film and the first conductive film on one main surface of the semiconductor substrate, and a step of forming a second conductive film on one main surface of the semiconductor substrate. Formation That step a method of manufacturing a semiconductor device according to claim 4, characterized in that it comprises the step of introducing a second impurity serving as the emitter through the second conductive film from the emitter contact. 6. The fourth insulating material film is further made of a material having an etching selection ratio with the third insulating film, and when forming the emitter contact, the fourth insulating material film is formed.
6. The method of manufacturing a semiconductor device according to claim 5, wherein the insulating material film is selectively etched with both the semiconductor substrate and the third insulating film.