JPH09233146A - Digital information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of elements switched simultaneously because of avoiding simultaneous switching operation of a signal output section of the information processing unit processing digital information as a major factor of various noise such as power/earth noise and ground bounce. SOLUTION: The information processing section has plural signal input sections 400-1-400-n, a detection circuit 411 that predicts whether or not state transition takes place in a prescribed timing as to a 1st signal received from the plural signal input sections 400-1-400-n and provides the output of an instruction signal to instruct to apply signal conversion to change the state of the 1st signal, and a signal conversion circuit 412 that receives the 1st signal and the instruction signal and applies signal conversion to the 1st signal based on the instruction signal and provides the output of the result as a 2nd signal. The detection circuit 411 sends an instruction signal and sends a control signal denoting it that the 2nd signal is a signal subject to signal conversion to a receiver side device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital information processing apparatus, and more particularly to a digital information processing apparatus that exchanges digital data in parallel.

[0002]

2. Description of the Related Art In an information processing apparatus that handles digital information, the main cause of various noises such as power / ground noise and ground bounce is the simultaneous switching operation of the elements in the apparatus, especially the simultaneous switching operation of the signal output section. is there. Therefore, it is effective to reduce the number of elements simultaneously switching in the device to reduce these noises. As a conventional noise reduction method, there is a method of previously multiplexing a plurality of output signals, reducing the number of output sections, and limiting the number of simultaneous operations. As another conventional noise reduction method, the rising edge of the signal at the output section /
There is a method to delay the fall time (slew rate control).

[0003]

However, there are problems in both of the two conventional methods described above. In the method of multiplexing the output signals and reducing the number of output sections, the circuit is speeded up by the multiplexing, which makes the design difficult,
Further, the high-speed element is generally expensive, which leads to an increase in cost. The method of delaying the rise / fall time of the signal at the output section causes a decrease in the transmission speed, and the rise / fall time is further reduced by using the characteristics of the transistor.
Since the fall time is controlled, the characteristics may vary due to factors such as temperature, and the expected noise reduction effect may not be obtained.

[0004]

In order to solve the above-mentioned problems, a digital information processing apparatus according to a first aspect of the present invention relates to a plurality of signal input sections and a first signal input from each of the plurality of signal input sections. Then, it is predicted whether a state transition will occur at a predetermined timing, and when it is detected that the number of the first signals in which the state transition occurs is larger than a predetermined number,
A detection circuit for sending an instruction signal for instructing to perform signal conversion for changing the state of the first signal, the first signal and the instruction signal are input, and a signal is sent to the first signal based on the instruction signal. And a signal conversion circuit that performs conversion and outputs as a second signal. Here, when the detection circuit detects that the number of the first signals in which the state transition occurs is larger than the predetermined number, the detection circuit sends the instruction signal to the receiving circuit which receives the second signal. , The control signal indicating that the second signal is a signal obtained by subjecting the first signal to signal conversion is transmitted.

The digital information processing apparatus of the second invention is
A receiving circuit for receiving a plurality of first signals and a second signal indicating that the first signals have been subjected to signal conversion; and information indicating a predetermined set of signal states relating to the plurality of signals. The signal states of the plurality of first signals and the second signals are compared at a predetermined timing, and if the two do not match, the first signal
And a control circuit for generating a signal that warns of a transmission error.

A digital information processing apparatus according to the third invention is
It is predicted whether or not a state transition occurs at a predetermined timing with respect to the plurality of signal input units and the first signals respectively input from the plurality of signal input units. When it is detected that the signal does not occur, a detection circuit for sending an instruction signal for instructing to perform signal conversion for changing the state of at least one first signal, and inputting the first signal and the instruction signal A signal conversion circuit that performs signal conversion on the first signal based on the signal and outputs the second signal as a second signal. Here, when the detection circuit detects that no state transition occurs in any of the first signals,
In addition to sending the instruction signal, a control signal indicating that the first signal has been subjected to signal conversion is sent to a receiving circuit that receives the second signal.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram illustrating an example of a mode of the present invention. In the figure, an output signal control circuit 4 which is a main part of the present invention
Reference numeral 10 includes a detection circuit 411 and a signal conversion circuit 412. The output signal control circuit 410 is one component of the digital information processing apparatus, and includes n signals D1, D2 generated from the signal generation unit of the digital information processing apparatus.
, Dn are input from the signal input units 400-1 to 400-n. The output signal control circuit 410 is a circuit that predicts the state transition of the signals D1, D2, ..., Dn output from the digital information processing device and controls the signal state. here,
The state transition is a state of a signal, for example, a voltage value changing beyond a certain threshold value. As an example, when the signal is a binary digital signal represented by a high potential and a low potential, the signal changes from a high potential to a low potential or from a low potential to a high potential.

In this embodiment, input units 400-1 to 400-40
Whether or not a state transition occurs for each of the n signals D1, D2, ..., Dn input from 0-n, and the number of signals where the state transition occurs is (n-1) or more. Detect if there is. The number of signals that cause a state transition is n-
When it is 1 or more, signal conversion is performed based on a signal conversion table described later so that all or some of the signals in which state transition occurs do not cause state transition, and (n-1) or more in total. The signals are controlled so that the states do not change at the same time.

Table 1 below is a signal conversion table.
It is a table which shows the signal conversion method at the time of (n-1) or more signal state transition. This table may be stored in a memory such as a ROM, or may be configured by a logic circuit as in the embodiments described later.

[0010]

[Table 1]

In the n signals D1 to Dn input from the input units 400-1 to 400-n, (n-1)
There are n combinations of books as shown in Table 1.
The detection circuit 411 detects whether or not the states of all the combinations of the signals are simultaneously transited. When the simultaneous state transition occurs for (n-1) output signals, that is, when the simultaneous state transition occurs for any combination of the output signals in Table 1, the detection circuit 411 determines that the combination of Table 1 An instruction signal for instructing not to cause state transition of all output signals other than the signal located at the beginning of the signal is sent to the signal conversion circuit 412. For example, when the target output signal is a binary signal, an instruction signal that inverts the original signal from the original signal polarity and instructs the signal conversion circuit 412 to keep the same state is sent. The signal conversion circuit 412 performs signal conversion on the target signal based on the instruction signal. All output signals other than the signal located at the head are shown in Table 1 under the item of control target signal. The signal conversion regulation shown in Table 1 is only one regulation, and various other signal conversion agreements can be considered. As an example, signal conversion is performed so that all output signals other than the signal located at the end of Table 1 do not undergo state transition.

The detection circuit 411 sends an instruction signal to the signal conversion circuit 412 and, at the same time, inverts (toggles) the polarity of a control signal indicating whether signal conversion has been performed and sends it to the input signal control circuit 450. In this way, the signals D1 and D input from the input units 400-1 to 400-n are input.
2, ..., Dn are partially or wholly output by the signal conversion circuit 412.
Then, the signals are converted by the output terminals 430-1 to 430-n and transmitted to the digital information processing apparatus on the receiving side. The control signal described above is also transmitted from the output unit 431 to the digital information processing device on the receiving side.

The receiving side digital information processing apparatus has the input signal control circuit 450 shown in FIG. 1, and the input signal control circuit 450 is a signal converted by the output signal control circuit 410 of the transmitting side digital information processing apparatus. Is converted back to the original signal state. Specifically, the detection circuit 451 detects the polarity change of the control signal input from the input unit 441, and the signals D1, D2, ..., Dn input from the input units 440-1 to 440-n, respectively. Detects whether or not the state has changed. The detection circuit 451 detects the signals D1, D2,
.., Dn, the signal whose state should be changed can be specified based on the conversion table in Table 2 below.

[0014]

[Table 2]

If the polarity of the control signal does not change, it means that (n-1) or more of the signals D1, D2, ... , Does not send an instruction signal for instructing signal conversion to the signal conversion circuit 452. In this case, the signal conversion circuit 452 does not inversely convert any of the signals D1, D2, ..., Dn, and sends the signal group from the output units 470-1 to 470-n to the digital information processing circuit in the subsequent stage.

When the polarity of the control signal changes, the signals D1 and D input from the input units 430-1 to 430-n are input.
Of (2, ..., Dn), (n-1) or more signals are simultaneously transiting to the state. As shown in Table 2, when the polarity of the control signal changes and the signal D1 makes a state transition, the signals of the simultaneous state transition detected at the transmitting side as described above are the signals D1, D2, D3, ..., D (n-1). Therefore,
The detection circuit 451 outputs signals D2, D3, ..., D (n-1).
To the signal conversion circuit 452, and the signal conversion circuit 452 outputs the signal D
Signal conversion is performed on 2, D3, ..., D (n-1).
For example, if the signal to be handled is a signal representing two values,
The polarity will be inverted before output. The signal conversion circuit 452, after performing the above-mentioned signal conversion, sends out a signal group to the digital information processing circuit in the subsequent stage. Similarly, when the polarity of the control signal changes and the signal Dm (where m is a natural number of 2 or more and n or less) also undergoes a state transition, a state transition is performed for the signal to be state transition according to the conversion table of Table 2. Give. When the polarity of the control signal changes and none of the signals make a state transition, the simultaneous state transition signals detected by the transmitting side as described above are all signals. Therefore, the detection circuit 451 sends an instruction signal for instructing signal conversion to all signals to the signal conversion circuit 452, and the signal conversion circuit 452 performs signal conversion to all signals. As described above, the detection circuit 451 restores the received signal based on the information of the conversion table of Table 2 and the signal whose state has changed, so that the digital information processing circuit on the receiving side can receive the signal of the correct information. You can

In this embodiment, the output signal control circuit 410
When the number of output signals is n, it monitors whether or not (n-1) signals make state transition at the same time, and when (n-1) or more signals make state transition, the number of signals that make state transition This is an example of the mode in which the signal conversion circuit 412 performs the signal conversion so that (n−2) or less.
Not limited to (n-1), any number k (k is 2 or more (n-
2) The following natural numbers) may be used. However, in this case, the control signal is not a binary signal that indicates only whether or not signal conversion has been performed, but a ternary or higher signal.

Next, this embodiment will be described in more detail with reference to the following embodiments. FIG. 2 is a block diagram showing an embodiment of the present invention, which is an example of a form in which an output signal control circuit which is a main part of the present invention is applied to a digital information processing circuit 2 having four signal output parts. This form example is described in 4 above.
In this embodiment, the number of simultaneous state transitions of two signals is detected and the state transitions of the signals are controlled. Specifically, the digital information processing circuit 2 of this embodiment is a circuit that handles a binary digital signal, and the output signal control circuit 1 changes the signal from a high potential to a low potential or a low potential. To change to high potential.

Here, the detection circuit 411 of FIG. 1 has the flip-flops (hereinafter referred to as F / F) 20 to 2 of FIG.
3, 40 to 43, control circuit 10, OR gate 11, NO
It corresponds to the R gate and F / F 13. The signal conversion circuit 412 in FIG. 1 corresponds to the conversion circuits 30 to 33.

In the figure, an input section of the F / F 20 is connected to a signal generating section Pa (not shown) of the digital information processing circuit 2, and the F / F 20 inputs the signal A generated by the signal generating section Pa. , And outputs a signal in synchronization with a clock signal CLK described later. Similarly, the input sections of the F / Fs 21 to 23 are connected to the signal generating sections Pb, Pc, and Pd (not shown) of the digital information processing circuit 2, respectively.
21 to 23 are signals B, C generated by the respective signal generators,
Each D is input and a signal is output in synchronization with a clock signal CLK described later. Further, the same clock signal CLK is externally input to the clock input sections of the F / Fs 20 to 23. The clock signal CLK is also input to the control circuit 10, the F / F 13, and 40 to 43 described later.

The output part of the F / F 20 is connected to one of the input parts of the conversion circuit 30, and the signal A generated by the F / F 20 is connected.
n is transmitted to the conversion circuit 30 in synchronization with the clock signal CLK. Similarly, the output sections of the F / Fs 21, 22, and 23 are
Each of the F / Fs 21, 22 and 23 is connected to one of the input sections of the conversion circuits 31, 32 and 33, and the F / Fs 21, 22 and 23 respectively synchronize the generated signals Bn, Cn and Dn with the clock signal CLK, respectively. , 33. Also,
The output parts of the F / Fs 20 to 23 are also connected to the control circuit 10, and the control circuit 10 outputs signals An, Bn, Cn, and D.
Enter n.

The conversion circuits 30 to 33 are circuits for converting the state of an input signal based on the signal from the control circuit 10 and outputting it. The output section of the conversion circuit 30 is connected to the input section of the F / F 40, and the signal a generated by the conversion circuit 30 is input to the F / F 40. Similarly, the conversion circuit 3
The output units of 1, 32, and 33 are F / F 41 and 4 respectively.
The conversion circuits 31 and 3 are connected to the input units of 2 and 43.
2 and 33 transmit the generated signals b, c and d to the F / Fs 41, 42 and 43, respectively.

The output unit of the F / F 40 is connected to the output unit 50, and the F / F 40 synchronizes the signal Aout generated by the F / F 40 with the clock signal CLK.
Send to Similarly, the output parts of the F / Fs 41, 42, 43 are connected to the output parts 51, 52, 53, respectively, and the F / Fs 41, 42, 43 respectively output the generated signals Bout, Cout, Dout as clock signals. It is transmitted to the output units 51, 52 and 53 in synchronization with CLK.
The output parts of the F / Fs 40 to 43 are also connected to the control circuit 10, and the control circuit 10 outputs signals Aout and Bo.
Input ut, Cout, Dout.

The control circuit 10 controls the signals An, Bn, Cn,
Dn and signals Aout, Bout, Cout, Dout are input. The control circuit 10 controls the signals An, Aout and B
The state transitions of n and Bout, Cn and Cout, Dn and Dout are detected, and the signals and the number of signals that undergo the state transition simultaneously for each clock are specified.

The output part of the control circuit 10 includes conversion circuits 30 to 30.
33, the OR gate 11 and the NOR gate 12. The signal FA generated by the control circuit 10 is input to the conversion circuits 31 and 32, and the signal FB generated by the control circuit 10 is input to the conversion circuits 32 and 33. Further, the signal FC generated by the control circuit 10 is converted into the conversion circuits 30, 3
The signal FD input to the signal 3 and generated by the control circuit 10 is
It is input to the conversion circuits 30 and 31. Furthermore, the signal FA,
FB, FC, and FD are OR gate 11 and NOR
It is input to the gate 12. The F / F 13 is a JK flip-flop, and inputs the output signal f1 of the OR gate 11 to the J input and the output signal f2 of the NOR gate 12 to the K input. Further, the output section of the F / F 13 is connected to the output section 54.

FIG. 3 is an example of an internal circuit diagram of the conversion circuits 30 to 33. Each conversion circuit is composed of circuits having the same configuration. The input parts FX and FY are connected to the input part of the OR gate 59, and the input part Xn is connected to the EXOR gate 58.
Is connected to the input section. Further, the output unit x is an EXO
It is connected to the output of the R gate 58.

Table 3 below shows the input parts Xn and F shown in FIG.
3 is a table illustrating the relationship between the signals input to X and FY and the signal output to the output unit x, and the above-described signals flowing on the signal lines of the block diagram of FIG. 2.

[0028]

[Table 3]

Signals An, FC, FD are input to the input sections Xn, FX, FY of the conversion circuit 30, respectively. The signal a is output from the output section x of the conversion circuit 30. The signals Bn, FA, and FD are input to the input units Xn, FX, and FY of the conversion circuit 31, respectively. Further, the signal b is output from the output section x of the conversion circuit 31. The input portion Xn, FX, FY of the conversion circuit 32 has a signal C, respectively.
n, FB, FA are input. The signal c is output from the output section x of the conversion circuit 32. The signals Dn, FB, and FB are input to the input units Xn, FX, and FY of the conversion circuit 33, respectively.
FC is input. Further, the signal d is output from the output section x of the conversion circuit 32.

FIG. 4 is an example of an internal circuit diagram of the control circuit 10 shown in FIG. The control circuit 10 includes the simultaneous operation detection units 60, 70, 80, 90 and the F / Fs 65, 75, 85, 9
Consists of five. The simultaneous operation detector 60 includes a signal generator Pa,
The EXOR gate 6 is a circuit for detecting the state transitions of three signals generated from Pb and Pc at the same time.
1, 62, 63 and an AND gate 64. EXO
The signals An and Aout are input to the R gate 61, and the EX
The OR gate 61 sends a high-level signal to the AND gate 64 when the signal An causes the state transition from the signal Aout. The EXOR gate 62 has a signal Bn,
Bout is input, and the EXOR gate 62 receives the signal Bn
Outputs a high-level signal to the AND gate 64 when the signal Bout makes a state transition. Also, E
The signals Cn and Cout are input to the XOR gate 63,
The EXOR gate 63 ANDs the signal at the high level when the signal Cn causes the state transition from the signal Cout.
It is sent to the gate 64. With this configuration, the simultaneous operation detection unit 60 outputs a high-level signal to the F / F 65 when all three signals generated from the signal generation units Pa, Pb, and Pc cause a state transition. This signal is output from the F / F 65 as the signal FA in synchronization with the rising edge of the clock signal CLK.

The simultaneous operation detector 70 includes a signal generator Pb,
EXOR gate 7 is a circuit for detecting a state transition of three signals generated from Pc and Pd at the same time.
1, 72, 73 and an AND gate 74. EXO
The signals Bn and Bout are input to the R gate 71, and the EX
The OR gate 71 sends a high level signal to the AND gate 74 when the signal Bn causes a state transition from the signal Bout. The EXOR gate 72 has a signal Cn,
Cout is input, and the EXOR gate 72 outputs the signal Cn.
Sends a high-level signal to the AND gate 74 when the signal Cout causes a state transition. Also, E
The signals Dn and Dout are input to the XOR gate 73,
The EXOR gate 73 ANDs a high-level signal when the signal Dn causes a state transition from the signal Dout.
It is sent to the gate 74. With this configuration, the simultaneous operation detecting unit 70 outputs a high-level signal to the F / F 75 when all three signals generated from the signal generating units Pb, Pc, and Pd cause a state transition. This signal is output as a signal FB from the F / F 75 in synchronization with the rising edge of the clock signal CLK.

The simultaneous operation detector 80 includes a signal generator Pc,
EXOR gate 8 is a circuit for detecting a state transition of three signals generated from Pd and Pa at the same time.
1, 82, 83 and an AND gate 84. EXO
The signals Cn and Cout are input to the R gate 81, and EX
The OR gate 81 sends a high level signal to the AND gate 84 when the signal Cn causes a state transition from the signal Cout. The EXOR gate 82 has a signal Dn,
Dout is input, and the EXOR gate 82 outputs the signal Dn.
Outputs a high level signal to the AND gate 84 when the signal Dout is causing a state transition. Also, E
The signals An and Aout are input to the XOR gate 83,
The EXOR gate 83 ANDs the signal of the high level when the signal An causes the state transition from the signal Aout.
It is sent to the gate 84. With this configuration, the simultaneous operation detection unit 80 outputs a high-level signal to the F / F 85 when all three signals generated from the signal generation units Pc, Pd, and Pa cause state transition. This signal is output from the F / F 85 as the signal FC in synchronization with the rising edge of the clock signal CLK.

The simultaneous operation detector 90 includes a signal generator Pd,
The EXOR gate 9 is a circuit for detecting a state transition of three signals generated from Pa and Pb at the same time.
1, 92, 93 and an AND gate 94. EXO
The signals Dn and Dout are input to the R gate 91, and the EX
The OR gate 91 sends a high level signal to the AND gate 94 when the signal Dn causes a state transition from the signal Dout. The EXOR gate 92 has a signal An,
Aout is input, and the EXOR gate 92 receives the signal An.
Sends a high-level signal to the AND gate 94 when the signal Aout is causing a state transition. Also, E
The signals Bn and Bout are input to the XOR gate 93,
The EXOR gate 93 ANDs the signal at the high level when the signal Bn causes the state transition from the signal Bout.
It is sent to the gate 94. With this configuration, the simultaneous operation detection unit 90 outputs a high level signal to the F / F 95 when all three signals generated from the signal generation units Pd, Pa, Pb cause state transition. This signal is output from the F / F 95 as the signal FB in synchronization with the rising edge of the clock signal CLK.

The operation of the output signal control circuit 1 will be described in detail below. The signals A, B, C, and D respectively generated by the signal generators Pa, Pb, Pc, and Pd of the digital information processing circuit 2 are F / F 20, 21 and, respectively.
22 and 23 are input. Signals An, Bn, Cn, Dn
Is in the same state as the signals A, B, C, D in synchronization with the rising edge of the clock signal CLK input to the F / F. For the signals An, Bn, Cn, Dn, The state is maintained until the rising of the signal CLK.

The conversion circuit 30 includes the signal An and the control circuit 10.
The signal a is output according to the following logical expression (1) based on the signals FC and FD output from

[0036]

[Equation 1]

According to the above logical expression (1), when the signal FC or FD sent from the control circuit 10 is in the high level state, the conversion circuit 30 inverts the polarity of the signal An and outputs it as the signal a at the subsequent stage F /. Send to F40. Specifically, the conversion circuit 30 sends a low-level signal a to the F / F 40 when the input signal An is in the high level state, and when the input signal An is in the low level state, The high-level signal a is sent to the F / F 40. Signal F
The high level state of C or FD indicates that the signal transmitted from the signal generation unit Pa undergoes state transition, that is, the state of the signal An is inverted from the state of the signal Aout. Inverting the state of the signal An in the conversion circuit 30 leads to generation of the signal a that does not cause the state transition at the clock. F / F40
The signal Aout sent from the F / F 40 becomes the state of the signal a in synchronization with the rising edge of the clock signal CLK, and this state is maintained until the next rising edge of the clock signal CLK. The signal Aout is sent from the output unit 50 to the digital information processing circuit on the receiving side.

Like the conversion circuit 30, the conversion circuit 31 includes a signal An and signals FD and FA output from the control circuit 10.
Then, the signal b is output according to the following logical expression (2).

[0039]

[Equation 2]

According to the above logical expression (2), when the signal FD or FA sent from the control circuit 10 is in the high level state, the conversion circuit 31 inverts the polarity of the signal Bn and outputs it as the signal b at the subsequent stage F /. Send to F41. The signal Bout sent from the F / F 41 becomes the state of the signal b in synchronization with the rising edge of the clock signal CLK in the F / F 41,
This state is maintained until the next rising of the clock signal CLK. The signal Bout is sent from the output unit 51 to the digital information processing circuit on the receiving side.

Like the conversion circuit 30, the conversion circuit 32 also outputs the signal c according to the following logical expression (3) based on the signal Cn and the signals FA and FB output from the control circuit 10.

[0042]

(Equation 3)

According to the above logical expression (3), if the signal FA or FB sent from the control circuit 10 is in the high level state, the conversion circuit 32 inverts the polarity of the signal Cn and outputs it as the signal c at the subsequent stage F /. Send to F42. The signal Cout sent from the F / F 42 becomes the state of the signal c in synchronization with the rising edge of the clock signal CLK in the F / F 42,
This state is maintained until the next rising of the clock signal CLK. The signal Cout is sent from the output unit 52 to the digital information processing circuit on the receiving side.

Similar to the conversion circuit 30, the conversion circuit 33 also outputs a signal d according to the following logical expression (4) based on the signal Dn and the signals FB and FC output from the control circuit 10.

[0045]

(Equation 4)

According to the above logical expression (4), if the signal FB or FC sent from the control circuit 10 is in the high level state, the conversion circuit 33 inverts the polarity of the signal Dn and outputs it as the signal d at the subsequent stage F /. Send to F43. The signal Dout sent from the F / F 43 becomes the state of the signal d in synchronization with the rising edge of the clock signal CLK in the F / F 43,
This state is maintained until the next rising of the clock signal CLK. The signal Dout is sent from the output unit 53 to the digital information processing circuit on the receiving side.

Next, as shown in FIG. 2, the control circuit 1
0 is the signals An, Bn, Cn, Dn and Aout, Bou
It receives t, Cout, and Dout. The control circuit 10 receives the signals An and Aou by inputting the above signals.
t, Bn and Bout, Cn and Cout, Dn and Dout
The state transitions of are detected, and the signals and the number of signals that undergo the state transition at the same time are specified.

Specifically, as shown in FIG. 4, the control circuit 10 controls the signals An and Aout, the signals Bn and Bout, the signals Cn and Cout, and the signals Dn and D.
Out is compared and a state transition is detected. Signals An and Aou
When the states of t, Bn and Bout, and Cn and Cout change at the same time, the signal FA becomes the high level state in synchronization with the falling of the clock signal CLK, and is sent to the conversion circuits 31 and 32. The state of the signal FA is held by the F / F 65 until the next fall of the clock signal CLK.
The logical expression (5) of the simultaneous operation detecting unit 60 that realizes the above operation is shown below.

[0049]

(Equation 5)

The signals whose states are changed are signal generation units Pa and P.
When the signals FA are generated by b and Pc, the fact that the high-level signal FA is sent to the conversion circuits 31 and 32 means that the signals FA are generated by the signal generators Pb and Pc, specifically, the signals. The conversion circuit performs signal conversion on Bn and Cn. That is, the signals Bn and Cn are the same as the signal Bou.
It is sent to the F / Fs 41 and 42, respectively, without causing a state transition from the states of t and Cout. Therefore, the only signal that makes a state transition at the output section is the signal An.

Next, signals Bn and Bout, Cn and Co
When the states of ut, Dn and Dout change at the same time, the signal FB goes to the high level state in synchronization with the falling of the clock signal CLK and is sent to the conversion circuits 32 and 33. The state of the signal FB is held by the F / F 75 until the next fall of the clock signal CLK. The logical expression (6) of the simultaneous operation detecting unit 70 that realizes the above operation is shown below.

[0052]

(Equation 6)

Signals whose states are changed are signal generators Pb and P.
In the case of signals generated by c and Pd, the fact that the high-level signal FB is sent to the conversion circuits 32 and 33 means that the signals are generated by the signal generation units Pc and Pd, specifically, the signals. The conversion circuit performs signal conversion on Cn and Dn. That is, the signals Cn and Dn are Cout,
Without changing the state from the state of Dout, F
/ F42, 43. Therefore, the signal that makes the state transition at the output unit is only the signal Bn.

Next, the signals Cn and Cout, Dn and Do
When the states of ut, An and Aout change at the same time, the signal FC goes to the high level state in synchronization with the fall of the clock signal CLK and is sent to the conversion circuits 33 and 30. The state of the signal FC is held by the F / F 85 until the next fall of the clock signal CLK. The logical expression (7) of the simultaneous operation detecting unit 80 that realizes the above operation is shown below.

[0055]

(Equation 7)

The signals whose states are changed are signal generators Pc and P.
In the case of the signals generated by d and Pa, the fact that the high-level signal FC is sent to the conversion circuits 33 and 30 means that the signals are generated by the signal generation units Pd and Pa, specifically, the signals. Signal conversion is performed on the Dn and An by a conversion circuit. That is, the signals Dn and An are the same as the signal Dou.
It is sent to the F / Fs 43 and 40, respectively, without causing a state transition from the states of t and Aout. Therefore, the only signal that makes a state transition at the output section is the signal Cn.

Next, the signals Dn and Dout, An and Ao
When the states of ut, Bn, and Bout change at the same time, the signal FD becomes the high level state in synchronization with the falling edge of the clock signal CLK, and is sent to the conversion circuits 30 and 31. The state of the signal FD is held by the F / F 95 until the next fall of the clock signal CLK. The logical expression (8) of the simultaneous operation detecting unit 90 that realizes the above operation is shown below.

[0058]

(Equation 8)

Signals whose states are changed are signal generation units Pd and P.
In the case of the signals generated by a and Pb, the fact that the signal FD in the high level state is sent to the conversion circuits 30 and 31 means that the signals generated by the signal generation units Pa and Pb, specifically, the signals. The conversion circuit performs signal conversion on An and Bn. That is, the signals An and Bn are the same as the signal Aou.
It is sent to the F / Fs 40 and 41 without causing a state transition from the state of t and Bout. Therefore, the signal that makes the state transition at the output section is only the signal Dn.

Finally, the signals An and Aout, Bn and Bo
When the states of ut, Cn and Cout, and Dn and Dout change at the same time, all of the signals FA, FB, FC, and FD are in the high level state in synchronization with the fall of the clock signal CLK, and the high level signal is converted. Circuits 30, 31,
To 32 and 33.

Signals whose states change are signal generation units Pa and P.
In the case of the signals generated by b, Pc, and Pd, the fact that the high-level signal is sent to all the conversion circuits means that the signals generated by the signal generation units Pa, Pb, Pc, and Pd, Specifically, signal conversion is performed on the signals An, Bn, Cn, and Dn by the conversion circuit. That is, signal A
n, Bn, Cn and Dn are the signals Aout, Bout,
Without causing a state transition from the state of Cout, Dout,
Each is sent to the F / F in the subsequent stage. Therefore, there is no signal that makes a state transition at the output.

The output section of the control circuit 10 is connected to the OR gate 11 and the NOR gate 12, and the signal F
A, FB, FC and FD are all OR gates 11 and N
It is input to the OR gate 12. As described above, when three or more signals make state transitions, the signals FA, FB, FC, F
Since any one or all of D is in the high level state, the output signal f1 of the OR gate 11 is in the high level state and the output signal f2 of the NOR gate 12 is in the low level state. Since the signal f1 is input to the J input and the signal f2 is input to the K input of the JKF / F13, the control signal CONT toggles (inverts) in synchronization with the rising edge of the clock signal CLK.
I do. If three or more signals do not change state, signal F
Since A, FB, FC and FD are all in the low level state, the signal f1 is in the low level state and the signal f2 is in the high level state. In this state, the output of the JKF / F13 does not toggle (invert) and remains unchanged from the previous state. That is, the control signal cont does not change.

Next, the operation of the output signal control circuit 1 shown in FIG. 2 will be described in detail while following the state of each signal. FIG.
3 is a waveform diagram of various signals of the output signal control circuit 1 of FIG.
6 shows changes in various signals when the signals A, B, C and D input to the input terminal change as shown in FIG. In the description below, (X, Y) = (0, 1) means that the signal X
Indicates that the signal X is in the low level state, and the signal Y is in the high level state. (X, Y) = (0, 1) → (1, 0) means that the signal X changes from the low level state to the high level state. , Signal Y has changed from a high level state to a low level state.

In the figure, the signal input to the output signal control circuit 1 is synchronized with the falling edge of the clock CLK0 (A,
B, C, D) = (0, 0, 0, 1) → (1, 1, 1,
In the case of 1), (An, Bn, Cn, Dn) = (1, 1, 1, 1) in synchronization with the rising edge of the clock CLK1. Further, at the rising edge of the clock CLK1, (A
out, Bout, Cout, Dout) = (0, 0,
0, 1). Therefore, the control circuit 10 detects that the signals Aout, Bout, and Cout output from the output section make a state transition at the clock next to the clock CLK1, that is, at the clock CLK2.

Since the state transition of the signals Aout, Bout, Cout is detected by the clock CLK2, the output signal of the control circuit 10 is synchronized with the falling edge of the clock CLK1 (FA, FB, FC, FD). = (1,
0, 0, 0). Depending on the states of the signals An, Bn, Cn, Dn and the signals FA, FB, FC, FD, the conversion circuit 30
The output signals of ~ 33 are (a, b, c, d) = (1, 0,
0, 1). As a result, the output signals of the F / Fs 40 to 43 are synchronized with the rising edge of the clock CLK2.
(Aout, Bout, Cout, Dout) = (1,
0, 0, 1).

Further, the output signal of the control circuit 10 is (FA, FB, FC, F at the falling edge of the clock CLK1.
D) = (1,0,0,0), the OR gate 11
And the output signal of the NOR gate 12 is (clock CLK
At the fall of 1, (f1, f2) = (1, 0), and the output signal of the JKF / F13 becomes (cont) = (0) → (1) in synchronization with the rising of the clock CLK2. Therefore, the output signals of the output units 50 to 54 are (Aout, Bout,
Cout, Dout, cont) = (0, 0, 0, 1,
0) → (1,0,0,1,1). By the above operation, by converting the signals Bout and Cout to the state where the signals Aout, Bout, and Cout originally make the state transition at the rising edge of the clock CLK2, the number of signals that make the simultaneous state transition is 3 to 1 (control signal is Including 3
To 2). Further, the polarity of the control signal cont is inverted due to the signal conversion.

Next, the signal input to the output signal control circuit 1 is synchronized with the falling edge of the clock CLK1 (A,
B, C, D) = (1, 1, 1, 1,) → (1, 0, 0,
0), (An, Bn, Cn, Dn) = (1, 0, 0, 0) in synchronization with the rising edge of the clock CLK2. Also, when the clock CLK2 rises, (A
out, Bout, Cout, Dout) = (1, 0,
0, 1). Therefore, the control circuit 10 has the output unit 53.
Since only the signal Dout output from the state transition occurs at the clock CLK3, three or more simultaneous state transitions are not detected. That is, the output signal of the control circuit 10 is the clock CL.
In synchronization with the fall of K2 (FA, FB, FC, F
D) = (0,0,0,0). In addition, the signals An and B
Depending on the states of n, Cn, Dn and the signals FA, FB, FC, FD, the output signals of the conversion circuits 30 to 33 are (a, b,
c, d) = (1, 0, 0, 0). As a result, in synchronization with the rising edge of the clock CLK3, the F / F40-
The output signal of 43 is (Aout, Bout, Cout,
Dout) = (1, 0, 0, 0).

The output signal of the control circuit 10 is (F
Since A, FB, FC, FD) = (0, 0, 0, 0), the output signals of the OR gate 11 and the NOR gate 12 are (f1, f2) = (0, 1), and JKF / F1
The output signal of 3 becomes (cont) = (1) → (1) at the rising edge of the clock CLK3, and the polarity is not inverted. Therefore, the output signals of the output units 50 to 54 are (Aout, Bout, C) at the rising edge of the clock CLK3.
out, Dout, cont) = (1, 0, 0, 0,
1). That is, since the number of simultaneous state transition signals is 1, the signals Aout, Bout, Cout, Dout are not converted at the time of rising of the clock CLK3.
Is output. Moreover, since the signal conversion is not performed, the polarity of the control signal cont is not inverted.

Next, the signal input to the output signal control circuit 1 is synchronized with the falling edge of the clock CLK2 (A,
B, C, D) = (1, 0, 0, 0) → (0, 1, 1,
1), (An, Bn, Cn, Dn) = (0, 1, 1, 1) in synchronization with the rising edge of the clock CLK3. Also, when the clock CLK3 rises, (A
out, Bout, Cout, Dout) = (1, 0,
0, 0). Therefore, the control circuit 10 outputs the signals Aout, Bout, Cout, Dou output from the output section.
It is detected that t transits to the next clock of the clock CLK3, that is, the clock CLK4.

The control circuit 10 controls the signals Aout and Bou.
The output signal of the control circuit 10 detects the state transition of t, Cout, and Dout at the clock CLK4.
In synchronization with the falling edge of the clock CLK3, (FA, F
B, FC, FD) = (1, 1, 1, 1). Signal A
Depending on the states of n, Bn, Cn, Dn and the signals FA, FB, FC, FD, the output signals of the conversion circuits 30 to 33 are (a,
b, c, d) = (1, 0, 0, 0). As a result, the F / F is synchronized with the rising edge of the clock CLK4.
The output signals of 40 to 43 are (Aout, Bout, Co
ut, Dout) = (1, 0, 0, 0).

The output signal of the control circuit 10 is (F
Since A, FB, FC, FD) = (1, 1, 1, 1), the output signals of the OR gate 11 and the NOR gate 12 are (f1, f2) = (1, 0), and JKF / F1
The output signal of 3 becomes (cont) = (1) → (0) in synchronization with the rising edge of the clock CLK4. Therefore, the output signals of the output units 50 to 54 are (Aout, Bout,
Cout, Dout, cont) = (1, 0, 0, 0,
0). By the above operation, originally, the signal Aout,
Bout, Cout, and Dout change state at the rising edge of the clock CLK4.
By performing signal conversion on all out, Cout, and Dout, the number of signals that undergo the simultaneous state transition can be reduced from 4 to 0 (4 to 1 when the control signal is included). Also,
By performing the signal conversion, the polarity of the control signal cont is inverted. The subsequent operation of the output signal control circuit 1 is similarly performed according to the operation of each logic circuit.

Next, a circuit for receiving a signal output from the digital information processing circuit 2 via the output signal control circuit 1 and inversely converting the received signal will be described with reference to the drawings. As described above, the output signal control circuit 1 performs signal conversion on the corresponding signal according to the method described above when the state transition of three or more signals, specifically, inverts the signal from the original signal code. Let Also, the output signal control circuit 1
Transmits a control signal that informs the receiving side of whether the signal conversion is performed or not, together with the signal to be transmitted. The digital information processing apparatus on the receiving side receives the signal to be received and the control signal indicating the presence / absence of signal conversion, reverse-converts the signal converted on the transmitting side, and sends it to the processing circuit in the subsequent stage.

FIG. 6 shows a digital information processing circuit 102 which receives a signal from the digital information processing circuit 2 shown in FIG. Further, in the figure, an input signal control circuit 101 is shown as an example of a circuit for converting an input signal into an inverse signal in a stage before the digital information processing circuit 102.
The input signal control circuit 101 is a circuit for performing inverse signal conversion on the signal that has been signal-converted by the output signal control circuit 1 shown in FIG. 2 and described in detail, and together with the signal, the output signal control circuit 1
Also, the above-mentioned control signal from is input.

Here, the detection circuit 451 of FIG. 1 corresponds to the F / Fs 140 to 144 and the control circuit 110 of FIG. In addition, the signal conversion circuit 452 of FIG.
Corresponding to 0-133.

In FIG. 6, the input signal control circuit 101 receives the clock signal CLK from the input section 155 and outputs the internal F / F.
Supply to F. In addition, the signal output from the output unit 50 of FIG. 2 is input to the input unit 150 as the signal Ain.
Similarly, the signals output from the output units 51 to 53 in FIG. 2 are input to the input units 151 to 153 by the signals Bin and Ci, respectively.
It is input as n and Din, respectively. Furthermore, the control signal c related to the signal conversion output from the output unit 54 in FIG.
ont is input to the input unit 154. Also, the output unit 1
50 to 154 are also connected to the control circuit 110, and the control circuit 110 outputs signals Ain, Bin, Cin, Din.
And the control signal cont.

The input section of the F / F 140 is connected to the input section 150, and the F / F 140 receives the signal Ain and outputs the signal in synchronization with the clock signal CLK. Similarly, the input units of the F / Fs 141 to 144 are connected to the input units 151 to 154, respectively, and the F / Fs 140 to
The signal 144 receives the signals Bin, Cin, Din, and cont, respectively, and outputs the signals in synchronization with the clock signal CLK.

The output portion of the F / F 140 is the conversion circuit 130.
The signal R generated by the F / F140 is connected to the input part of the
A is transmitted to the conversion circuit 130 in synchronization with the clock signal CLK. The conversion circuit 130 is specifically an EXOR gate. Similarly, the output sections of the F / Fs 141, 142, 143 are connected to the input sections of the conversion circuits 131, 132, 133, respectively, and the F / Fs 131, 132, 133 clock the generated signals RB, RC, RD, respectively. Signal C
The conversion circuits 131, 132, 13 are synchronized with LK, respectively.
Send to 3. The output units of the F / Fs 140 to 144 are also connected to the control circuit 110, and the control circuit 11
0 is the signals RA, RB, RC, RD and the control signal Rcon
Enter t and. The conversion circuits 131 to 133 are specifically EXOR gates.

The conversion circuits 130 to 133 have the control circuit 11
It is a circuit that converts the state of an input signal based on the signal from 0 and outputs the signal. The output of the conversion circuit 130 is F /
The signal Ra, which is connected to the input unit of the F120 and is generated by the conversion circuit 130, is input to the F / F120. Similarly, each of the conversion circuits 131, 132, 133 has an F / F
It is connected to the input part of F121, 122, 123,
The conversion circuits 131, 132, 133 output the generated signals Rb, Rc, Rd to the F / Fs 121, 12 respectively.
2 to 123.

The output section of the F / F 120 is connected to the digital information processing circuit 102.
/ F120 generates the signal A'to the clock signal CLK
To the digital information processing circuit 102 in synchronism with the above.
Similarly, the output sections of the F / Fs 121, 122, 123 are also connected to the digital information processing circuit 102, and the F / F 1
21, 122, and 123 are generated signals B ′,
C ′ and D ′ are sent to the digital information processing circuit 102 in synchronization with the clock signal CLK.

The control circuit 110 controls the signals Ain, Bin,
Cin, Din and signals RA, RB, RC, RD are input. Both the signal Ain and the signal RA are signals output from the output unit 50 on the transmission side shown in FIG.
n is a signal output from the output unit 50 one clock after the signal RA. Similarly, both the signal Bin and the signal RB are signals output from the output unit 51, and the signal B
in is a signal output from the output unit 51 one clock after the signal RB. Further, both the signal Cin and the signal RC are signals output from the output unit 52, and the signal Cin
in is a signal output from the output unit 52 one clock after the signal RC. Furthermore, both the signal Din and the signal RD are signals output from the output unit 53, and the signal Din is a signal output from the output unit 53 one clock after the signal RD. By inputting the above signals, the control circuit 110 detects the state transition of each signal output from the output unit on the transmission side, and identifies the signal that transits the state for each clock. In addition, the control circuit 110
The control signal relating to the signal conversion output from the output unit 54 in FIG. 2 is input, and it is detected whether the input signal is subjected to the signal conversion.

The output of the control circuit 110 is the conversion circuit 13
0 to 133 are connected. The signal RFA generated by the control circuit 110 is input to the conversion circuit 130, and the signal RFB generated by the control circuit 110 is input to the conversion circuit 131. In addition, the signal R generated by the control circuit 110
FC is input to the conversion circuit 132, and the signal RFD generated by the control circuit 110 is input to the conversion circuit 133.

FIG. 7 is an example of an internal circuit diagram of the control circuit 110 shown in FIG. The control circuit 110 includes signal conversion detectors 160, 170, 180, 190, 200, OR gates 163, 173, 183, 193, F / F 164.
It consists of 174, 184, 194 and an EXOR gate 211. The control signals cont and Rcont are input to the EXOR gate 211. The signal cont is the signal Rco
The state of the signal transmitted from the output unit 54 on the transmission side in FIG. 2 one clock after nt is shown. By the operation of the output signal control circuit 1 described above, the control circuit 110 causes the signal co
It is detected that the signal conversion has been performed when the state of nt changes from the signal Rcont, that is, when the state of nt is inverted. E
The XOR gate 211 outputs the high-level signal XORE when the control signal is inverted, based on the following logical expression (9), in the signal conversion detection units 160, 170, 180, and 1.
90, 200.

[0083]

[Equation 9]

The signal conversion detection section 160 is one of the circuits for detecting whether or not signal conversion has been performed in the output side signal control circuit 1 on the transmission side shown in FIG. 2, and the signals from the EXOR gate 161 and the AND gate 162 are used. Become. EXOR
Signals Ain and RA are input to the gate 161, and EXO
The R gate 161 is based on the following logical expression (10).
When the signal Ain is in the state transition from the signal RA, the high level signal is sent to the AND gate 162 as the signal XORA.

[0085]

(Equation 10)

The AND gate 162 receives the signals XORE, X.
The ORA is input and the signal fa is output to the OR gates 173 and 183 based on the following logical expression (11).

[0087]

[Equation 11]

With this configuration, the signal conversion detection section 160
The OR gate 173, 1 outputs the signal in the high level state when the signal input from the input unit 150 causes the state transition and the control signal indicates that the signal conversion is performed.
Output to 83. High level signal is OR gate 1
By being output to the conversion circuits 131 and 73,
And 132, inverse signal conversion, that is, signal restoration is performed.

Next, the signal conversion detector 170 is also shown in FIG.
It is one of the circuits for detecting whether or not signal conversion has been performed in the output signal control circuit 1 on the transmission side shown in
It is composed of an EXOR gate 171 and an AND gate 172. The signals Bin and RB are input to the EXOR gate 171, and the EXOR gate 171 receives the logical expression (12) below.
Based on the above, when the signal Bin causes the state transition from the signal RB, the high level signal is sent to the AND gate 172 as the signal XORB.

[0090]

(Equation 12)

The AND gate 172 receives the signals XORE, X.
The ORB is input and the signal fb is output to the OR gates 183 and 193 based on the following logical expression (13).

[0092]

(Equation 13)

With this configuration, the signal conversion detector 170
The OR gate 183, 1 outputs a high-level signal when the signal input from the input unit 151 causes a state transition and the control signal indicates signal conversion.
Output to 93. High level signal is OR gate 1
The conversion circuit 132 outputs to 83 and 193.
And 133, signal restoration is performed.

Next, the signal conversion detector 180 is also shown in FIG.
It is one of the circuits for detecting whether or not signal conversion has been performed in the output signal control circuit 1 on the transmission side shown in
It is composed of an EXOR gate 181 and an AND gate 182. Signals Cin and RC are input to the EXOR gate 181, and the EXOR gate 181 outputs the logical expression (14) below.
Based on the above, when the signal Cin makes a state transition from the signal RC, a high level signal is sent to the AND gate 182 as the signal XORC.

[0095]

[Equation 14]

The AND gate 182 outputs the signals XORE, X.
The ORC is input and the signal fc is output to the OR gates 193 and 163 based on the following logical expression (15).

[0097]

(Equation 15)

With this configuration, the signal conversion detection unit 180
When the signal input from the input unit 152 causes the state transition and the control signal indicates that the signal conversion is performed, the high level signal is OR gates 193 and 1.
Output to 63. High level signal is OR gate 1
By being output to 93 and 163, the conversion circuit 133
And 130, signal restoration is performed.

Next, the signal conversion detector 190 is also shown in FIG.
It is one of the circuits for detecting whether or not signal conversion has been performed in the output signal control circuit 1 on the transmission side shown in
It is composed of an EXOR gate 191 and an AND gate 192. The signals Din and RD are input to the EXOR gate 191, and the EXOR gate 191 uses the following logical expression (16).
Based on the above, when the signal Din makes a state transition from the signal RD, a high level signal is sent to the AND gate 192 as the signal XORD.

[0100]

(Equation 16)

The AND gate 192 receives the signals XORE, X.
The ORD is input, and the signal fd is output to the OR gates 163 and 173 based on the following logical expression (17).

[0102]

[Equation 17]

With this configuration, the signal conversion detecting section 190
When the signal input from the input unit 153 causes the state transition and the control signal indicates that the signal conversion is performed, the OR gate 163, 1 outputs the signal in the high level state.
Output to 73. High level signal is OR gate 1
The conversion circuit 130 is output by the output signals 63 and 173.
And 131, signal restoration is performed.

The signal conversion detecting section 200 is a circuit for detecting whether or not all signals have been converted in the output signal control circuit 1 on the transmitting side shown in FIG.
This is an example, and the NOR gate 201 and the AND gate 2
02. The NOR gate 201 has a signal XORA,
XORB, XORC, and XORD are input, and the NOR gate 201 sends a high-level signal to the AND gate 202 when all the signals Ain, Bin, Cin, and Din have not made a state transition. The AND gate 202 inputs this signal and the signal XORE indicating the presence or absence of signal conversion on the transmission side, and outputs the signal fall based on the following logical expression (18) to the OR gates 163, 173, and 18.
3, and output to 193.

[0105]

(Equation 18)

With this configuration, the signal conversion detection unit 200
Is a high-level signal when all signals input from the input units 150 to 153 do not cause state transition and the control signal indicates signal conversion.
Output to the R gates 163, 173, 183, 193.
The signals in the high level state are OR gates 163, 173, 1
By being output to 83 and 193, the conversion circuit 13
Signal restoration is performed at 0, 131, 132, and 133.

OR gates 163, 173, 183, 19
3 is connected to the signal conversion detection unit as shown in the figure, and based on the following logical expression (19), signals Rfa,
Rfb, Rfc, and Rfd are sent to the F / F in the subsequent stage.

[0108]

[Equation 19]

OR gates 163, 173, 183, 19
Signals Rfa, Rfb, and Rf respectively generated by
c and Rfd are F / F 164, 174 and 18 respectively.
4, 194. The states of the signals RFA, RFB, RFC, and RFD, which are the output signals of the F / F, are synchronized with the rising edge of the clock signal CLK input to the F / F.
The signals become the same as the signals Rfa, Rfb, Rfc, and Rfd, and the signals RFA, RFB, RFC, and RFD are held in that state until the next rising of the clock signal CLK.

Now, the operation of the input signal control circuit 101 will be described in detail below. The output units 50, 51, 5 of FIG.
The signals Aout output from 2, 53 and 54,
Bout, Cout, Dout, and cont are input to the input units 150, 151, 152, 153, and 154 of FIG. The signals input from the input units 50, 51, 52, 53 and 54 are signals Ain, Bin, Cin, and
F / F140, 141, 14 as Din and cont
2, 143 and 144 respectively. F / F14
The signals 0, 141, 142, 143, and 144 are output signals RA, RB, RC, RD, and Rcont in synchronization with the rising edge of the input clock signal CLK.
Of the input signals Ain, Bin, Cin,
Set to the same state as Din and cont. Signals RA, RB,
RC, RD, and Rcont are the next clock signal CLK
The state is maintained until the rising edge of.

Here, the signals RA, RB, RC, RD, R
cont and signals Ain, Bin, Cin, Din, co
By inputting nt and nt to the control circuit 110, the control circuit 110 can detect whether or not the signals input to the input units 150 to 153 have undergone a state transition for each clock, and the signal is transmitted on the transmission side. A control signal indicating that the conversion has been applied can be detected. The control circuit 110 operates so as to cause the state transition of the signal that should originally undergo the state transition, by the circuit described above. Specifically, as described above, when the state of the signal input to the input unit 150 is changed, the signal R in the high level state is supplied to the conversion circuit 130.
Send FA. Further, when the state of the signal input to the input unit 151 is changed, the high level signal RFB is sent to the conversion circuit 131. In addition, the input unit 15
When changing the state of the signal input to 2, the signal RFC in the high level state is sent to the conversion circuit 132. Further, when the state of the signal input to the input unit 153 is changed, the high-level signal RFD is sent to the conversion circuit 133.

The conversion circuit 130 is an EXOR gate, and when receiving the high-level signal RFA from the control circuit 110, inverts the state of the signal RA and outputs it as the signal Ra to the F / F 120. Similarly, the conversion circuit 131
Is also an EXOR gate, and when it receives the high-level signal RFB from the control circuit 110, it inverts the state of the signal RB and outputs it as the signal Rb to the F / F 121. Further, the conversion circuit 132 is also an EXOR gate, and when receiving the signal RFC in the high level state from the control circuit 110, the state of the signal RC is inverted and the signal Rc is F / F.
Output to 122. Furthermore, the conversion circuit 133 also EXOR
When it is a gate and receives the high-level signal RFD from the control circuit 110, it inverts the state of the signal RD and outputs it as the signal Rd to the F / F 123.

The F / Fs 120 to 123 are conversion circuits 13
The signal R generated by 0, 131, 132, 133
a, Rb, Rc, and Rd are input respectively, and in synchronization with the clock signal CLK, signals A ′, B ′, C ′, and
It is output as D ′ to the digital information processing circuit 102 at the subsequent stage. The signals A ′, B ′, C ′, D ′ output from the input signal control circuit 101 are signals obtained by subjecting the signal conversion on the transmission side to inverse conversion. Specifically, the signal A ′,
B ′, C ′, and D ′ are signals restored to the signals A, B, C, and D generated in the signal generating units Pa, Pb, Pc, and Pd of the digital information processing device on the transmission side.

Next, the input signal control circuit 10 shown in FIG.
The operation 1 will be described in detail while following the state of each signal.
FIG. 8 is a waveform diagram of various signals of the input signal control circuit 101 of FIG. 6, and the output unit 5 of the digital information processing circuit on the transmission side.
It shows changes in various signals when the signals Ain, Bin, Cin, Din, and cont input from 0 to 54 to the input signal control circuit 101 change as illustrated.

In the figure, the signal input to the input signal control circuit 101 is synchronized with the rising edge of the clock CLK1.
(Ain, Bin, Cin, Din, cont) =
(0,0,0,1,0) → (1,0,0,1,1). When the clock CLK1 rises, (R
A, RB, RC, RD, Rcont) = (0, 0, 0,
1, 0), the control circuit 110 detects the state transition of the signal Ain and the control signal cont. Therefore, the control circuit 110 synchronizes with the rising edge of the clock CLK2 and outputs (RFA, RFB, RFC, RFD) = (0, 1,
It is output so that it becomes 1, 0). In addition, F / F140-
The output signal of 143 is (RA, RB, RC, RD) = (1, 0, 0, 1) in synchronization with the rising edge of CLK2.
Becomes Therefore, (RFA, RFB, RFC, RFD)
= (0, 1, 1, 0) and (RA, RB, RC, RD)
= (1, 0, 0, 1), the conversion circuits 130 to 133
Is (Ra, Rb, Rc, Rd) = (1, 1, 1, 1)
To output the output signal. Therefore, the output to the digital information processing circuit 102 is (A ′, B ′, C ′, D ′) = (1, 1, 1,
1).

Next, the signal input to the input signal control circuit 101 is synchronized with the rising edge of the clock CLK2,
(Ain, Bin, Cin, Din, cont) =
(1,0,0,1,1) → (1,0,0,0,1). At this time, the control circuit 110 does not detect the state transition of the control signal cont, that is, the inverted state indicating that the signal conversion is performed on the transmission side, and the output signal of the control circuit 110 is
In synchronization with the rising edge of CLK3, (RFA, RFB,
RFC, RFD) = (0,0,0,0). Therefore, (RFA, RFB, RFC, RFD) = (0, 0,
0, 0) and (RA, RB, RC, RD) = (1, 0,
0, 0), the conversion circuits 130 to 133 have (Ra, R
b, Rc, Rd) = (1, 0, 0, 0) is output. Therefore, the output to the digital information processing circuit 102 is synchronized with the rising edge of CLK4 (A ′,
B ', C', D ') = (1, 0, 0, 0).

Next, the signal input to the input signal control circuit 101 is synchronized with the rising edge of the clock CLK3,
(Ain, Bin, Cin, Din, cont) =
(1,0,0,0,1) → (1,0,0,0,0). When the clock CLK3 rises, (R
A, RB, RC, RD, Rcont) = (1, 0, 0,
0, 1), the control circuit 110 causes the control signal co
Detects only state transition of nt. Therefore, the control circuit 11
0 is synchronized with the rising edge of the clock CLK4 (R
FA, RFB, RFC, RFD) = (1,1,1,1)
Is output as follows. In addition, the output signals of the F / Fs 140 to 143 are synchronized with the rising edge of CLK4 (R
A, RB, RC, RD) = (1, 0, 0, 0).
Therefore, (RFA, RFB, RFC, RFD) = (1,
1, 1, 1) and (RA, RB, RC, RD) = (1,
0, 0, 0), the conversion circuits 130 to 133
a, Rb, Rc, Rd) = (0, 1, 1, 1) is output. Therefore, the digital information processing circuit 1
The output to 02 is synchronized with the rising edge of CLK5,
(A ′, B ′, C ′, D ′) = (0, 1, 1, 1). The subsequent operation of the input signal control circuit 101 is similarly performed according to the operation of each logic circuit. Through the above operation, in the input signal control circuit 101, the signal converted by the output signal control circuit on the transmission side is correctly restored to the signal before conversion.

As described above, according to this embodiment, by providing the output signal control circuit for converting the signals output from the digital information processing circuit, the status can be maintained without reducing the number of output signals. The effect of reducing the number of transition signals can be obtained. Further, by providing an input signal control circuit in the digital information processing circuit on the receiving side and receiving a control signal indicating whether or not there is signal conversion from the output signal control circuit, the input signal control circuit performs signal conversion on the transmitting side. It is possible to restore the correct signal before the operation and supply the correct signal to the digital information processing circuit in the subsequent stage.

Further, since the output signal control circuit for reducing the number of signals that transit to the simultaneous state is constituted by the logic circuit, compared with the slew rate control, which is more effective depending on the operating environment such as temperature, the change in the operating environment can be prevented. It is possible to obtain an effect that noise reduction can be reliably expected.

Next, the transmission error detection circuit which operates by using the signal of the input signal control circuit according to the present invention will be described. FIG. 9 is a circuit diagram showing an example of one form of the transmission error detection circuit according to the present invention.
It is connected to the input signal control circuit 101 and the digital information processing circuit 102 already described.

Now, the transmission error detection circuit 301 will be described with reference to FIGS. 9 and 10. As described above, the input signal control circuit 101 receives the signal transmitted from the output signal control circuit 1 on the transmission side shown in FIG. The transmission error detection circuit 301 is a circuit for detecting whether a transmission error has occurred due to noise or the like in the transmission path from the output signal control circuit 1 on the transmission side to the input signal control circuit 101 on the reception side. Transmission error detection circuit 301
Uses a signal generated by the control circuit 110 to detect a transmission error. Specifically, the EXO shown in FIG.
Signal XORE generated by R211 and signal conversion detection unit 1
The signals XORA, XORB, XORC, and XORD generated by 60, 170, 180, and 190 are used as input signals.

The operating principle of the transmission error detection circuit is as follows. Of the four signals Ain, Bin, Cin, and Din input to the input signal control circuit 101, the number of signals that simultaneously transit to the state is always two or less, and the control signal cont input to the input signal control circuit 101 is in the state. When making a transition, the number of signals that make a state transition at the same time among the signals Ain, Bin, Cin, and Din is 1 or less. That is,
On the receiving side, monitor the number of simultaneous state transitions of the input signal,
When a state transition operation other than the above conditions is detected, it can be determined that an error has occurred during transmission. This determination circuit is the transmission error detection circuit 301.

Therefore, the function of the transmission error detection circuit 301 is to detect the case where the number of signals of the signals Ain, Bin, Cin, and Din whose state transition is 2 or 3 or more. More specifically, the transmission error detection circuit 301
Generates a high-level alarm signal when the number of signals of which the state transition among the signals Ain, Bin, Cin, and Din is 3 or more. Further, when the control signal cont transits to the state, that is, when the control signal cont indicates that signal conversion has been performed on the transmission side, the transmission error detection circuit 30
No. 1 generates an alarm signal in a high level state when the number of signals that make a state transition among the signals Ain, Bin, Cin, and Din is 2 or more. When the high-level alarm signal is received from the error detection circuit 301, the digital information processing circuit 102 on the receiving side determines that the received signal has an error, and performs processing such as a resend request.

Now, the specific structure and operation of the transmission error detection circuit 301 will be described. EXOR in FIG.
The gate 310 inputs the signals XORA and XORB,
The XOR gate 311 inputs the signals XORC and XORD. Similarly, NOR gate 312 provides signals XORA,
XORB is input, and the NOR gate 313 receives the signal XOR.
Input C and XORD. Also, the AND gate 314
Inputs signals XORA and XORB, and AND gate 3
15 inputs the signals XORC and XORD. further,
The OR gate 316 inputs the signals XORC and XORD.

The AND gate 317 is the EXOR gate 3
The output signal of 10 and the output signal of the EXOR gate 311 are input. When only the signals XORA and XORC are in the high level state, when only the signals XORA and the signal XORD are in the high level state, when only the signals XORB and the signal XORC are in the high level state, only the signals XORB and the signal XORD are in the high level state AND in either case
The gate 317 outputs a high level signal. In other words, when only the signals Ain and Cin make a state transition, when only the signals Ain and Din make a state transition, when only the signals Bin and Cin make a state transition, the signal Bin,
In either case where only Din makes a state transition, A
The ND gate 317 outputs a high level signal.

The AND gate 318 is the NOR gate 31.
3 and the output signal of the AND gate 314 are input. When only the signals XORA and XORB are in the high level state, the AND gate 318 outputs the signal in the high level state. In other words, the AND gate 318 outputs a signal in the high level state when only the signals Ain and Bin make the state transition.

The AND gate 319 is the NOR gate 31.
2 and the output signal of the AND gate 315 are input. When only the signals XORC and XORD are in the high level state, the AND gate 319 outputs the signal in the high level state. In other words, the AND gate 318 outputs a signal in the high level state when only the signals Cin and Din make a state transition.

As described above, the AND gates 317, 318, 31.
The high-level signal of any one of 9 causes the input signal Ai
A case where two signals among n, Bin, Cin, and Din make a state transition is detected. These AND gates 317,
The output signals of 318 and 319 are input to the OR gate 322, and the output signal of the OR gate 322 is input to the AND gate 324 as the signal T2. On the other hand, the AND gate 324 inputs the signal XORE. The signal XORE is
It is a signal indicating whether or not the signal conversion is performed in the output signal control circuit 1 on the transmission side, and indicates that the signal conversion is performed when the signal XORE is in the high level state. Therefore,
The high-level output signal of the AND gate 324 is subjected to signal conversion on the transmission side, and the signals Ain, Bin, Cin, D
It is shown that two signals that change state in are detected. That is, the high-level output signal of the AND gate 324 is the input signals Ain, Bin, Cin, D on the transmission path.
Indicates that a transmission error has occurred in in. The output signal of the AND gate 324 is the OR gate 32 as the signal CT2.
5 is input to the OR gate 325 and the alarm signal AL
The M is output to the digital information processing circuit 102.

Then, the AND gate 320 causes the EXOR
The output signal of the gate 310 and the output signal of the AND gate 315 are input. Signal XORA, signal XORC, signal X
In the case where only the ORD is in the high level state, the signal XORB, the signal XORC, or the signal XORD is in the high level state, the AND gate 320 outputs the signal in the high level state. In other words, the signals Ain, C
When only in and Din change state, signals Bin and C
In either case where only in and Din transit to the state transition, the AND gate 320 outputs a high level signal.

The AND gate 321 is the AND gate 31.
4 and the output signal of the OR gate 316 are input. When only the signals XORA, XORB, and XORC are in the high level state, the signals XORA, XORB, and
When only the signal XORD is in the high level state, the signal XOR
AND gate 3 when A, signal XORB, signal XORC, or signal XORD is in the high level state
21 outputs a high level signal. In other words, when only the signals Ain, Bin, and Cin are in the state transition, when only the signals Ain, Bin, and Din are in the state transition, and when the signals Ain, Bin, Cin, and Din are in the state transition, the AND operation is performed. The gate 321 outputs a high level signal.

As described above, the input signal Ain, Bi is input by the high level signal of either of the AND gates 320, 321.
A case where three or more signals among n, Cin, and Din make a state transition is detected. These AND gates 320 and 32
The output signal of 1 is input to the OR gate 323, and the output signal of the OR gate 323 is input to the OR gate 325 as the signal T34. Therefore, the high-level output signal T34 of the OR gate 324 indicates that the signal conversion is performed on the transmission side, and three or more signals that change the state among the signals Ain, Bin, Cin, and Din are detected. That is, O
The high level output signal T34 of the R gate 323 indicates that a transmission error has occurred in the input signals Ain, Bin, Cin and Din on the transmission path. The OR gate 325 outputs the alarm signal ALM to the digital information processing circuit 102 based on the signals CT2 and T34.

FIG. 10 is a waveform diagram for explaining the operation of the transmission error detection circuit of FIG. 9, and a case where a transmission error occurs in the shaded portion of the input signal Din will be described.
The input units 150 to 155 of FIG. 6 have signals Ain, Bin, Cin, Din, cont, and CLK as shown in the figure.
Is entered. Here, consider the case where the signal Din is input in the low level state from the rising edge of the clock CLK3 to the rising edge of the clock CLK4 in the high level state due to a transmission error.

At the rising edge of the clock CLK3, FIG.
Signal conversion detection units 160, 170, 180, 190, 2 of
00 is (XORA, XORB, XORC, XORD,
XORE) = (0,1,0,1,1) is output,
The transmission error detection circuit 301 inputs these signals. Since only the signals Bin and Din undergo the state transition, the AND 317 ORs the signals in the high level state as described above.
It is sent to the gate 322. Therefore, as shown in FIG. 10, the signal T2 output from the OR gate 322 becomes (T2) = (0 → 1) at the rising edge of the clock CLK3, and the signal T2 is sent to the AND gate 324.
On the other hand, since the signal XORE is in the high level state at the time of the clock signal CLK3, the signal CT2 output from the AND gate 324 is (C
T2) = (0 → 1), and the signal CT2 is sent to the OR gate 325. Therefore, the alarm signal ALM output from the OR gate 325 becomes (ALM) = (0 → 1) at the rising edge of the clock CLK3, and the high-level alarm signal ALM is sent to the digital information processing circuit 102.

Further, the signal Di in the clock CLK3
Due to the transmission error of n, the signal Din is transferred to the next clock C
State transition also occurs in LK4. Therefore, the transmission error detection circuit 301 continues to send the high-level alarm signal ALM to the digital information processing circuit 102 even at the clock CLK4.

For reference, the output signals A'and B'of the input signal control circuit 101 in FIG. 6 are shown when the transmission error does not occur and a normal signal is input, and when the transmission error occurs. The waveforms of C, C'and D'are shown in FIG.

As described above, by providing the input signal control circuit with the transmission error detection circuit for monitoring each input signal, it is possible to reduce the number of state transition signals without reducing the number of output signals and perform signal conversion. It is also possible to detect a transmission error that occurs on the transmission path from the output signal control circuit to the input signal control circuit that performs inverse signal conversion.

As described above, in the embodiment of the present invention, it is configured to detect whether simultaneous state transition occurs for n output signals and perform signal conversion. However, the present invention is as follows. The present invention is not limited to the configuration in which n output signals are collectively controlled. For example, it is possible to adopt a configuration in which n output signals are divided into an arbitrary number and the divided signal groups are independently applied to each of the divided signal groups to carry out signal conversion. In this case, the number of control signals cont is a divided number. For example, when the number of output signals is 8, and the number of control signals cont is 2, when control is performed in units of 4 signals.

Further, in the above-mentioned embodiment, the circuit for reducing the number of signals that undergo the state transition among a plurality of output signals has been described. However, this technical idea conversely changes the output signal to the state when there is no state transition signal. It can be applied to signal conversion so as to make a transition. For example, the signal generators Pa and P
b, Pc, Pd generated signals A, B,
If neither C nor D transits, the signals A, B,
The conversion circuits 30 to 33 in FIG. 2 perform signal conversion on any two signals of C and D, and the control signal cont
The polarity of is inverted. Signals Ain, Bin, Cin, D
Any two of the ins undergo a state transition and the control signal co
When nt makes a state transition, signals Ain, Bin, C
Since neither in nor Din originally causes a state transition, the input signal control circuit 101 of FIG.
The conversion circuits 120 to 123 perform reverse conversion so that none of Bin, Cin, and Din undergoes state transition. This method enables signal restoration on the receiving side. This method is effective when the clock is extracted using the PLL circuit on the receiving side. This is because the PLL circuit synchronizes from the change point of the signal, and if the low level state or the high level state continues, the synchronization may be lost on the receiving side.

[0139]

As described above, the digital information processing apparatus of the present invention is provided with the output signal control circuit which performs signal conversion for a plurality of output signals, and thereby makes the state transition without reducing the number of output signals. The effect that the number of signals can be reduced is obtained. Further, by providing an input signal control circuit in the digital information processing circuit on the receiving side and receiving a control signal indicating the presence or absence of signal conversion from the output signal control circuit,
The input signal control circuit can restore the correct signal before the signal conversion is performed on the transmitting side, and can supply the restored signal to the digital information processing circuit in the subsequent stage.

[Brief description of drawings]

FIG. 1 is a block diagram showing an output signal control circuit and an input signal control circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an output signal control circuit according to an embodiment of the present invention.

FIG. 3 is an internal circuit diagram of a conversion circuit of an output signal control circuit.

FIG. 4 is a circuit diagram showing an embodiment of a control circuit of the output signal control circuit.

FIG. 5 is a time chart showing waveforms of various signals in the output signal control circuit.

FIG. 6 is a block diagram showing an input signal control circuit according to an embodiment of the present invention.

FIG. 7 is a circuit diagram showing an embodiment of a control circuit of the input signal control circuit.

FIG. 8 is a time chart showing waveforms of various signals in the input signal control circuit.

FIG. 9 is a circuit diagram showing a transmission error detection circuit according to an embodiment of the present invention.

FIG. 10 is a time chart showing waveforms of various signals in the transmission error detection circuit.

[Explanation of symbols]

1, 410 Output signal control circuit 2, 102 Digital information processing circuit 10, 110 Control circuit 11, 59, 163, 173, 183, 193, 31
6, 322, 323, 325 OR gate 12, 201, 312, 313 NOR gate 13 JK flip-flop 20, 21, 22, 23, 40, 41, 42, 43, 6
5, 75, 85, 95, 120, 121, 122, 12
3, 140, 141, 142, 143, 144, 16
4, 174, 184, 194 flip-flops 30, 31, 32, 33, 130, 131, 132, 1
33 conversion circuits 50, 51, 52, 53, 430-1 to 430-n,
431, 470-1 to 470-n output section 58, 61, 62, 63, 71, 72, 73, 81, 8
2, 83, 91, 92, 93, 161, 171, 18
1, 191, 211, 310, 311 EXOR gates 60, 70, 80, 90 Simultaneous operation detection units 64, 74, 84, 94, 162, 172, 182, 1
92, 202, 314, 315, 317, 318, 31
9, 320, 321, 324 AND gate 101, 450 Input signal control circuit 150, 151, 152, 153, 154, 155,
400-1 to 400-n, 440-1 to 440-n, 4
41 input section 160, 170, 180, 190, 200 signal conversion detection section 301 transmission error detection circuit 412, 452 signal conversion circuit 411, 451 detection circuit

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Kenichi Saito 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (6)

[Claims] 1. A plurality of signal input sections and a first signal input from each of the plurality of signal input sections are predicted to have a state transition at a predetermined timing, and the state transition is predicted. A detection circuit which, when detecting that the number of the generated first signals is larger than a predetermined number, sends out an instruction signal instructing to perform signal conversion for changing the state of the first signals; A signal conversion circuit that inputs the first signal and the instruction signal, performs the signal conversion on the first signal based on the instruction signal, and outputs the signal as a second signal; When the circuit detects that the number of the first signals in which the state transition occurs is larger than a predetermined number, the circuit sends the indication signal to the receiving circuit which receives the second signal. , The second signal is before First
A digital information processing apparatus, which sends out a control signal indicating that the signal has been subjected to the signal conversion. 2. The digital information processing apparatus according to claim 1, wherein the digital information processing apparatus further inputs the first signal between each of the plurality of input units and the signal conversion circuit, The detection circuit includes a plurality of flip-flops that hold the first signal for one clock and then send the signal to the signal conversion circuit. The detection circuit includes the first signal before being input to the second signal and the flip-flop. A digital information processing apparatus, comprising: inputting a signal and comparing the input first signal and input second signal to predict whether or not a state transition will occur. 3. The digital information processing apparatus according to claim 1, wherein the number of the signal input units is n, and the number of the first signals in which the state transition occurs is (n−1) in the detection circuit. When it is detected that the state transition is generated, the instruction signal for instructing to perform the signal conversion on a part of the plurality of first signals in which the state transition occurs is transmitted, and the state transition is Digital information processing, characterized in that, when it is detected that the number of the generated first signals is n, the instruction signal for instructing to perform the signal conversion on all the first signals is transmitted. apparatus. 4. A plurality of signal input sections, and a first conversion table having a correspondence relationship between a set of signals in which a state transition occurs and a set of signals to be subjected to a first signal conversion for changing the states of the signals. , Predicting whether or not the state transition occurs at a predetermined timing for the first signals respectively input from the plurality of signal input units, and based on the second conversion table, the first signals A first detection that sends an instruction signal for instructing to perform the first signal conversion on the first signal and a control signal indicating that the first signal conversion has been performed on the first signal. A circuit, the first signal and the first instruction signal are input, the first signal conversion is performed on the first signal based on the first instruction signal, and as a second signal First signal conversion circuit to output and state transition occurs A second conversion table corresponding to the first conversion table, having a correspondence relationship between a signal set and a signal set to be subjected to a second signal conversion for changing a signal state; the control signal; And a second instruction signal for instructing to perform the second signal conversion based on the second conversion table by detecting whether a state transition occurs at a predetermined timing. A second detection circuit for sending, a second signal and the second instruction signal are received, and the second signal conversion is performed on the second signal based on the second instruction signal. , And a second signal conversion circuit for outputting as a third signal. 5. A receiving circuit for receiving a plurality of first signals and a second signal indicating that the first signals have been subjected to signal conversion, and a predetermined signal state relating to the plurality of signals. Of the first signal and the signal state of the plurality of first signals are compared at a predetermined timing, and when the two do not match, the first signal causes a transmission error. And a control circuit that generates a signal that warns of a transmission error. 6. A plurality of signal input sections and a first signal input from each of the plurality of signal input sections are predicted as to whether or not a state transition will occur at a predetermined timing, and which of the first No. 1 signal, when detecting that no state transition occurs, a detection circuit for sending an instruction signal for instructing to perform signal conversion for changing the state of at least one of the first signals; and the first signal. And a signal conversion circuit which inputs the instruction signal, performs the signal conversion on the first signal based on the instruction signal, and outputs the second signal as a second signal. When it is detected that the state transition of the first signal does not occur, the receiving circuit which sends out the instruction signal and receives the second signal,
A digital information processing apparatus, which sends a control signal indicating that the signal conversion has been performed on the first signal.