JPH09232968A - Variable length code generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate a variable length code not emulating a prescribed unique word systematically by correcting a bit pattern of each code word generated by a prefix processing means. SOLUTION: A prefix processing section 12 receives a symbol number, an incident probability of each symbol, and a parameter to generate a prescribed dummy code word and decides a bit pattern of all code words by using a variable length coding algorithm from generated incidence probability and corrected incident probability. A suffix processing section 13 applies suffix check of each code word as to the variable length code generated by the processing section 12 to revise the bit pattern or to use an additional bit at need.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for generating a variable-length code that does not emulate a unique word and is used in a system for transmitting signals using a binary code.

[0002]

2. Description of the Related Art Generally, in a digital signal transmission system using a binary code, a variable length code (VLC) typified by a Huffman code is often used in order to perform efficient lossless coding. On the other hand, synchronization recovery / error correction techniques are often combined to provide resistance to distortion during transmission and storage. In particular, a unique word having an exclusive bit pattern is also adopted in international standard image coding in order to reduce the influence of transmission path distortion on a decoded image.

A bit stream composed of variable-length codes may lose synchronization between code words due to transmission path distortion or the like, resulting in continuous erroneous decoding. For example, the structure of an image such as slices in an image frame By inserting the unique word into the bitstream at the synchronized timing, the erroneous decoding is limited to the range up to the unique word existing next to the distortion occurrence point.

The unique word carries coding information so that it can be correctly recognized in the case where the unique word itself is not distorted with respect to any appearance pattern of symbols and any occurrence pattern of distortion. It is necessary to have a unique bit pattern that does not match (emulate) some or all of the other codewords that represent it or any combination thereof.

[0005]

Therefore, in designing a variable-length code, consideration must be given to satisfying this condition. However, there has been no systematic generation method of variable length code that satisfies these conditions, so that some codewords are disabled or a marker bit that prevents emulation is inserted at an appropriate position. However, much effort has also been paid to verify that the generated code does not cause emulation.

Therefore, an object of the present invention is to provide a variable-length coding apparatus capable of systematically generating a variable-length code that does not emulate a unique word having a specific pattern, while taking coding efficiency into consideration. Is to propose.

[0007]

According to the invention, the length N
Unique word creating means for creating a unique word composed of consecutive bits "0" of (N is a plurality of natural numbers),
A prefix processing means for creating each code word having a consecutive length of bits "0" in the prefix of the code word is s (s is a natural number) or less, and including at least one bit "1", and the prefix processing means. The consecutive length of bit "0" in the suffix of each codeword is t (t is a natural number) or less, the consecutive length of bit "0" in each codeword is less than N, and s + t <N
And a suffix processing means for modifying the bit pattern of each code word so that the variable length code generating device is provided.

The requirements for the characteristics of the unique word and the structure of the variable length code to prevent the variable length code from emulating the unique word are as follows.

As a characteristic of the unique word, it is assumed that the unique word satisfies the following conditions. (Assumption 1) The unique word used in the code to be handled is of a single type. (Assumption 2) It is assumed that the unique word is composed of only bit "0".

Assumption 1 is an important condition for facilitating the generation of the variable length code, but this does not limit the usage of the unique word. If you need to use multiple types of unique words, use the single type of unique word specified here as an escape symbol,
An extension code assigned to each function may be placed after that. Assumption 2 is easy to recognize in a real system.
It is a setting that is widely used and is an important condition for facilitating the generation of variable-length codes. The bit length of the unique word is represented by N.

The requirement for a variable length code that does not emulate a unique word depends on the characteristics of the unique word based on the above assumption and the appearance pattern of the variable length code set (not the appearance pattern of the code word in each code). To do. Regarding the appearance pattern of the variable length code set, first, the simplest infinite loop transmission system with a single code is assumed. In this system, each codeword appears based only on the probability of occurrence of a symbol in the code. The requirements for each codeword in this system are as follows. (Condition 1) A codeword composed only of bit "0" is prohibited. (Condition 2) The maximum continuous length of bit "0" in the prefix of each codeword is s or less. (Condition 3) The maximum continuous length of bit "0" in the suffix of each codeword is t or less. (Condition 4) s + t <N. (Condition 5) The maximum continuous length of bit "0" in the middle of each codeword is less than N.

(Condition 1) is a condition for preventing the unique word from being emulated when the same code word appears consecutively. (Condition 2), (Condition 3), and (Condition 4) are conditions that prevent a combination of two codewords from emulating a unique word. Also,
(Condition 5) is a condition for preventing emulation due to inclusion of a unique word in a code word. Satisfying (Conditions 1 to 5) at the same time is a necessary and sufficient condition not to cause unique word emulation,
According to the above-described configuration of the present invention, this condition will be achieved. That is, according to the present invention, it is possible to systematically generate a variable length code that does not emulate a unique word having a specific pattern.

The prefix processing means uses consecutive s +
It is preferable that it is a means for generating a variable length code by introducing a dummy code word consisting of only one bit "0".

The prefix processing means determines the occurrence probability p _d.
For generating the dummy codeword of the above, and the modified occurrence probability obtained by modifying each occurrence probability p _i of another symbol using the occurrence probability p _d

[Outside 3] , A generated occurrence probability p _d and a modified occurrence probability

[Outside 4] It is preferable to include a prefix processing code generation means for determining the bit patterns of all code words by using the variable length coding algorithm.

The suffix processing means measures the suffix state of each code word, and the consecutive length of the bit "0" in the suffix of this code word is t or less and N-1 consecutive bits in the code word. It is also preferable to include a means for outputting the code word without using the additional bit when the bit "0" of 1 is not included.

If the consecutive length of the bit "0" in the suffix of the code word is t or less and there are N-1 consecutive "0" bits in the code word, the suffix processing means generates the N-1. It is also preferable to further include means for inserting an additional bit of bit "1" after each bit "0".

It is also preferable that the suffix processing means further includes means for inserting an additional bit of the bit "1" when the continuous length of the bit "0" in the suffix of the code word exceeds t.

The suffix processing means is preferably means for performing parameter measurement and bit pattern correction processing on the tree representation.

In one embodiment of the present invention, there is further provided a parameter optimizing means for modifying the parameters s and t to optimum values for improving the coding efficiency.

The parameter optimizing means measures the average code length of the variable length code output from the suffix processing means and the number of additional bits added by the suffix processing means, and the measured average code length and the number of additional bits. And means for modifying the parameters s and t accordingly.

In one embodiment of the present invention, the consecutive length of bits "0" in the prefix of the codeword is less than or equal to s, the codeword contains at least one bit "1", and the suffix of the codeword is The continuous length of bit "0" is t or less, and bit "0" in the codeword
Means for generating a fixed-length code having a continuous length of less than N and s + t <N are further provided.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram schematically showing the configuration of an embodiment of the variable length code generation device of the present invention.

In the figure, 10 is the number of symbols n, the occurrence probability p _{i of} each symbol, and the unique word length N (N
Is a plurality of natural numbers), the number E of unique word types, and the internal processing parameters s and t. The input unit 10 includes a unique word creation unit 11, a prefix processing unit 12, and a suffix processing unit 13.
And the output unit 14 for outputting the obtained variable length code and unique word are sequentially connected in series.

As shown in FIG. 2, the unique word creating section 11 includes a word creating section 11a which creates a word consisting of consecutive bits "0" having a length N, and E when the number of types E is E≥2. It is mainly composed of a plurality of word generators 11b that create unique words of variable length codes or fixed length codes of various types. When only a single type of unique word is requested (E = 1), a word consisting of consecutive bits “0” of length N generated by the word generation unit 11a is output as it is as a unique word. When multiple types of unique words are requested (E ≧ 2)
Is the word generator 1 in the multiple word generator 11b.
A plurality of unique words are generated by using the above-mentioned single unique word generated in 1a as an escape code and providing an extension code behind it.

As shown in FIG. 3, the prefix processing unit 12 has a parameter s (a natural number that defines the maximum continuous length of the bit "0" in the prefix of the codeword) in addition to the number of symbols n and the occurrence probability p _i of each symbol. ) And a parameter t (a natural number that defines the maximum continuous length of bits “0” in the suffix of the codeword).
And a dummy codeword generating unit 12b that generates a dummy codeword having only s + 1 consecutive bits “0” and an occurrence probability of p _d , and the occurrence probability of other symbols using the 12c occurrence probability p _d. Modified occurrence probability with modified p _i

[Outside 5] And the generated occurrence probability p _d and the corrected occurrence probability p _d

[Outside 6] To the prefix processing code generation unit 12d that determines the bit patterns of all code words by using the variable length coding algorithm.

The above-mentioned (condition 1) and (condition 2) for the variable-length code are simultaneously satisfied by performing this prefix processing. That is, this is consecutive s + 1
This is possible by introducing a dummy codeword consisting only of "0" bits. If a dummy codeword with this property is present in the code, all other codewords are:
It is clear that (Condition 1) and (Condition 2) are satisfied. However, the use of the dummy codeword causes a deterioration in coding efficiency. The dummy code word is used only for appropriately determining the bit pattern of another code word, and is a code word that is not used during actual information transmission.

Assuming that the occurrence probability corresponding to the dummy codeword is p _d , the modified occurrence probability for determining other codewords.

[Outside 7] Is corrected from the actual occurrence probability p _i of each symbol using p _d, and is calculated as follows.

[Equation 1] However, 1 ≦ i ≦ n, and n is the total number of code words (the number of symbols) excluding dummy code words. p _d and

[Outside 8] Therefore, the bit patterns of all the code words including the dummy code word are determined by the normal variable length code generation algorithm represented by the Huffman code. As an example, Table 1 shows the probabilities of occurrence of each symbol, the corrected probabilities of occurrence of each symbol and dummy codeword, and the reference Huffman code C ₁₀ obtained from the probabilities of occurrence, (condition 1) and (condition 2). The variable-length code C _{11 to be} satisfied and the average code length of each code are shown. In this example, the dummy codeword occurrence probability p _d is p _d = 0.
It is assumed that the length of the dummy codeword is 3 (s
= 2, t = 0, N = 3).

[0029]

[Table 1]

The value of p _d that gives a certain value of s is obtained by the following equation since the entropy of the symbol having the occurrence probability P is expressed by −log ₂ P. p _d ≈1 / 2 ^{s + 1} (Equation 2) This is an approximate expression, but the actual length of the dummy codeword is s.
If it is longer than +1, a proper codeword can be obtained by making p _d larger than 1/2 ^{s + 1} . If it is short, the opposite process may be performed.

In another embodiment of the present invention described later, the value of this parameter s is optimized. The value of s is limited in range as follows. 1 ≦ s + 1 ≦ L _max +1 (Equation 3) However, L _max is the maximum code word length in the reference variable-length code when a dummy code word is not included, and has the following properties.

[Equation 2]

As shown in FIG. 4, the suffix processing section 13 performs a terminal preprocessing section 13a for preprocessing so that the final bit does not have "0", and a tree structure for measuring the parameters of the tree structure at all levels. The parameter measurement unit 13b, the suffix state measurement unit 13c that measures the suffix state of each code word, and the determination that the continuous length of the bit “0” in the suffix of the code word is t or less and the additional bit is not used. The determination processing unit 13d of 1 and that the continuous length of the bit "0" in the suffix of the code word is t or less and there are N-1 consecutive bits "0" in the code word. And a third determination processing unit 13f that inserts an additional bit of bit "1" after the N-1 number of bits "0".
And a fourth determination processing unit 13g that determines that the continuous length of the bit "0" in the suffix of the codeword exceeds t and inserts an additional bit of the bit "1", and a symbol after the above processing is completed. And a sorting unit 13h that sorts in the order of occurrence probabilities.

In the suffix processing section 13,
Suffix inspection of each code word is performed on the variable length code generated by the prefix processing unit 12, and the bit pattern is changed or if necessary so as to satisfy the above (condition 3), (condition 4) and (condition 5). The additional bits are used. This process is performed on the tree representation of the binary code. For example, the Huffman code C ₁₀ and the variable-length code C ₁₁ subjected to the prefix processing described above are expressed as shown in FIGS. 5 and 6, respectively. In these figures, the leaf represents the terminal bit of the codeword, and the node represents the bit in the middle of the codeword. In this configuration, the suffix of each codeword is determined to require additional bits at each node or leaf. T for suffix
Since consecutive bits "0" up to the bit are allowed,
It is necessary to check the need for additional bits up to the node on level t for each leaf.

The inspection and additional bit processing will be described in detail below.

In the terminal preprocessing section 13a, as many code words as long as t bits or less are preprocessed so that the last bit has "0". This is possible by using the known equivalent transformation that exchanges nodes and leaves at the same level while maintaining the average code length. This pre-processing has the effect of reducing the sequence of "0" bits in the longer word suffix.

The tree structure parameter measuring unit 13b measures the tree structure parameters at all levels. n _i : the number of leaves in level i r _i : the total number of nodes and leaves in level i

(Equation 3)

In the suffix state measuring section 13c, the suffix state parameter is set to level i (i>
Measure at t). _mi : number of leaves having terminal bit "0" at level i u _{it-1, j} : total number of leaves and nodes in which all j bits consecutive from level _it-1 are "0", where u _{it-1 , l} = r _it / 2 (Equation 7) u _{it-1, j + 1} = u _{it-1, j-} m _{it-1 + j} (0 <j <t) (Equation 8)

The following determination processing is performed in the first determination processing section 13d.

(Equation 4) , No additional bits are needed at level i. In this case, there are no nodes or leaves having consecutive "0" s for t bits or more. Codewords are assigned by the equivalent transformation so that nodes with long consecutive "0" bits terminate at this level. At this time, if n _i ≤r _it / 2, then m ₁ = n _i ...... (Equation 9) Otherwise, m _i = r _it / 2 ...... (Equation 10)

The following determination processing is performed in the second determination processing section 13e.

(Equation 5) , No additional bit is required at level i.
However, there are nodes or leaves that have consecutive "0" s longer than t bits. A codeword is assigned by the equivalent transformation so that nodes with t bits or less and as long as possible consecutive "0" bits terminate at this level. In this _{case, n i ≦ r it / 2} -u it-1, t + 1 if, m _i = n _i ............ (Equation 11) _{Otherwise, m i = r it / 2} -u it- _{1, t + 1} ………… (Equation 12)

The following determination processing is performed in the third determination processing section 13f. If there is one of the remaining r _i -n _i nodes that has a N-1 bit length of "0" in the suffix, then a bit "1" is inserted at this level. In order to maintain the integrity of the code necessary for the processing of the lower layer, the virtual leaf is set at the position conjugate with the additional bit (see FIG. 7). These are all terminated with "0",
It will not be changed by the subsequent equivalent conversion. In this process, when determining the node that uses the additional bit, the node with the smallest sum of the occurrence probabilities of leaves below level i is selected as the target, and the equivalent conversion is executed so as to minimize the deterioration of the coding efficiency. To do. In the example, three consecutive
Additional bit is level 4 to prevent "0" of bit
And used at level 7. Through this process, the requirement 5 is satisfied.

The following determination processing is performed in the fourth determination processing section 13g.

(Equation 6) , Then n _i + u _{it−1, t + 1} −r _i leaves require an additional bit “1”. The additional bits are added in order from the leaf having the end bit of “0”, which has a long continuous bit length of “0”. In order to maintain the integrity of the code necessary for the processing of the lower layer, the virtual leaf is set at the position conjugate with the additional bit (see FIG. 7). These are all terminated with "0" and will not be changed by the subsequent equivalent conversion or the like. The parameters n _i are changed as follows. n _{i + 1} = n _{i + 1} + 2 × (n _i + u _{it-1, t + 1} −r _i ) (Equation 13) In this process, the level i is determined when the node using the additional bits is determined. The node having the smallest sum of the occurrence probabilities of the following leaves is selected as the target, and the equivalent conversion is executed so as to suppress the deterioration of the coding efficiency to the minimum. In this example, additional bits are used at level 5 to prevent suffixes of consecutive "0" bits. By this process, (Condition 3) and (Condition 4) are satisfied.

The next level suffix is checked (i
= I + 1), the tree structure parameter measurement unit 13b, the suffix state measurement unit 13c, the first determination processing unit 13d, the second determination processing unit 13e, the third determination processing unit 13f, and the fourth determination processing unit described above at this level. The processing of the determination processing unit 13g is repeated.

By performing processing for each level in this manner, after the inspection of all levels is completed, the sorting unit 13h
In, symbols are sorted in order of occurrence probability and codewords are reallocated in order of bit length. In this example,
The code C ₁₁ is converted to the code C ₁₂ shown in Table 1 and FIG. 7 which does not cause emulation.

In all of the above processing steps, the equivalent conversion does not process the dummy codeword, the converted codeword, and the virtual codeword.

FIG. 8 is a block diagram schematically showing the configuration of another embodiment of the variable length code generation device of the present invention.

In the figure, 80 is the number of symbols n, the occurrence probability p _{i of} each symbol, and the unique word length N (N
Is an input unit to which a plurality of natural numbers) and the number E of unique word types are input. A unique word creation unit 81, a prefix processing unit 82, a suffix processing unit 83, and an output unit 84 that outputs the obtained variable length code and unique word are sequentially connected to the input unit 80 in series. In this embodiment, a parameter optimization unit 85 for parameters s and t is further provided. The parameter optimization unit 85 receives the output of the suffix processing unit 83 and the output of the input unit 80, performs optimization processing of the parameters s and t so as to improve the coding efficiency of the code that does not cause emulation, and performs optimization. The output parameters s and t are output to the prefix processing unit 82. The configurations of the unique word creation unit 81, the prefix processing unit 82, and the suffix processing unit 83 in this embodiment are the same as those in the embodiment of FIG.

As shown in FIG. 9, the parameter optimizing unit 85 calculates initial values of the parameters s and t from the length N of the unique word given from the input unit 80 (s + t <
N) initial value calculation unit 85a and suffix processing unit 8
3 measures the average code length of the variable length code and the number of additional bits added by the suffix processing unit 83, and the parameters s and t according to the measured average code length and the number of additional bits. It includes a determination unit 85c that determines whether to correct, a correction unit 85d that corrects the parameters s and t according to the determination, and an output unit 85e that outputs the corrected parameters s and t to the prefix processing unit 82. There is.

The judging section 85c and the correcting section 85d are responsive to the given parameter N (unique word length).
The value of the parameter s is optimized to be as large as possible within the range that does not involve additional bits. More specifically, the parameter s is modified to a range that gives the minimum average code length of N−3 ≦ s ≦ N−1, and the parameter t is t = N−1−.
s to be corrected.

Hereinafter, the judging section 8 of the parameter optimizing section 85
5c and the optimization process of the parameters s and t in the correction unit 85d will be described in detail.

In the present embodiment, by introducing a dummy code, inserting an additional bit in a suffix or a code word, etc.,
When compared with the reference code having the smallest average code length, the coding efficiency is deteriorated. This deterioration is formulated by parameters that characterize the structure of the code, such as the occurrence probability and the number of consecutive "0" bits in the suffix, and the parameters that are conscious of unique words such as s, t, and N.

The deterioration of the coding efficiency due to the dummy codeword is expressed as follows. Since the length of each codeword is determined by the compact code generation algorithm based on the corrected occurrence probability,

(Equation 7) Becomes However,

[Outside 9] Is the length of the code word i, and 1 ≦ i ≦ n. Therefore,

(Equation 8) Becomes However,

[Outside 10] Represents the average length of the code after the prefix processing. The difference between the entropy and the average code length in the compact code is d, respectively for the reference code and the code after the prefix processing.

[Outside 11] When expressed as

[Equation 9] Becomes From Equations 2 and 16, the average code length after prefix processing is expressed as a function of the parameter s as follows.

(Equation 10) here,

[Outside 12] Is independent of s, it can be seen that the efficiency deterioration due to the dummy codeword is a monotonically decreasing function with respect to the parameter s.

The deterioration of the coding efficiency due to the suffix process is defined by the parameter t. The increment ΔL _add of the average code length due to the additional bits is as follows. ΔL _add = ΔL _addsuffix + ΔL _addmiddle ………… (Formula 19)

The influence of the additional bit on the suffix by the fourth determination processing unit (13g) in the suffix processing unit 83 is

[Equation 11] Becomes However,

[Outside 13] Is the maximum length of the code after suffix processing, last (i +
1) is the number of the codeword having the smallest occurrence probability at level i + 1, w _i = n _i + u _{it-1, t + 1} −r _i , p (i
+1, h) indicates the h-th highest occurrence probability of the code word of level i + 1. Since the number of nodes at level _it-1 is expressed as r _it-1 -n _it-1 , the following equation holds.

(Equation 12) Since r _it-1 and n _it-1 have no correlation with t, from equation 21, u _{it-1, t + 1} is a monotonically decreasing function with respect to the parameter t. Therefore, ΔL _addsuffix is a monotonically decreasing function with respect to the parameter t.

The influence of the additional bit in the code word by the second and third determination processing units (13e and 13f) in the suffix processing unit 83 is

(Equation 13) It is expressed as However, Num _addmiddle (t, N,
i) is the total number of additional bits in the codeword,

[Equation 14] It is. Here, v (i) is the number of nodes having suffix "0" bits from level i, Num
_termleaf (i, j) is the number of nodes terminated as leaves at level j without additional bits, Num
_addleaf (i, j) is the sum of the occurrence probabilities of all codewords in which the additional bits exist below the insertion node. Num
_{Since addmiddle} (t, N, i) is a monotonically decreasing function with respect to t and N, ΔL _addmiddle (t, N) is also t and N.
Is a monotonically decreasing function of.

From the above equations 18 and 20 to 22, the average code length of the code that does not cause emulation

[Outside 14] Is expressed by the following equation 24.

(Equation 15)

The following characteristics can be obtained from the above equations 18, 20, 20, and 24 and the above-mentioned condition of s + t <N (condition 4). (Characteristic 1) The average code length of the code that does not cause emulation as the parameter s increases.

[Outside 15] Becomes smaller. (Characteristic 2) The average code length of the code that does not cause emulation as the parameter t increases

[Outside 16] Becomes smaller. (Characteristic 3) The average code length of codes that do not cause emulation as the unique word length N increases

[Outside 17] Becomes smaller. (Characteristic 4) For a certain code, for a constant N, the minimum average code length determined by the balance between s and t

[Outside 18] Exists.

Parameter s for improving coding efficiency
A specific optimization process for the points t and t will be described below.

The probabilities of occurrence of each symbol for the English alphabet consisting of 26 symbols, and the reference Huffman code C ₂₀ obtained from these probabilities of occurrence, are shown in the left part of Table 2 below.

[0059]

[Table 2]

When s and N are changed within a range satisfying the above condition of s + t <N (condition 4), the average code length of the code that does not cause emulation changes as shown in FIG. The change in the total number of additional bits is shown in FIG. As described above, it is more advantageous to improve the coding efficiency by increasing t within the range satisfying the condition of s + t <N. Therefore, t = N-1-s.

From FIG. 10, when the code length N of the unique word is as short as N = 5 due to hardware restrictions, s = 3.
It can be seen that the minimum code length is obtained when. For this case, the modified occurrence probabilities of each symbol and dummy codeword, the variable length code C ₂₁ without emulation, and the average code length are shown in the middle part of Table 2. In this case, the coding efficiency deterioration with respect to the Huffman code is 2.91%. Further, it can be seen that when the code length N of the unique word is N = 11, which is relatively long, the minimum code length is obtained when s = 8. For this case, the modified probability of occurrence of each symbol and dummy codeword, the variable length code C ₂₂ without emulation, and the average code length are shown in the right part of Table 2. In this case, the coding efficiency deterioration of the Huffman code is as small as 0.04%.

The following points are verified from FIGS. 10 and 11. (Verification 1) In the case of N >> s, the average code length becomes shorter as s becomes larger. This agrees with (Characteristic 1) described above. (Verification 2) When N≈s or N >> t, the average code length decreases as t increases. This agrees with (Characteristic 2) described above. (Verification 3) When N ≧ 5, the minimum average code length is given by the balance between s and t. This agrees with (Characteristic 4) described above. (Verification 4) When N is large, an average code length close to the reference Huffman code C ₂₀ is obtained for some choices of s. (Verification 5) In the case of N ≧ 3, s ≦ N−1 or t ≧
2 does not require additional bits. This is Equation 20, Equation 2
It agrees with 3.

FIG. 12 shows the minimum average code length when the length N of the unique word changes and the parameter s giving it.
Shows the relationship. The following points are verified from the figure. (Verification 6) As N increases, the minimum average code length decreases, and an average code length close to the reference Huffman code C ₂₀ is obtained. This agrees with (Characteristic 3) described above. (Verification 7) s and t giving the minimum average code length are N-3.
≦ s ≦ N−1 or 0 ≦ t ≦ 2.

As a result, in order to improve the coding efficiency, each parameter should be N within the allowable range of the hardware.
It is optimal to make the value of s as large as possible, and to make the value of s as large as possible without adding bits.

FIG. 13 is a block diagram schematically showing the configuration of still another embodiment of the variable length code generation device of the present invention.

In the figure, 130 is the number of symbols n,
Occurrence probability p _{i of} each symbol, unique word length N
(N is a plurality of natural numbers) and the number E of unique word types are input units. The input unit 130 includes a unique word creation unit 131 and a prefix processing unit 132.
, The suffix processing unit 133, and the output unit 134 for outputting the obtained variable length code and unique word are sequentially connected in series, and the parameter optimization unit 135 for the parameters s and t is further provided. . In the present embodiment, the prefix processing unit 132 is also added.
Further, a fixed length code processing unit 136 is added in parallel to the suffix processing unit 133. The unique word creation unit 131 and the prefix processing unit 1 according to the present embodiment.
The configurations of 32, the suffix processing unit 133, and the parameter optimization unit 135 are the same as the respective configurations in the embodiment of FIG.

As shown in FIG. 14, the fixed length code processing unit 136 has a bit length determination unit 136a for determining the bit length M of the fixed length code (FLC) and a unique word having the determined bit length M. And a fixed length code generation unit 136b that generates a fixed length code that satisfies the requirement for a fixed length code that does not emulate.

The bit length determining unit 136a determines the bit length of the fixed length code from the number of symbols n, the unique word length N, and the parameters s and t so as to satisfy the following expression. f (M-1) < ^n≤f (M) However, f (M) = 2 ^Ms-1 -2 ^Mt-1 +2 ^Mst-2- ( ^Ms -t-N) * 2 ^MstN-3 ... (Equation 25) When M-s-1 <1, M-s-1 = 1
If M-t-1 <1, then M-t-1 = 1, and M
If -s-t-2 <1, then M-s-t-2, and M-s
When −t−N−3 <1, Ms−t−N−3 = 0.

The fixed-length code generation unit 136b generates a fixed-length code having the bit length M thus determined and satisfying the requirement for a fixed-length code that does not emulate a unique word. The requirements are as follows. (Condition 1 ') A code word consisting only of bit "0" is prohibited. (Condition 2 ') A code word in which the maximum continuous length of the bit "0" in the prefix of each code word is larger than s is prohibited. (Condition 3 ') A code word in which the maximum continuous length of bit "0" in the suffix of each code word is larger than t is prohibited. (Condition 4 ') s + t <N. (Condition 5 ') Codewords whose maximum continuous length of bit "0" is N or more in the middle of each codeword are prohibited.

The present embodiment is an example of a variable length code generation device in a signal transmission system in which both variable length codes and fixed length codes are used. Variable length codes are processed by the prefix processing unit 132 and the suffix processing unit 133. The generated fixed-length code is generated by the fixed-length code processing unit 136 so as to be a codeword other than those prohibited under the above conditions. In addition,
In fixed length codes, the use of additional bits is prohibited in order to keep the length of all code words constant.

The present embodiment can be easily applied to a plurality of types of variable length code transmission systems including fixed length codes, which is a more general usage pattern. In this type of signal transmission method using a plurality of code sets, parameters such as s, t, and N are determined by the transmission procedure of each code. As an example, FIG.
As shown in FIG. 5, in the transmission system of the plural types of variable-length codes involving the most general plural loops, the requirements for not causing emulation for each code set are (condition 1) to (condition 5), (condition 5) described above. 1 ') to (Condition 5'), s and t are replaced with s _i and t _i (constraint parameters for the i-th type code), respectively, and the following requirements are given. (Condition 6) s _{i + 1} + t _i <N (Condition 7) s ₁ + t _i <N

Variable length codes are generated in consideration of (Condition 1) to (Condition 7), and fixed length codes are (Condition 1 ') to (Condition 5') and (Condition 6) and (Condition 7). It is generated in consideration of and.

Each parameter is optimized in consideration of the overall coding efficiency. The length N of the unique word is determined according to the recognition ability of consecutive bits "0" of the hardware. The total average code length L _total is expressed as in the following Expression 26 using a function representing the average code length of each code.

(Equation 16) However, q _i represents the rate at which the code i appears in the entire code sequence.

The embodiments described above are merely illustrative of the present invention and are not restrictive, and the present invention can be implemented in various other modified modes and modified modes. Therefore, the scope of the present invention is defined only by the claims and their equivalents.

[0075]

As described in detail above, according to the present invention, a unique word creating means for creating a unique word consisting of consecutive bits "0" having a length N and a bit "0" in a prefix of a code word. Has a continuous length of s or less and a prefix processing means for creating each code word including at least one bit "1", and a continuous length of bit "0" in the suffix of each code word created by this prefix processing means. Is less than or equal to t, the continuous length of the bit “0” in each code word is less than N, and suffix processing means for correcting the bit pattern of each code word so that s + t <N is provided. , It is possible to systematically generate a variable length code that does not emulate a unique word with a specific pattern.

[Brief description of drawings]

FIG. 1 is a block diagram schematically showing the configuration of an embodiment of a variable length code generation device of the present invention.

FIG. 2 is a block diagram schematically showing a configuration example of a unique word creation unit in the embodiment of FIG.

FIG. 3 is a block diagram schematically showing a configuration example of a prefix processing unit in the embodiment of FIG.

FIG. 4 is a block diagram schematically showing a configuration example of a suffix processing unit in the embodiment of FIG.

5 is a diagram showing a tree structure of a Huffman code for each symbol shown in Table 1. FIG.

FIG. 6 is a diagram showing a tree structure of a variable length code subjected to prefix processing in each symbol shown in Table 1.

FIG. 7 is a diagram showing a tree structure of a variable-length code that does not emulate each symbol shown in Table 1;

FIG. 8 is a block diagram schematically showing the configuration of another embodiment of the variable length code generation device of the present invention.

9 is a block diagram schematically showing a configuration example of a parameter optimizing unit in the embodiment of FIG.

FIG. 10 is a characteristic diagram of an average code length with respect to a parameter s of a code that does not cause emulation.

FIG. 11 is a characteristic diagram of the number of additional bits with respect to a parameter s of a code that does not cause emulation.

FIG. 12 is a characteristic diagram of a minimum average code length with respect to the length N of a unique word and a parameter s which gives it.

FIG. 13 is a block diagram schematically showing the configuration of still another embodiment of the variable length code generation device of the present invention.

FIG. 14 is a block diagram schematically showing a configuration example of a fixed-length code processing unit in the embodiment of FIG.

FIG. 15 is a diagram schematically showing a transmission system of multiple types of variable length codes with multiple loops.

[Explanation of symbols]

 10, 80, 130 Input section 11, 81, 131 Unique word creation section 12, 82, 132 Prefix processing section 13, 83, 133 Suffix processing section 14, 84, 134 Output section 85, 135 Parameter optimization section 136 Fixed length code Processing unit

Claims (10)

[Claims] 1. A unique word creating means for creating a unique word consisting of consecutive bits "0" of length N (N is a plurality of natural numbers), and a consecutive length of bits "0" in a codeword prefix is s ( s is a natural number) or less,
The prefix processing means for creating each code word including at least one bit "1", and the continuous length of the bit "0" in the suffix of each code word created by the prefix processing means is t (t is a natural number) or less. Yes,
Suffix processing means for modifying the bit pattern of each code word so that the continuous length of the bit "0" in each code word is less than N and s + t <N. Long code generator. 2. The prefix processing means is means for generating a variable length code by introducing a dummy codeword consisting of only consecutive “s + 1” bits “0”. apparatus. 3. The prefix processing means generates the dummy codeword having the occurrence probability p _d , and the modified occurrence probability obtained by correcting each occurrence probability p _i of another symbol using the occurrence probability p _d. Outside 1] And a generated occurrence probability p _d and a modified occurrence probability 3. The apparatus according to claim 2, further comprising: prefix processing code generation means for determining bit patterns of all code words by using the variable length coding algorithm. 4. The suffix processing means measures the suffix state of each code word, and the consecutive length of the bit "0" in the suffix of the code word is t or less and N is consecutive in the code word. -1 means for outputting the codeword without the use of additional bits when there is no one bit "0". 4. The apparatus according to claim 1, further comprising: . 5. The suffix processing means is such that the consecutive length of bits "0" in the suffix of the code word is t or less and N-1 bits "0" are consecutive in the code word.
5. The apparatus of claim 4, further comprising means for inserting an additional bit of bit "1" after the N-1 bits "0", if any. 6. The suffix processing means further comprises means for inserting an additional bit of a bit “1” when the continuous length of the bit “0” in the suffix of the codeword exceeds t. The device according to claim 4 or 5. 7. The suffix processing means is means for performing parameter measurement and bit pattern correction processing on a tree expression, according to any one of claims 4 to 6.
The device according to item. 8. A parameter optimizing means for correcting the parameters s and t to optimum values for improving the coding efficiency is further provided.
The device according to item. 9. The parameter optimizing means measures the average code length of the variable length code output from the suffix processing means and the number of additional bits added by the suffix processing means, and the measured average. 9. Device according to claim 8, characterized in that it comprises means for modifying the parameters s and t according to the code length and the number of additional bits. 10. The run length of bit "0" in the prefix of the code word is s or less, the code word includes at least one bit "1", and the run length of bit "0" in the suffix of the code word. Is less than or equal to t, the length of consecutive bits "0" in the codeword is less than N, and means for generating a fixed-length code satisfying s + t <N is further provided. The apparatus according to any one of 1.