JPH09231794A - Semiconductor memory device and measuring circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently measure the redundancy with a tester in a semiconductor memory device having a redundancy function with input/output terminals to which multi bits are input/output in parallel and a measuring circuit. SOLUTION: The device includes a memory cell array part 10 which has memory cell areas 0 to 15 corresponding to input/output terminals I/O 0 to 15 to which multi bits are input/output in parallel, and divides the areas 0-15 to a plurality of area groups 9. Each area group 9 has extra memory cell blocks constituting a memory cell area, i.e., redundant cell replacement blocks 11, 12 to replace with failure bit parts in the groups 9. Moreover, each area group 9 is provided with a bit-compressing means which receives output data corresponding to outputs from areas in the same group, compresses the data to bits of a smaller count than that of the output data and outputs to input/output terminals I/O 0, 10, 4, 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a measuring circuit, and more particularly to a semiconductor memory device with a redundant function and an measuring circuit having input / output terminals for inputting and outputting in multi-bit parallel.

[0002]

2. Description of the Related Art Conventionally, in measuring a semiconductor memory device (hereinafter, referred to as a multi-bit device) having an input / output terminal for inputting / outputting a multi-bit in parallel of this kind, an input / output terminal of a multi-bit device and a measuring device (hereinafter A method of measuring a driver / comparator (called a tester) (hereinafter referred to as D / C) in a one-to-one correspondence and a method for collectively determining data of a plurality of input / output terminals of a multi-bit device by one input / output terminal There are two methods of using a test mode (hereinafter, referred to as a bit compression test mode).

First, a first measuring method in a conventional semiconductor memory device will be described. FIG. 7 is an explanatory diagram exemplifying a measuring circuit of a conventional semiconductor memory device, and shows a relationship between input / output terminals of a multi-bit device and D / C of a tester. Considering the case of a tester having 8 D / Cs per measurement block of a tester and having 4 measurement blocks of a tester, a multi-bit device having up to 8 input / output terminals, for example, an 8-bit I / C. 1 up to O device 14
One measurement block is assigned to one multi-bit device, and two measurement blocks from a 17-bit multi-bit device having 9 to 16 input / output terminals, for example, 16-bit I / O device 15, from 17 Measurement is performed by assigning four measurement blocks to a multi-bit device having 32 input / output terminals, for example, a 32-bit device 16.

Next, a second measuring method in the conventional semiconductor memory device will be described. FIG. 8 illustrates the internal configuration of a conventional semiconductor memory device, for example, a 16-bit input / output terminal device 15 which is a semiconductor memory device disclosed in Japanese Patent Laid-Open No. 4-307751 in a simplified manner in accordance with a chip layout. It is a partial block diagram. Referring to FIG. 8, the device 15 itself has the same configuration on the left and right sides, but the right side portion is omitted for convenience of illustration. However, in the following description, the block on the right side is also included.

The memory cell array portion 10 has a region 0, which is a memory cell region corresponding to each of the input / output terminals I / O0-15.
15 to 15, each of the areas 0 to 15 is connected to the data bus RWBS0 to 1 via the corresponding read amplifier DA0 to 15 and write amplifier WA0 to 15 respectively.
5 is connected. In addition, these data buses RWBS
0 to 15 are connected to the corresponding output control circuits DO0 to 15 and the data input circuits DI0 to 15, respectively. The outputs of the output control circuits DO0-15 are
Further, it is connected to the data output circuits DB0 to DB15, which are driving means of the input / output terminals I / O0 to 15, respectively, and drives the input / output terminals I / O0 to 15 to output data or Hi-Z.
Performs control to enter the state.

The data buses RWBS0 to 15 are data buses RWBS0 to 3, data buses RWBS4 to 7,
Data bus RWBS8-11, data bus RWBS12
15 to 15 are input to the corresponding data determination circuits TFF1 to TFF4, and the data determination circuits TFF1 to TFF1 to
The outputs of 4 are input to the corresponding data output control circuits DO0, 4, 8, and 12.

Further, the respective input / output terminals I / O0, 4, 8, 12 used in the bit compression test mode are compressed and not used in the bit compression test mode, and the other input / output terminals I / O1-3, 5 are not used. ~ 7,9 ~ 11,13 ~ 15 data input circuits DI1 ~ 3,5 ~ 7,9 ~ 1
1, 13 to 15 are also connected. Switching between the normal operation and the bit compression test mode is switched by the TEST signal 13. That is, the data determination circuits TFF1 to TFF4 controlled by the TEST signal 13, the data output control circuits DO0 to 15 and the data input circuit DI.
Bit compression means is composed of 0 to 15 and the data output circuits DB0 to DB15.

At the time of normal read, the cell data read from the areas 0 to 15 are amplified by the respective read amplifiers DA0 to DA15 corresponding to the areas 0 to 15, and are amplified via the data output control circuits DO0 to 15. Data output circuit D
This is transmitted to B0 to B15, and the data is output to each input / output terminal.

At the time of reading in the bit compression test mode, the outputs of the read amplifiers DA0 to DA15 output the data bus RWBS.
0-3, data bus RWBS4-7, data bus RWB
A combination of S8 to 11 and data buses RWBS12 to 15 is input to the data determination circuits TFF1 to TFF corresponding to each combination, and the respective data determination circuits TFF are input.
The outputs of 1 to 4 are input to the data output control circuits DO0, 4, 8, 12 corresponding to the input / output terminals I / O 0, 4, 8, 12 used in the bit compression test mode. The data determination circuits TFF1 to TFF4 output "high" data when the inputs are all the same data, and output "low" data when there is at least one different data.
The data output control circuits DO0 to 15 are input to the data buses RWBS0, 4, 8 and 8 when the data from the data determination circuits TFF1 to TFF4 are "high".
The data of 12 is transmitted to the data output circuits DB0 to 15, and when the output data of the data determination circuits TFF1 to 4 is'low ', a signal for stopping the operation of the data output circuits DB0 to 15 is generated and transmitted to the data output circuits DB0 to 15. .

Therefore, when the data input to the respective data decision circuits 2 are all equal, the data buses RWBS0, I / O0, 4, 8, 12 are connected to the data buses RWBS0,
The data from the output terminals 4, 8 and 12 are output. In other cases, the output from the input / output terminals I / O 0, 4, 8 and 12 is Hi-z.
Becomes

By the above operation, the multi-bit device 15
Is operating properly and all the data are equal, the expected value is output to the input / output terminals I / O0, 4, 8, 12 and even one of the data on the data bus RWBS0, 4, 8, 12 is different due to a malfunction. In that case, the input / output terminals I / O 0, 4,
The data of 8 and 12 are Hi-z, and the expected value is not output, so that the defect can be detected. Also, if all the data becomes the data opposite to the expected value due to a malfunction, the data is output to the input / output terminals I / O 0, 4, 8, 12, but the data is different from the expected value, so a defect is detected. it can.

At the time of normal write, each input / output terminal I / O0-
The data input from 15 is the data input circuits DI0 to 15 corresponding to the respective input / output terminals, the data bus RWBS0,
The data is transmitted to the write amplifiers WA0 to WA15 through 4, 8 and 12, and the write amplifiers WA0 to WA15 write the data to the areas 0 to 15 which are the memory cell areas.

At the time of writing in the bit compression test mode, I
The data of / O0, 4, 8, 12 is input to all the data input circuits DI0-15 connected to each, and the output of each data input circuit DI0-15 is the data bus RWBS.
The write amplifiers WA0 to WA15 corresponding to the respective write amplifiers WA0 to WA0 are input via 0, 4, 8, and 12, respectively.
15, the areas 0 to 15 which are the memory cell areas,
Data is written.

[0014]

In the conventional semiconductor memory device, when the above-mentioned first conventional measuring method is applied, it is necessary for each device under test as the number of input / output terminals of the device under test increases. Since the number of measurement blocks of various testers increases, the number of parallel measurements decreases and the measurement efficiency per tester decreases.

When the second measurement method described above is applied, the measurement efficiency per tester can be improved by using the bit compression test mode. However, as shown in FIG. 8, replacement with a redundant cell replacement block is performed. Area group 9
Area and each area 0 which is a memory cell area compressed by the bit compression means in the bit compression test mode.
Since the combination of 15 is different, the measurement for detecting the defective bit and replacing the memory cell block including the defective bit with the redundant memory cell block (hereinafter,
Redundancy measurement) is not possible using the bit compression test mode.

Furthermore, the redundancy measurement must use the first measurement method even in the case of a device equipped with the bit compression test mode or using a tester having a measurement function that performs a similar operation. The number of parallel measurements per tester is reduced because it has to be done.

Therefore, in order to solve at least one of these technical problems, the present invention, in a semiconductor memory device with a redundant function having each input / output terminal for inputting / outputting in a multi-bit parallel manner and a measuring circuit, measures a redundancy by a tester. The purpose is to improve efficiency.

[0018]

Therefore, the present invention has a memory cell area corresponding to each input / output terminal for inputting / outputting in multiple bits in parallel, and these memory cell areas are divided and arranged into a plurality of area groups. Having a memory cell array section,
In the semiconductor memory device having a redundancy function, each of the area groups has an extra memory cell block that constitutes the memory cell area, and a redundant cell replacement block that replaces a defective bit portion in each of the area groups, For each area group, input output data corresponding to the output from each memory cell area in the same area group, and bit compression to a bit number less than the bit number of the output data,
Each is provided with a bit compression means for outputting to the input / output terminal.

Further, the present invention has a memory cell array section having memory cell areas corresponding to the respective input / output terminals for inputting / outputting in multi-bits in parallel and dividing and arranging these memory cell areas into a plurality of area groups. , A semiconductor memory device having a redundant function in which each area group has an extra memory cell block forming the memory cell area and is a redundant cell replacement block for replacing a defective bit part in each area group. In the measurement circuit, output data from the input / output terminals corresponding to the memory cell areas in the same area group is input to each of the area groups, and bit compression is performed to a bit number smaller than the bit number of the output data. Then
Each is provided with a bit compression means for outputting to the measuring device.

[0020]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a partial block diagram showing a first embodiment of a semiconductor memory device of the present invention. Referring to FIG. 8, this semiconductor memory device is a 16-bit I / O device 15 like the conventional semiconductor memory device of FIG. 8, and although the device 15 itself has the same configuration on the left and right sides, For convenience, the right part is omitted. But,
In the following description, the block on the right side is also included.

The memory cell array section 10 is composed of areas 0 to 15 which are memory cell areas, and areas 0, 1, 8 ,.
9, area 10/11/2/3, area 4/5/12/1
It is divided and arranged in the area group 9 of four combinations of the areas 3, 15, 14, 6 and 7. When there is a defective bit portion in each area group 9, the redundant cell replacement blocks 11, 12, ... In the same area group are respectively replaced. The read amplifiers DA0 to DA1 corresponding to the areas 0 to 15 respectively.
5 and write amplifiers WA0 to 15 and are connected to the corresponding data buses RWBS0 to RWBS15. These data buses RWBS0-15 are connected to the corresponding output control circuits DO0-15 and data input circuits DI0-15. The outputs of the output control circuits DO0 to 15 are further input / output terminals I
/ O0-15 data output circuits DB0-DB0
15 are respectively connected to drive input / output terminals I / O0 to 15 to output data or control to Hi-Z state.

Further, the data buses RWBS0 to RWBS15 are input to the data judging circuits TFF1 to TFF4 in a combination corresponding to each area group 9, respectively, and each data judging circuit TFF1 is inputted.
The outputs of 4 to 4 are input to the corresponding data output control circuits DO0, 10, 4, and 14. Further, the input / output terminal I used in the bit compression test mode
/ O0, 10, 4, 14 are other input / output terminals I / O1, 8, 9, 11, ... Compressed in the bit compression test mode.
Data input circuits DI1, 8, 9, 11, 2, 3, 5, 12, corresponding to 2, 3, 5, 12, 13, 15, 6, 7
It is also connected to 13, 15, 6 and 7, respectively. Switching between normal operation and bit compression test mode is done by TEST
Switching by the signal 13. That is, this TEST signal 1
The data compression circuits TFF1 to TFF4, the data output control circuits DO0 to DO15, the data input circuits DI0 to 15 and the data output circuits DB0 to 15 controlled by 3 form bit compression means.

A normal read / write operation is exactly the same as that of the conventional semiconductor memory device shown in FIG.

At the time of reading in the bit compression test mode, the data output from the areas 0 to 15 are stored in the areas 0 to 15 respectively.
Are input to the read amplifiers DA0 to 15 corresponding to, and input to the data determination circuits TFF1 to TFF4 corresponding to the respective area groups 9 through the data buses RWBS0 to 15 in a combination for each area group 9 as described above. The subsequent operation is exactly the same as that of the conventional semiconductor memory device of FIG.

When writing in the bit compression test mode, the input / output terminal I / O used in the bit compression test mode
Input / output terminals I / O 1/8/9/11 that do not use the data of 0, 10, 4 and 14 in the bit compression test mode
・ Data input circuits DI1 ・ 8 ・ 9,11 ・ 2 ・ 3,5 ・ 1 connected to 2, 3, 5, 12, 13, 15, 6, and 7
Input also to 2, 13, 15, 6 and 7. The subsequent operation is exactly the same as usual, and the outputs of the respective data input circuits DI0 to 15 are input to the respective write amplifiers WA0 to WA0 to 15 via the data buses RWBS0 to 15 and the respective write amplifiers WA0 to WA1.
5, the same data is written in each of the areas 0 to 15 for each area group 9 having a combination equal to the combination of bit compression.

By the above operation, the read / write measurement can be performed for each area group 9 using the bit compression test mode.

FIG. 2 is a partial block diagram showing a second embodiment of the semiconductor memory device of the present invention. Referring to FIG.
This semiconductor memory device is a 16-bit I / O device 15 as in the semiconductor memory device of the first embodiment of FIG. 1, but this is an example in which the configuration of the region group 9 is different from that of the above-described embodiment. The device 15 itself has the same configuration on the left and right sides, but the right side portion is omitted for convenience of illustration.
However, in the following description, the block on the right side is also included.

The area group 9 is an area 0 which is a memory cell area.
* 8, area 1 * 9, area 2 * 10, area 3 * 11, area 4 * 12, area 5 * 13, area 6 * 14, area 7 * 15
The area group 9 is composed of 8 combinations. Therefore, in this embodiment, the input / output terminals used in the bit compression test mode are the input / output terminals I / O 0, 9, 2,
11, 4, 13, 6, and 15, which are operationally the same as in the first embodiment. Further, in the example given here, the number of region groups 9 is eight, and the number of regions included therein is two. However, the number of region groups 9 may change or the number of regions included therein may change. Even if the number changes, the same applies when the structure of the area group 9 is the unit of each area group as shown in FIG. However, because of the circuit configuration of the present invention, the number of input / output terminals used in the bit compression test mode is equal to the number of area groups 9, and therefore, when the number of area groups 9 changes, the number of area groups 9 is changed accordingly. The number of input / output terminals used in the bit compression test mode also changes.

FIG. 3 is a partial block diagram showing a third embodiment of the semiconductor memory device of the present invention. Referring to FIG.
This semiconductor memory device is a 16-bit I / O device 15 similarly to the semiconductor memory device of the second embodiment of FIG. 2, but this is an example of the case where the configuration of the region group 9 is different from that of the above-described embodiment, The description is omitted. The device 15 itself has the same configuration on the left and right sides, but the right side portion is omitted for convenience of illustration. However, in the following description, the block on the right side will be briefly described.

The area group 9 is an area 0 which is a memory cell area.
.1, area 2.3, area 4.5, area 6 and 7, area 8
9, area 10/11, area 12/13, area 14/15
The area group 9 is composed of 8 combinations. Therefore, in this embodiment, the input / output terminals 1 used in the bit compression test mode are I / O 0, 2, 4, 6, 8, 1
0, 12, and 14, which are operationally similar to those of the above-described embodiment.

FIG. 4 is a partial block diagram showing a fourth embodiment of the semiconductor memory device of the present invention. Referring to FIG.
This semiconductor memory device is a 16-bit I / O device 15 like the semiconductor memory device of the third embodiment of FIG. 3, but this is an example of the case where the configuration of the region group 9 is different from that of the above-described embodiment, The description is omitted. The device 15 itself has the same configuration on the left and right sides, but the right side portion is omitted for convenience of illustration. However, in the following description, the block on the right side will be briefly described.

The area group 9 is different on the row side and the column side, and the combinations of the areas 0 to 15 included in the row-side area groups 9 are the areas 0, 8, the areas 1 and 9, the areas 2 and 10, and the areas 2. Three
There are 8 combinations of 11, area 4/12, area 5/13, area 6/4, and area 7/15, and the combinations of areas 0 to 15 included in each area group 9 on the column side are areas. 0 ・ 1 ・ 8 ・ 9, area 2 ・ 3 ・ 10 ・ 11, area 4 ・
There are four combinations of 5/12/13 and areas 6/7/14/15. In other words, the two small area groups on the row side are included in one area group 9 on the column side. Areas 0 to 15 and data judgment circuits TFF1 to TFF4
The correspondence of is completely the same as that of the second embodiment, and the operation is completely the same as that of the second embodiment. Regarding replacement with the redundant cell replacement block 12 on the column side, each area group 9 on the column side is replaced.
The defective bits on the column side of the row-side region group 9 included therein are compared and replaced.

When the row and column region groups 9 have different configurations as described above, the circuit configuration of the present invention is applied in units of the smallest region group 9 to realize the same operation as that of the above-described embodiment. If the row-side or column-side area group 9 includes the other area group 9, the same applies to both cases.

FIG. 5 is a partial block diagram showing a fourth embodiment of the semiconductor memory device of the present invention. Referring to FIG.
This semiconductor memory device is a 16-bit I / O device 15 like the semiconductor memory device of the first embodiment of FIG. 1, but this is an example of the case where the configuration of the region group 9 is different from that of the above-described embodiment, The description is omitted. The device 15 itself has the same configuration on the left and right sides, but the right side portion is omitted for convenience of illustration. However, in the following description, the block on the right side will be briefly described.

The area group 9 is an area 0 which is a memory cell area.
・ 8 ・ 2 ・ 10, area 1 ・ 9 ・ 3 ・ 11, area 4 ・ 12
・ There are 4 combinations of 6/14, areas 5 ・ 13 ・ 7 ・ 15 and two small area groups with each area separated, and other circuit configurations and circuit operations are performed. This is exactly the same as the form 1. in this way,
The same is true when the memory cell regions 8 forming the region group 9 are arranged apart from each other.

FIG. 6 is a block diagram showing a measuring circuit of the present invention as a sixth embodiment. Referring to FIG. 6, the measurement circuit according to the present embodiment has a 16-bit I / O device 15,
The data determination circuits TFF1 to TFF4 and the drivers / comparators D / C to D / C are included.

The 16-bit I / O device 15 is a device under test, and has the same group of regions 9 as the semiconductor memory device of the first embodiment shown in FIG. That is, device 1
5 I / O terminals I / O 0, 1, 8, 9, I / O terminals I / O
O2 ・ 3 ・ 10 ・ 11, I / O terminal I / O4 ・ 5 ・ 12
13 and the area group 9 divided and arranged in the combinations of the areas 0 to 15 corresponding to the combination of the input / output terminals I / O 6, 7, 14, and 15. However, it is assumed that the semiconductor memory device of the first embodiment shown in FIG. 1 does not have the bit compression means, or has the bit compression means but does not use it.

The data determination circuits TFF1 to TFF4 are bit compression means corresponding to each area group of the device 15 of 16-bit I / O. At the time of reading, the data output to the input / output terminal I / O of the device 15 is input and
The same operation as the data determination circuits TFF1 to TFF4 in the first embodiment is performed, and the determination result is output to the D / C to in the measurement block of the measurement device connected to each. Also,
At the time of writing, the device 1 connected to the data input from the D / C to
5 to the input / output terminals I / O0-15.

Driver / comparator D / C ~
Is a driver / comparator in the measuring block of the measuring device. Although it is mounted on the pin electronics card in the measuring device, its detailed description is omitted here.

With the configuration of the measurement circuit of the present embodiment described above, even in a multi-bit device that does not have a built-in bit compression test mode, the measurement of the bit compression test mode can be realized outside the multi-bit device, and the bit compression test mode can be set. It can be used to perform redundancy measurements.

[0041]

As described above, the semiconductor memory device and the measuring circuit according to the present invention include a combination of memory cell areas for bit compression in the bit compression test mode.
The redundancy measurement using the bit compression test mode becomes possible by making the combination of the memory cell areas in the area group which is common to the redundant cells and which is to be replaced, equal.

Therefore, there is an effect that the redundancy measurement can be efficiently performed without reducing the number of parallel measurements available in the bit compression test mode.

[Brief description of drawings]

FIG. 1 is a partial block diagram showing a first embodiment of a semiconductor memory device of the present invention.

FIG. 2 is a partial block diagram showing a second embodiment of the semiconductor memory device of the present invention.

FIG. 3 is a partial block diagram showing a third embodiment of the semiconductor memory device of the present invention.

FIG. 4 is a partial block diagram showing a fourth embodiment of the semiconductor memory device of the present invention.

FIG. 5 is a partial block diagram showing a fifth embodiment of the semiconductor memory device of the present invention.

FIG. 6 is a block diagram showing a measurement circuit of the present invention as a sixth embodiment.

FIG. 7 is an explanatory diagram illustrating a measurement circuit of a conventional semiconductor memory device.

FIG. 8 is a partial block diagram showing an example of the internal configuration of a conventional semiconductor memory device.

[Explanation of symbols]

 9 area group 10 memory cell array section 11 row-side redundant cell replacement block 12 column-side redundant cell replacement block 13 TEST signal 14 8-bit I / O device 15 16-bit I / O device 16 32-bit I / O device 17 Tester measurement block 1 18 Tester measurement block 2 19 Tester measurement block 3 20 Tester measurement block 4 DA0-15 Read amplifier DB0-15 Data output circuit DI0-15 Data input circuit DO0-15 Data output control circuit I / O0-15 I / O terminals TFF1-4 data judgment circuit WA0-15 write amplifier area 0-15 memory cell area

Claims (2)

[Claims] 1. A memory cell array section having memory cell areas respectively corresponding to input / output terminals for inputting / outputting multi-bits in parallel, and dividing and arranging the memory cell areas into a plurality of area groups, each of the areas being provided. The group has an extra memory cell block forming the memory cell area,
In a semiconductor memory device having a redundancy function of a redundant cell replacement block that replaces a defective bit part in each area group, each area group corresponds to an output from each memory cell area in the same area group. The semiconductor memory device further comprises bit compression means for inputting the output data, performing bit compression to a bit number smaller than the bit number of the output data, and outputting the bit data to the input / output terminal. 2. A memory cell array section having memory cell areas respectively corresponding to input / output terminals for inputting / outputting multi-bits in parallel, and dividing and arranging the memory cell areas into a plurality of area groups, each of the areas being provided. The group has an extra memory cell block forming the memory cell area,
In a measuring circuit of a semiconductor memory device having a redundancy function, which is a redundant cell replacement block that replaces a defective bit part in each area group, each area group corresponds to each memory cell area in the same area group. The measuring circuit further comprises bit compression means for inputting the output data from the input / output terminal, compressing the data into a bit number smaller than the bit number of the output data, and outputting the bit data to a measuring device.