JPH09231573A - Optical information reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To much exactly perform the reproduction of optical recording object recording the edge position of an information pit in an optical recording medium as information and to increase the amounts of recorded information. SOLUTION: A RF signal digitized by a clock with the fourfold period of an information pit is inputted to a waveform equalizing circuit 11, removal of a bias fluctuation, gain fluctuation and interference between signals and the equalization of waveform are performed and the result is inputted to a decoder 12. Correct information is restored in the decoder 12 by utilizing the redundancy of the signal supplied from the waveform equalizing circuit 11 and reducing the influence of noise included in the input signal. The output of the decoder 12 calculates a target amount of reproducing signal in a target amplitude calculating circuit 14 and it is inputted to an error detecting circuit 15. The output of the waveform equalizing circuit 11 is also supplied to the error detecting circuit 15, the error between two signals is detected, the result is returned to the waveform equalizing circuit 11 and the frequency characteristic of the waveform equalizing circuit 11 is automatically optimized according to the input signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical information reproducing apparatus for reproducing an optical recording medium such as an optical disc.

[0002]

2. Description of the Related Art In a conventional optical disc reproducing apparatus,
A clock signal is reproduced from a reproduction signal of clock pits recorded in advance at a plurality of locations on the optical disc, and P
A technique of generating a sampling clock signal synchronized with the clock signal using LL (Phase Locked Loop) or the like, sampling an analog reproduction signal reproduced from the optical disc at a timing at which the sampling clock changes, and converting the analog reproduction signal into a digital signal. Is often used.

For example, the applicant of the present invention has disclosed in Japanese Unexamined Patent Publication No. 6-76303.
In an information recording medium in which the information recorded in each pit is reproduced by an optical detection system that obtains a reproduction signal according to the pit by scanning with a light beam along the pit row, the transmission of the reproduction optical detection system The edge position of the information pit is stepwise shifted from a predetermined reference position within a range corresponding to a predetermined period shorter than the transient period of the reproduction signal determined according to the characteristic, in accordance with the digital information to be recorded. An information recording medium characterized by the above and an information reproducing apparatus for reproducing recorded information from the recording medium are proposed.

Further, the applicant of the present invention has also filed Japanese Unexamined Patent Publication No. 6-76.
In No. 303, the recording medium in which the reference pit indicating the reference position is recorded, and a clock that is phase-synchronized with the reference position based on the reproduction signal of the reference pit are reproduced, and further defined by the clock. There has been proposed the information reproducing apparatus for A / D converting the reproduced signal from the information recording medium at a certain sample timing.

Further, the present applicant has filed Japanese Patent Application No. 6-177894.
No. 3, No. 6, pp. 187-242, proposes means for automatically adjusting the sample timing. FIG. 7 shows Japanese Patent Application No. 6-177894.
1 shows an example of a basic format when the number is used for an optical disc.

As shown in FIG. 7 (a), pits are arranged on the disc at a constant period P, and all recorded information has a front end (front edge) position and a rear end (rear edge) of these pits. It is recorded as a shift amount in eight steps of position. The unit shift amount which is one unit of this shift amount is Δ
L, and the pit length is from the minimum value Lmin to the maximum value Lma
Change to x. The period P in which the pits are arranged on the disc is set so that the reciprocal 1 / P thereof coincides with 1/2 of the cutoff spatial frequency Fc in the transfer characteristic of the reproducing optical system.

FIG. 8 is a diagram showing an example of a pit array recorded on the disc. FIG. 8A shows the same as FIG. 7A.
The possible shapes of the pit are shown. Also, FIG.
The pit on the left side of is the maximum pit of length Lmax, and the information of stage 7 is recorded at the front end and the rear end thereof.
The pit on the right side is the smallest pit with a length of Lmin,
Information of stage 0 is recorded at the front end and the rear end thereof. FIG. 7C is another example, in which the information of stage 2 is recorded at the front end of the left pit, the information of stage 6 is recorded at the rear end, and the information of stage 5 is recorded at the front end of the right pit. The information shows the state in which the information of step 4 is recorded at the rear end. The pitch of the pit array is the constant value P as described above. In this example, the front and rear edges of the pit are each 8
Since the information corresponding to the stage is recorded, it is possible to record 8 × 8 = 64 types of information in one pit.

Further, the above-mentioned disk has a Japanese Patent Application No. 6-17.
It goes without saying that a pattern for adjusting the phase of the sample clock proposed in No. 7894 is recorded.

Next, an example of a reproducing apparatus for reproducing recorded information from the above-mentioned optical disc is shown in FIG. 9 and will be described. In this example, a so-called three-beam type optical pickup is used, but another type of optical pickup may be used.

The optical pickup 1 is of the three-beam type as described above, and irradiates the disk 2b with three light beams. The relative positions of the three beams are such that when the central main beam is located directly above the read track, the sub-beams on both sides irradiate positions offset by 1/4 track from the center of the read track. It is set. Then, the optical pickup 1 converts the reflected lights of the two sub-beams into electric signals and subtracts them from each other to generate a tracking error signal and outputs it to the tracking servo circuit 3. Further, the optical pickup 1 converts the reflected light of the central main beam into an electric signal to generate a reproduction signal (hereinafter, simply referred to as “RF reproduction signal”), and the focus servo circuit 4, the spindle servo circuit 5, the clock reproduction circuit. 7 and the A / D conversion circuit 8.

The tracking servo circuit 3 follows the tracking error signal supplied from the optical pickup 1 so that the main beam of the optical pickup 1 correctly traces the track of the optical disc 2b.
Control the position of.

The focus servo circuit 4 follows the focus error signal extracted from the RF reproduction signal supplied from the optical pickup 1 so as to keep the distance between the optical pickup 1 and the disc 2b correct.
Control the position of. Further, the spindle servo circuit 5 extracts the rotation synchronization signal included in the RF reproduction signal supplied from the optical pickup 1 and controls the rotation speed of the spindle motor 6 so that the rotation speed of the optical disc 2b becomes a predetermined value. .

The clock regenerating circuit 7 includes an optical pickup 1
From the RF reproduction signal supplied from the optical disc 2b
The reproduced portion of the reference pit which is periodically recorded above is extracted, and a reproduced clock synchronized with this is generated by the PLL circuit. The frequency of the generated reproduction clock is set to be twice the repetition frequency of the pits. The reproduced clock is output to the digital signal processing circuit 9 and the pulse phase adjusting circuit 10.

On the other hand, the A / D conversion circuit 8 samples the RF reproduction signal supplied from the optical pickup 1 at the timing when the sample pulse supplied from the pulse phase adjustment circuit 10 changes, and converts it into a digital signal. The converted digital signal is output to the digital signal processing circuit 9 and the pulse phase adjusting circuit 10.

The pulse phase adjustment circuit 10 extracts a reproduction portion of a fixed pattern for pulse phase adjustment contained in the digital signal supplied from the A / D conversion circuit 8,
In accordance with this, the sample clock is generated by adjusting the phase of the reproduction clock supplied from the clock reproduction circuit 7 and supplied to the A / D conversion circuit 8.

FIGS. 7A and 7B are timing charts of two input signals supplied to the A / D conversion circuit 8. FIG. 2B shows an RF reproduction signal when the pit train shown in FIG. 1A recorded on the disc is reproduced, and FIG. 3C shows the RF reproduction signal supplied from the pulse phase adjusting circuit. Shows the sample clock. As described above, the A / D conversion circuit 8 samples the RF signal of FIG. 7B at the timing of the change point (rising edge) of the sample clock shown in FIG. 7C and converts it into a digital signal. To do.

When the front end position and the rear end position of the pit are changed in eight ways as shown in FIG. 7A corresponding to the information to be recorded, the RF reproduction signal which is a reproduction signal thereof is also shown in FIG. 7B. 8), the portions corresponding to the front end portion and the rear end portion of the pit change in eight ways. When these changed portions are sampled by the A / D conversion circuit 8, the levels of L0 to L7 corresponding to the recorded information can be detected. Therefore, it is desirable that the sampling timing of the RF reproduction signal in the A / D conversion circuit 8 be the central portion when the RF reproduction signal changes in eight ways as shown in FIG. 7C. Therefore, in this example, the pulse phase adjusting circuit 10 is provided to constantly adjust the phase of the sample clock so that the RF reproduction signal can always be sampled at the optimum timing.

The digital signal output from the A / D conversion circuit 8 as described above is supplied to the digital signal processing circuit 9. The digital signal processing circuit 9 processes the supplied digital signal to restore the recorded information.

The cut-off frequency fc in the transfer characteristic of the information reproducing apparatus is determined as follows by the optical resolution Fc of the information reproducing apparatus and the relative speed v. fc = v × Fc On the other hand, when the relative speed between the information recording medium and the information reproducing apparatus or its optical detection system is v, the pit repetition frequency fp in the RF reproduction signal is fp = v / P. P is the period of the pits on the disc, and is set as 1 / P = Fc / 2. Therefore, the repetition frequency fp of the pits is expressed as follows. fp = v × Fc / 2 Further, since the sampling frequency fs at which the RF reproduction signal is sampled by the A / D conversion circuit is twice fp, fs = v × Fc, which is the transfer characteristic of the information reproducing apparatus. Corresponds to the cutoff frequency fc at. Therefore, according to the sampling theorem, only the frequency band up to half the cutoff frequency fc can be reproduced from the signal sampled by the A / D conversion circuit.

Due to such a problem, in the conventional information reproducing apparatus, it is difficult to correctly restore the recorded information unless the RF reproduced signal is always sampled at the correct timing.

Therefore, in the conventional information reproducing apparatus, the RF reproduction signal can be sampled at correct timing.
Since it is necessary to provide a means for adjusting the phase of the sample clock, the circuit configuration of the information reproducing apparatus is complicated.

Further, since the reference pattern for adjusting the phase of the sample clock had to be recorded on the information recording medium in advance, the recording capacity of the information recording medium was reduced accordingly.

[0023]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and eliminates the need for adjusting the phase of the sample clock, thereby increasing the density of the information recording medium and the information reproducing apparatus. This is intended to simplify the configuration.

[0024]

According to the present invention, a clock signal is reproduced from a reproduction signal having a predetermined recording pattern formed in advance at a plurality of positions on an optical recording medium, and the clock signal is reproduced at each change point of the clock signal. A / which samples the analog reproduction signal of the optical recording medium and converts it into a digital signal
In an optical information reproducing apparatus equipped with a D converting means, the frequency of the clock signal is set to be at least twice the cutoff frequency determined by the transfer characteristics of the reproducing optical system and the relative speed between the optical recording medium and the reproducing optical system. .

Further, waveform equalizing means for performing waveform equalization on the digital signal output from the A / D converting means, and decoding means for restoring recorded information based on the output signal of the waveform equalizing means, And a transfer characteristic adjusting unit for automatically adjusting the transfer characteristic of the waveform equalizing unit based on the decoding result output by the decoding unit.

By optimally adjusting the transfer characteristic of the waveform equalizing means using the transfer characteristic adjusting means, the signal when the phase of the sample clock is optimally adjusted is simulated by the waveform equalizing means. To solve the above problems.

Further, since the decoding means adopts the maximum likelihood decoding method using the redundancy of the recorded information, the reliability of the decoding result by the decoding means is improved, so that the transfer characteristic of the waveform equalizing means is improved. Can be adjusted more correctly.

Further, there is provided error correction means for correcting a decoding error included in the decoding result output by the decoding circuit using an error correction code included in the record information, and based on an output signal of the error correction means. By adjusting the transfer characteristic of the waveform equalizer, the transfer characteristic of the waveform equalizer can be adjusted more correctly.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the present invention.
This will be described with reference to FIG. This example is an example in which the present invention is applied to the information reproducing apparatus described in JP-A-6-76303 previously proposed by the present applicant.

FIG. 1 is a block diagram showing the overall structure of the optical information reproducing apparatus according to the present invention. Disc 2a is Japanese Patent Laid-Open No.
No. 76303, the information recording medium is different from the conventional example in that information is recorded by shifting the positions of the front end and the rear end of pits periodically arranged on the disc in eight steps. Is the same. But the disc 2a
In No. 6, the pattern for adjusting the phase of the sample clock, which was previously proposed by the present applicant in Japanese Patent Application No. 6-177894, is not recorded.

The optical pickup 1 is similar to that of the conventional example, irradiates the optical disk 2a with three light beams, and outputs an RF reproduction signal and a tracking error signal from the reflected light.

The tracking error signal output from the optical pickup 1 is supplied to the tracking servo circuit 3. The tracking servo circuit 3 uses the tracking error signal so that the main beam of the optical pickup 1 correctly traces on the track of the optical disc 2a.
The position of the optical pickup 1 is controlled. Further, the focus servo circuit 4 receives the RF supplied from the optical pickup 1.
The focus error signal is extracted from the reproduction signal, and the position of the optical pickup 1 is controlled so that the distance between the optical pickup 1 and the optical disk 2a is kept correct.

Further, the spindle servo circuit 5 extracts a rotation synchronizing signal from the RF reproduction signal supplied from the optical pickup 1 so that the spindle motor 6 can rotate so that the rotation speed of the optical disk 2a becomes a predetermined value. Control the number of rotations.

The RF reproduction signal output from the optical pickup 1 is also supplied to the clock reproduction circuit 7. The clock reproducing circuit 7 extracts the reproduced portion of the reference pit that is periodically recorded from the RF reproduced signal supplied from the optical pickup 1 and generates a reproduced clock in synchronization with the extracted portion. The frequency of the generated reproduction clock is set to be four times the repetition frequency of the pits. The generated reproduction clock is A /
It is output to the D conversion circuit 8 and the digital signal processing circuit 9.

On the other hand, the RF reproduction signal output from the optical pickup 1 is supplied to the A / D conversion circuit 8. FIG.
Shows two input signals and one output signal supplied to the A / D conversion circuit 8, and with reference to this, the A / D
The operation of the conversion circuit 8 will be described. 5A shows a pit string recorded on the optical disc 2a, and FIG. 5B shows an RF reproduction signal when the pits in FIG. 5A are reproduced. Further, FIG. 7C shows a reproduction clock supplied from the clock reproduction circuit 7, and its frequency is four times the repetition frequency of the pits.

The A / D conversion circuit 8 samples the RF reproduction signal shown in FIG. 5B at the rising edge timing of the reproduction clock shown in FIG. 5C, and the digital signal shown in FIG. Convert to. The frequency of the reproduction clock is four times the repetition frequency of the pit, and the repetition frequency of the pit is 1 / the cutoff frequency fc determined by the transfer characteristics of the optical pickup 1 and the relative speed between the optical disc 2a and the optical pickup 1. Since it is 2, the frequency of the reproduction clock is twice the cutoff frequency fc.

Therefore, by subjecting the signal sampled by the A / D conversion circuit 8 to appropriate signal processing, a desired RF reproduction signal can be obtained within the frequency band up to the cutoff frequency fc regardless of the phase of the sampling clock. It is clear from the sampling theorem that can be reproduced.

The RF reproduction signal sampled by the A / D conversion circuit 8 is output to the digital signal processing circuit 9. In the digital signal processing circuit 9, the A / D conversion circuit 8
By performing digital signal processing on the digital signal supplied from, the A / D conversion circuit 8 generates a signal sampled at the optimum timing, and by decoding this signal, it is recorded on the optical disc 2a. The recorded information is reproduced and output.

Next, an example of the digital signal processing circuit 9 is shown in the block diagram of FIG. 2 and will be described. The digital signal processing circuit 9 operates in synchronization with the reproduction clock supplied from the clock reproduction circuit 7, but is not shown in the figure.

The digitized RF signal output from the A / D conversion circuit 8 is supplied to the waveform equalization circuit 11. The waveform equalization circuit 11 performs filtering on the supplied digital RF signal by a method described below to generate and output a signal similar to the digital RF signal when sampled at the optimum timing. Further, since the waveform equalization circuit 11 performs waveform equalization on the supplied digital RF signal, it also removes intersymbol interference, which is an influence of pits recorded before and after, and outputs it. The digital signal generated by the waveform equalization circuit 11 is output to the decoder (decoding circuit) 12.

The decoder 12 decodes the record information from the digital signal supplied from the waveform equalization circuit 11, and performs error correction in an error correction circuit (not shown) provided in the subsequent stage. The error correction circuit corrects the decoding error in the signal decoded by the decoder 12 by the error correction code added to the recording signal in advance, and outputs the result.

On the other hand, the output signal of the decoder 12 is also supplied to the target amplitude calculation circuit 14. Target amplitude calculation circuit 1
In 4, the target reproduction signal is reproduced by a method described later according to the decoding result supplied from the decoder 12, and the result is output to the error detection circuit 15.

On the other hand, the error detection circuit 15 is also supplied with the digital signal output from the waveform equalization circuit 11, and the error detection circuit 15 takes the difference between these two input signals and uses this as an error signal for waveform equalization. Return to circuit 11.

In the waveform equalizing circuit 11, the error detecting circuit 15
The transfer characteristic of the waveform equalizing circuit 11 is sequentially changed by a method described later based on the error signal supplied from Therefore, even if the transfer characteristic of the reproduction optical system changes or the phase relationship between the reproduction clock and the RF reproduction signal changes due to, for example, the optical disc 2a tilting with respect to the optical pickup 1, the waveform equalization circuit 11 automatically operates. It is possible to correct this, and always obtain a good digitized RF signal.

Further, even if the amplitude or bias amount of the RF reproduction signal changes due to unevenness of the reflection film of the optical disc 2a, the transfer characteristic of the waveform equalizing circuit 11 automatically changes in the same manner as in the above case. So always good digitized RF
A signal can be obtained.

Next, the structure of the waveform equivalent circuit 11 will be described with reference to FIG. The digitized RF signal output from the A / D conversion circuit 8 is first supplied to the delay circuit 16 and delayed by one clock of the reproduction clock supplied from the clock reproduction circuit 7. Similarly, the output of the delay circuit 16 is sequentially input to the delay circuits 17 to 19 and delayed by one clock. The output terminal of the A / D conversion circuit 8 is tap 1 and the output terminals of the delay circuits 17 to 19 are taps 2 to 5.
Then, the output signal of the tap 1 is appropriately amplified or attenuated by the variable amplification circuit 20 and output to the addition circuit 26. Similarly, the output signals of the taps 2 to 5 are appropriately amplified or attenuated by the variable amplification circuits 21 to 24 and output to the addition circuit 26.

Delay circuits 16-19, variable amplifier circuit 20-
24 and the addition circuit 26 are 5-tap FIR (Fini)
te Impulse Response) filter is formed. The digitized RF signal supplied from the A / D conversion circuit 8 is appropriately waveform-equalized by this FIR filter and output to the edge data extraction circuit 27. At this time, the amplification factors of the variable amplification circuits 20 to 24 are adjusted at any time by the amplification factor adjustment circuit 25, whereby the transfer characteristics of the FIR filter are automatically adjusted so as to be appropriately and optimally corresponding to the input signal. Adjusted to.

The edge data extraction circuit 27 extracts a portion corresponding to the edge of the pit from the signal supplied from the addition circuit 26 and outputs it to the decoder 12 and the error detection circuit 15.

Next, the operation of the target amplitude calculation circuit 14 will be described. The target amplitude calculation circuit 14 calculates an ideal reproduction signal level according to the signal supplied from the decoder 12 and outputs it. Assuming that the larger the information recorded at the edge of the pit (the closer to “7” in the example shown in FIG. 7), the higher the voltage level of the reproduction signal, the signal i (0 ≦ i ≦ 7) from the decoder 12 is output. When supplied, the target amplitude calculation circuit 14 calculates the target amplitude Oi according to the equation (1). Oi = A × i + B (1) In the equation (1), A and B are arbitrarily determined constants.

Next, the operation of the error detection circuit 15 will be described. In the error detection circuit 15, the ideal reproduction signal obtained from the decoding result of the reproduction signal, that is, the target amplitude calculation circuit 1
The target reproduction signal calculated in accordance with equation (1) in step 4,
An error signal which is a difference from an actual reproduction signal, that is, a signal supplied from the waveform equalization circuit 11 is calculated and output to the waveform equalization circuit 11. The error signal is calculated by calculating the error between the ideal reproduction signal and the signal output from the waveform equalization circuit 11. The waveform equalization circuit 11 automatically adjusts the transfer characteristic of the waveform equalization circuit 11 using the waveform of this error signal.

Next, referring to FIG. 4, the waveform equalizing circuit 11
A method of adjusting the transfer characteristic in step 1 will be described. The waveform equalizing circuit 11 described above constitutes a 5-tap FIR filter, and its transfer characteristic is adjusted by adjusting the amplification factors of the signals output from the taps 1 to 5, respectively. The signals output from the taps 1 to 5 are adjusted by the variable amplification circuits 20 to 24, respectively, and the amplification factors of these variable amplifiers are adjusted by the amplification factor adjustment circuit 25.

The amplification factor adjusting circuit 25 includes delay circuits 28-3.
2, and the correlation detection circuits 33 to 37, each of which is composed of one delay circuit and one correlation detection circuit.
There are two block configurations, and each block adjusts the amplification factor of the corresponding variable amplifier circuit.

First, tap 3 which is the center of taps 1-5
A method of adjusting the amplitude of the signal output by the variable amplifier circuit 22 will be described. The output terminal of the delay circuit 17, that is, the signal output from the tap 3 is the delay circuit 3
After being delayed for a predetermined time at 0, it is supplied to the correlation detection circuit 35. The delay amount of the signal in the delay circuit 30 is calculated from the output terminal of the delay circuit 17, the variable amplification circuit 22, the addition circuit 26, the edge data extraction circuit 27, and the decoder 1.
2. It is set to be equal to the total delay amount in the path from the target amplitude calculation circuit 14 and the error detection circuit 15 to the correlation detection circuit 35. Due to this delay, the phases of the two signals supplied to the correlation detection circuit 35 are matched.

The correlation detection circuit 35 calculates the correlation between the two signals supplied to this circuit, that is, the signal supplied from the delay circuit 30 and the error signal supplied from the error detection circuit 15. As described above, the error signal is the waveform equivalent circuit 1
Since the error of the output signal of 1 with respect to the target amplitude is represented, the correlation detection circuit 35 calculates the correlation between these two input signals and outputs from the tap 3 included in the error signal. It means that the magnitude of the signal component is calculated.

The correlation detection circuit 35 can be realized by a multiplier, for example. If a positive signal is output to the variable amplifier circuit 22 as a result of multiplying the two signals supplied to the correlation detection circuit 35, the variable amplifier circuit 22 reduces the amplification factor of the signal supplied from the tap 3 to a small value. Reduce to. As a result, the amplification factor in the variable amplification circuit 22 may become negative, but in this case, the variable amplification circuit 22 operates as an inverting amplification circuit. Conversely, when a negative output signal from the correlation detection circuit 35 is supplied to the variable amplification circuit 22, the variable amplification circuit 22 slightly increases the amplification factor of the signal supplied from the tap 3. With the above operation, the amplification factor of the variable amplification circuit 22 is controlled by the delay circuit 30 and the correlation detection circuit 35.

Next, a method of adjusting the amplitude of the signal output from the tap 1 in the variable amplifier circuit 20 will be described. The amplification factor of the variable amplification circuit 20 is controlled by the delay circuit 28 and the correlation detection circuit 33 in the same manner as described above. The tap 1, that is, the output signal of the A / D conversion circuit 8 is delayed by a delay circuit 28 for a predetermined time and output to the correlation detection circuit 33. This delay circuit 28
The delay time is set to be equal to the delay amount in the delay circuit 30 described above. On the other hand, the correlation detection circuit 33 is supplied with an error signal in addition to the output signal of the delay circuit 28, calculates the correlation between the two supplied signals, and outputs the result to the variable amplification circuit 20. In the variable amplification circuit 20, when the output of the correlation detection circuit 33 is positive, the amplification factor is slightly reduced, while when it is negative, the amplification factor is slightly increased to control the amplification factor of the variable amplification circuit 20.

Next, a method of adjusting the amplitude of the signal output from the tap 2 in the variable amplification circuit 21 will be described. The amplification factor of the variable amplification circuit 21 is controlled by the delay circuit 29 and the correlation detection circuit 34 in the same manner as described above. The tap 2, that is, the output signal of the delay circuit 16 is delayed by the delay circuit 29 for a predetermined time and output to the correlation detection circuit 34. The delay time in the delay circuit 29 is set equal to the delay amount in the delay circuit 30 described above. On the other hand, the correlation detection circuit 34 is supplied with an error signal in addition to the output signal of the delay circuit 29, calculates the correlation between the two supplied signals, and outputs the result to the variable amplification circuit 21. In the variable amplification circuit 21, when the output of the correlation detection circuit 34 is positive, its amplification factor is slightly reduced,
On the other hand, when it is negative, the amplification factor of the variable amplification circuit 21 is controlled by slightly increasing the amplification factor.

Next, a method of adjusting the amplitude of the signal output from the tap 4 in the variable amplification circuit 23 will be described. The amplification factor of the variable amplification circuit 23 is controlled by the delay circuit 31 and the correlation detection circuit 36 in the same manner as described above. The tap 4, that is, the output signal of the delay circuit 18 is delayed by the delay circuit 31 for a predetermined time and output to the correlation detection circuit 36. The delay time in the delay circuit 31 is set equal to the delay amount in the delay circuit 30 described above. On the other hand, the correlation detection circuit 36 is supplied with an error signal in addition to the output signal of the delay circuit 31, calculates the correlation between the two supplied signals, and outputs the result to the variable amplification circuit 23. In the variable amplification circuit 23, when the output of the correlation detection circuit 36 is positive, its amplification factor is slightly reduced,
On the other hand, when it is negative, the amplification factor of the variable amplification circuit 23 is controlled by slightly increasing the amplification factor.

Next, a method of adjusting the amplitude of the signal output from the tap 5 in the variable amplification circuit 24 will be described. The amplification factor of the variable amplification circuit 24 is controlled by the delay circuit 32 and the correlation detection circuit 37 in the same manner as described above. The tap 5, that is, the output signal of the delay circuit 19 is delayed by the delay circuit 32 for a predetermined time and output to the correlation detection circuit 37. The delay time in the delay circuit 32 is set equal to the delay amount in the delay circuit 30 described above. On the other hand, the correlation detection circuit 37 is supplied with an error signal in addition to the output signal of the delay circuit 32, calculates the correlation between the two supplied signals, and outputs the result to the variable amplification circuit 24. In the variable amplification circuit 24, when the output of the correlation detection circuit 37 is positive, the amplification factor is slightly reduced,
On the other hand, when it is negative, the amplification factor of the variable amplification circuit 24 is controlled by slightly increasing the amplification factor.

As described above, the amplification factor adjusting circuit 25
By controlling the amplification factors in the variable amplification circuits 20 to 24, the transfer characteristic of the waveform equalization circuit 11 is automatically adjusted to the optimum state according to the input signal. As a result, the waveform equalization circuit 11 always outputs a signal when the RF reproduction signal is sampled at the optimum timing.

By making the decoder 12 in the above-mentioned example a maximum likelihood decoding method using the redundancy of the recorded information, a more reliable decoding result is supplied to the target amplitude calculation circuit 14, The exact target amplitude is supplied to the error detection circuit. As a result, since a more accurate error signal is supplied from the error detection circuit to the waveform equalization circuit 11, the transfer characteristic in the waveform equalization circuit 11 can be adjusted more correctly.

Further, in the above example, the output signal of the decoder 12 is supplied to the target amplitude calculation circuit 14 to calculate the target amplitude. However, as shown in FIG. 6, the signal output from the error correction circuit 13 is By supplying the target amplitude calculation circuit 14 and calculating the target amplitude on the basis of this, the reliability of the signal supplied to the target amplitude calculation circuit 14 is improved, so a more accurate target amplitude is calculated. be able to. In that case, although the circuit configuration becomes more complicated, a more accurate error signal is calculated based on a more accurate target amplitude,
Since it is supplied to the waveform equalization circuit 11, the waveform equalization circuit 11
The transfer characteristic in can be adjusted more correctly.

[0063]

According to the present invention, the cut-off frequency of 2 determined by the transfer characteristic of the reproducing optical system and the number of revolutions of the optical disk.
Even if the sampling timing is not accurately adjusted by sampling the RF reproduction signal at a sampling frequency that is twice or more, by performing signal processing on the digital signal obtained by sampling, A digital signal equivalent to that when the timing is adjusted can be generated.

In order to control the timing when sampling the RF reproduction signal, it is not necessary to record the reference data, which has been conventionally required, in the recording medium, and the capacity of the recorded information can be increased.

Sampling is performed by performing signal processing by a waveform equalization circuit on an RF reproduction signal sampled at a sampling frequency that is at least twice the cutoff frequency determined by the transfer characteristics of the reproduction optical system and the number of revolutions of the optical disk. A digital signal equivalent to the case of adjusting the timing of the pulse to be generated can be generated, and at the same time, intersymbol interference, which is an influence from pits recorded before and after, and fluctuations of the amplitude and bias component of the reproduced signal are removed Therefore, the circuit configuration can be simplified as compared with the case where a circuit adapted to each purpose is individually provided.

By performing maximum likelihood decoding on the data by utilizing the redundancy of the recording signal, the reliability of the decoded data is improved, so that the transfer characteristic of the waveform equalizing means can be adjusted more correctly.

The decoding error existing in the data decoded in the information reproducing apparatus is corrected based on the error correction code previously inserted in the recording signal, and the transfer characteristic of the waveform equalizing means is adjusted using the result. As a result, the transfer characteristic of the waveform equalizer can be adjusted more accurately.

[Brief description of drawings]

FIG. 1 is a block diagram of an optical information reproducing device according to the present invention.

2 is a first embodiment of the digital signal processing circuit shown in the block diagram of FIG.

FIG. 3 is a block diagram showing a specific configuration of the waveform equalization circuit shown in FIG.

FIG. 4 is a diagram for explaining the amplification factor adjusting circuit shown in FIG. 3 in more detail.

FIG. 5 is a diagram for explaining reproduction of recorded information in the optical information reproducing device according to the present invention.

6 is a second embodiment of the digital signal processing circuit shown in the block diagram of FIG.

FIG. 7 is a diagram for explaining a pit string formed on an optical information recording medium.

FIG. 8 is a diagram for explaining a pit string formed on an optical information recording medium, similar to FIG.

FIG. 9 is a block diagram of a conventional optical information reproducing device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Optical pickup, 2a, 2b ... Optical disk, 3 ... Tracking servo circuit 4 ... Focus servo circuit, 5 ... Sinddle servo circuit, 6 ... Spindle motor 7 ... Clock reproduction circuit, 8 ... A / D conversion circuit 9, 9a, 9b ... Digital signal processing circuit, 10 ... Pulse phase adjustment circuit 11 ... Waveform equalization circuit, 12 ... Decoder, 13 ... Error correction circuit 14 ... Target amplitude calculation circuit, 15 ... Error detection circuit 16, 17, 18, 19 ... Delay Circuit, 20, 21,
2, 23, 24 ... Variable amplification circuit 25 ... Amplification factor adjustment circuit, 26 ... Addition circuit, 27 ... Edge data extraction circuit, 28, 29, 30, 31, 32 ... Delay circuit, 33, 34, 35, 36, 37 ... Correlation detection circuit

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[Procedure amendment]

[Submission date] November 28, 1996

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0026

[Correction method] Change

[Correction contents]

[0026] By optimally adjusting the transfer characteristic of the waveform equalization means using said transfer characteristic adjusting means, a signal at the time of optimally adjusting a phase of the sample clock, raw Te said waveform equalizing means smell And solve the above problems.

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0040

[Correction method] Change

[Correction contents]

The digitized RF signal output from the A / D conversion circuit 8 is supplied to the waveform equalization circuit 11. Waveform equalizing circuit 11, by performing the filtering in a manner described below with respect to the digital RF signal to be supplied, and outputs the digital RF signal when sampled at the optimum timing raw form by. Further, the waveform equalization circuit 11
Performs waveform equalization on the supplied digital RF signal, so that intersymbol interference, which is an influence from pits recorded before and after, is also removed and output. Waveform equalization circuit 1
The digital signal generated in 1 is a decoder (decoding circuit)
12 is output.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0042

[Correction method] Change

[Correction contents]

On the other hand, the output signal of the decoder 12 is also supplied to the target amplitude calculation circuit 14. Target amplitude calculation circuit 1
In 4, the target reproduction signal is generated by the method described later according to the decoding result supplied from the decoder 12, and the result is output to the error detection circuit 15.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0047

[Correction method] Change

[Correction contents]

Delay circuits 16-19, variable amplifier circuit 20-
24 and adder circuit 26 of the 5-tap FIR (Fini
te Impulse Response) filter is formed. The digitized RF signal supplied from the A / D conversion circuit 8 is appropriately waveform-equalized by this FIR filter and output to the edge data extraction circuit 27. At this time, the amplification factors of the variable amplification circuits 20 to 24 are adjusted at any time by the amplification factor adjustment circuit 25, whereby the transfer characteristics of the FIR filter are automatically adjusted so as to be appropriately and optimally corresponding to the input signal. Adjusted to.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0055

[Correction method] Change

[Correction contents]

The correlation detection circuit 35 can be realized by a multiplier, for example. If a positive signal is output to the variable amplifier circuit 22 as a result of multiplying the two signals supplied to the correlation detection circuit 35, the variable amplifier circuit 22 reduces the amplification factor of the signal supplied from the tap 3 to a small value. Reduce to. As a result, the amplification factor in the variable amplification circuit 22 may become negative, but in this case, the variable amplification circuit 22 operates as an inverting amplification circuit. Conversely, when a negative output signal from the correlation detection circuit 35 is supplied to the variable amplification circuit 22, the variable amplification circuit 22 slightly increases the amplification factor of the signal supplied from the tap 3. Amplification factor of the variable amplification circuit 22 in the above operation is controlled by the delay circuit 30 and the correlation detection circuit 35.

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0056

[Correction method] Change

[Correction contents]

Next, a method of adjusting the amplitude of the signal output from the tap 1 in the variable amplifier circuit 20 will be described. Amplification factor of the variable amplifier circuit 20, in a similar manner as described above, are controlled by the delay circuit 28 and the correlation detection circuit 33. The tap 1, that is, the output signal of the A / D conversion circuit 8 is delayed by a delay circuit 28 for a predetermined time and output to the correlation detection circuit 33. This delay circuit 28
The delay time is set to be equal to the delay amount in the delay circuit 30 described above. On the other hand, the correlation detection circuit 33 is supplied with an error signal in addition to the output signal of the delay circuit 28, calculates the correlation between the two supplied signals, and outputs the result to the variable amplification circuit 20. In the variable amplification circuit 20, when the output of the correlation detection circuit 33 is positive, the amplification factor is slightly reduced, while when it is negative, the amplification factor is slightly increased to control the amplification factor of the variable amplification circuit 20.

[Procedure amendment 7]

[Document name to be amended] Statement

[Name of item to be corrected] 0057

[Correction method] Change

[Correction contents]

Next, a method of adjusting the amplitude of the signal output from the tap 2 in the variable amplification circuit 21 will be described. Amplification factor of the variable amplifier circuit 21, in a similar manner as described above, are controlled by the delay circuit 29 and the correlation detection circuit 34. The tap 2, that is, the output signal of the delay circuit 16 is delayed by the delay circuit 29 for a predetermined time and output to the correlation detection circuit 34. The delay time in the delay circuit 29 is set equal to the delay amount in the delay circuit 30 described above. On the other hand, the correlation detection circuit 34 is supplied with an error signal in addition to the output signal of the delay circuit 29, calculates the correlation between the two supplied signals, and outputs the result to the variable amplification circuit 21. In the variable amplification circuit 21, when the output of the correlation detection circuit 34 is positive, its amplification factor is slightly reduced,
On the other hand, when it is negative, the amplification factor of the variable amplification circuit 21 is controlled by slightly increasing the amplification factor.

[Procedure amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0058

[Correction method] Change

[Correction contents]

Next, a method of adjusting the amplitude of the signal output from the tap 4 in the variable amplification circuit 23 will be described. Amplification factor of the variable amplifier circuit 23, in a similar manner as described above, are controlled by the delay circuit 31 and the correlation detection circuit 36. The tap 4, that is, the output signal of the delay circuit 18 is delayed by the delay circuit 31 for a predetermined time and output to the correlation detection circuit 36. The delay time in the delay circuit 31 is set equal to the delay amount in the delay circuit 30 described above. On the other hand, the correlation detection circuit 36 is supplied with an error signal in addition to the output signal of the delay circuit 31, calculates the correlation between the two supplied signals, and outputs the result to the variable amplification circuit 23. In the variable amplification circuit 23, when the output of the correlation detection circuit 36 is positive, its amplification factor is slightly reduced,
On the other hand, when it is negative, the amplification factor of the variable amplification circuit 23 is controlled by slightly increasing the amplification factor.

[Procedure amendment 9]

[Document name to be amended] Statement

[Correction target item name] 0059

[Correction method] Change

[Correction contents]

Next, a method of adjusting the amplitude of the signal output from the tap 5 in the variable amplification circuit 24 will be described. Amplification factor of the variable amplifier circuit 24, in a similar manner as described above, are controlled by the delay circuit 32 and the correlation detection circuit 37. The tap 5, that is, the output signal of the delay circuit 19 is delayed by the delay circuit 32 for a predetermined time and output to the correlation detection circuit 37. The delay time in the delay circuit 32 is set equal to the delay amount in the delay circuit 30 described above. On the other hand, the correlation detection circuit 37 is supplied with an error signal in addition to the output signal of the delay circuit 32, calculates the correlation between the two supplied signals, and outputs the result to the variable amplification circuit 24. In the variable amplification circuit 24, when the output of the correlation detection circuit 37 is positive, the amplification factor is slightly reduced,
On the other hand, when it is negative, the amplification factor of the variable amplification circuit 24 is controlled by slightly increasing the amplification factor.

[Procedure amendment 10]

[Document name to be amended] Drawing

[Correction target item name] Fig. 5

[Correction method] Change

[Correction contents]

[Figure 5]

Claims (12)

[Claims] 1. A clock signal is reproduced from a reproduction signal of a predetermined recording pattern formed in advance at a plurality of positions on an optical recording medium, and an analog reproduction signal of the optical recording medium is reproduced at each change point of the clock signal. In an optical information reproducing apparatus for sampling and converting into a digital signal, the frequency of the clock signal is not less than twice the cutoff frequency determined by the transfer characteristic of the reproducing optical system and the relative speed between the optical recording medium and the reproducing optical system. An optical information reproducing device characterized by being set. 2. A clock signal is reproduced from a reproduction signal of a predetermined recording pattern formed in advance at a plurality of positions on the optical recording medium, and an analog reproduction signal of the optical recording medium is reproduced at each change point of the clock signal. In an optical information reproducing apparatus for sampling and converting into a digital signal, the frequency of the clock signal is not less than twice the cutoff frequency determined by the transfer characteristic of the reproducing optical system and the relative speed between the optical recording medium and the reproducing optical system. The optical recording medium is set, and the positions of the front end and the rear end of the pits or marks formed in a predetermined cycle are displaced stepwise from the reference position to a predetermined position corresponding to the recording information. Accordingly, the optical information reproducing apparatus is characterized in that the recorded information is recorded. 3. A waveform equalizer for performing waveform equalization on the digital signal reproduced from the optical recording medium, and a signal recorded on the recording medium based on a signal output by the waveform equalizer. The optical information reproducing apparatus according to claim 1, further comprising a decoding unit that restores recorded information. 4. A waveform equalizer that performs waveform equalization on the digital signal reproduced from the optical recording medium, and a signal recorded on the recording medium based on a signal output from the waveform equalizer. The optical information reproducing apparatus according to claim 2, further comprising a decoding unit that restores the recorded information. 5. A first transfer characteristic adjusting means for automatically adjusting a transfer characteristic of the waveform equalizing means based on a decoding result output by the decoding means. 3. The optical information reproducing device described in 3. 6. A first transfer characteristic adjusting means for automatically adjusting a transfer characteristic of the waveform equalizing means based on a decoding result output by the decoding means. 4. The optical information reproducing device described in 4. 7. The optical information reproducing apparatus according to claim 5, wherein the decoding means performs maximum likelihood decoding using the redundancy of the recorded information recorded on the optical recording medium. 8. The optical information reproducing apparatus according to claim 6, wherein the decoding means performs maximum likelihood decoding using the redundancy of the recorded information recorded on the optical recording medium. 9. An error correction unit that corrects a decoding error included in the output signal of the decoding unit using an error correction code included in the recording information; and the waveform based on the output signal of the error correction unit. The optical information reproducing apparatus according to claim 3, further comprising second transfer characteristic adjusting means for automatically adjusting the transfer characteristic of the equalizing means. 10. An error correction unit that corrects a decoding error included in an output signal of the decoding unit using an error correction code included in the recording information, and the waveform based on an output signal of the error correction unit. The optical information reproducing apparatus according to claim 4, further comprising: second transfer characteristic adjusting means for automatically adjusting the transfer characteristic of the equalizing means. 11. An error correction unit that corrects a decoding error included in the output signal of the decoding unit using an error correction code included in the recording information, and the waveform based on the output signal of the error correction unit. 8. The optical information reproducing apparatus according to claim 7, further comprising second transfer characteristic adjusting means for automatically adjusting the transfer characteristic of the equalizing means. 12. An error correction unit that corrects a decoding error included in the output signal of the decoding unit using an error correction code included in the recording information, and the waveform based on the output signal of the error correction unit. 9. The optical information reproducing apparatus according to claim 8, further comprising second transfer characteristic adjusting means for automatically adjusting the transfer characteristic of the equalizing means.