JPH0922882A - Formation of contact hole of minute semiconductor element - Google Patents

Formation of contact hole of minute semiconductor element

Info

Publication number
JPH0922882A
JPH0922882A JP8171378A JP17137896A JPH0922882A JP H0922882 A JPH0922882 A JP H0922882A JP 8171378 A JP8171378 A JP 8171378A JP 17137896 A JP17137896 A JP 17137896A JP H0922882 A JPH0922882 A JP H0922882A
Authority
JP
Japan
Prior art keywords
forming
contact hole
insulating film
spacer
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8171378A
Other languages
Japanese (ja)
Other versions
JP3170458B2 (en
Inventor
Jin Kook Kim
ジンクク キム
Sung Wook Park
ソンウク バク
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hyundai Electronics Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Industries Co Ltd filed Critical Hyundai Electronics Industries Co Ltd
Publication of JPH0922882A publication Critical patent/JPH0922882A/en
Application granted granted Critical
Publication of JP3170458B2 publication Critical patent/JP3170458B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physical Vapour Deposition (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent the damage of a lower insulation layer and insulation between undesired conductors against the side wall of a contact hole when an insulation spacer is formed in a fine contact hole by forming an insulation film for forming a spacer in a manner to weaken its covering characteristic of stepped part and forming an insulation spacer through anisotropic etching thereafter. SOLUTION: An oxide film 24 for forming a spacer is made relatively thick on an insulation film 22, while it is made reatively thin on the side wall of the film 22 in a contact hole and in the area connecting with an active region 20 on a silicon substrate 21 or conductive parts of other devices. The film 24 is anisotropically etched until the region 20 in the contact hole is exposed thoroughly to a blanket. Thus, in the interior of the contact hole, an insulation spacer 24" is prepared, and the devices and conductors protected by the film 22 can be prevented from being connected undesirably with the side wall of the contact hole even in the following steps such as vapor depositing of conductor, etc., for contact formation.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は半導体素子製造工程
中コンタクトホール形成方法に関するもので、特に微細
コンタクトホール内に絶縁スペーサ形成時下部絶縁層が
損傷されることを防止するための微細半導体素子のコン
タクトホール形成方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a contact hole during a semiconductor device manufacturing process, and more particularly to a fine semiconductor device for preventing a lower insulating layer from being damaged when an insulating spacer is formed in the fine contact hole. The present invention relates to a contact hole forming method.

【0002】[0002]

【従来の技術】半導体素子の集積度が大きくなることに
よりコンタクトホール形成がだんだんかたくなってい
る。これにより内部導体間の絶縁を効果的に維持しなが
ら接続する部分だけを開けて(open)やる微細コン
タクトホールを形成するために1次に幅が大きいコンタ
クトホールを形成した後、前記コンタクトホールの側壁
に絶縁スペーサを形成してコンタクトホールによる導体
間の短絡を防止する方法が広く利用されている。
2. Description of the Related Art Contact holes are becoming more and more difficult to form due to the increased integration of semiconductor devices. As a result, a contact hole having the first largest width is formed in order to form a fine contact hole by opening (opening) only a connecting portion while effectively maintaining insulation between the inner conductors. A method of forming an insulating spacer on a sidewall to prevent a short circuit between conductors due to a contact hole is widely used.

【0003】図3(a)(b)は従来の方法によるコン
タクトホール形成の過程を示す断面図で、これを通じて
従来技術を概略的に考察してみると次の通りである。
3 (a) and 3 (b) are sectional views showing a process of forming a contact hole by a conventional method, and the conventional technique will be schematically considered through the following steps.

【0004】図3(a)はシリコン基板11に図示しな
い他の素子及び配線を形成した後、絶縁膜12を形成す
る。この後、フォトリソグラフィ(photo lit
hography)工程を通じてコンタクトホールマス
クを形成し、これを蝕刻マスクとして利用して異方性乾
式蝕刻法により素子及び配線と接続される部分の絶縁膜
12を除去して、既に形成された活性領域10を露出さ
せた後、フォトレジストを除去して、スペーサ形成用酸
化膜13を蒸着した状態の断面図である。
In FIG. 3A, an insulating film 12 is formed after forming other elements and wiring (not shown) on the silicon substrate 11. After this, photolithography
A contact hole mask is formed through a photolithography process and is used as an etching mask to remove the insulating film 12 in a portion connected to the device and the wiring by an anisotropic dry etching method, thereby forming the active region 10 already formed. FIG. 6 is a cross-sectional view showing a state in which the photoresist is removed after exposing the film, and a spacer forming oxide film 13 is deposited.

【0005】次に、図3(b)に示すように、スペーサ
形成用酸化膜13をブランケットに上記コンタクトホー
ル内部の活性領域10が完全に露出されるまで異方性蝕
刻して、絶縁スペーサ13’を形成した状態の断面図
で、図3(b)の符号12’はスペーサ形成のための蝕
刻時絶縁膜12の一部が損傷されることを示している。
Next, as shown in FIG. 3B, the spacer forming oxide film 13 is anisotropically etched on the blanket until the active region 10 inside the contact hole is completely exposed, and the insulating spacer 13 is formed. In the cross-sectional view of the state where'is formed, reference numeral 12 'in FIG. 3B indicates that a part of the insulating film 12 during etching for forming the spacer is damaged.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、上述し
た従来方法においては、コンタクトホール内の絶縁スペ
ーサ形成時に、要求される過度蝕刻過程で下部の絶縁膜
が蝕刻されることとなる。これにより、コンタクトの形
成のための後続工程時、導体間の所望しない接続の発生
の憂慮が高い。
However, in the above-mentioned conventional method, the lower insulating film is etched in the required excessive etching process when the insulating spacer in the contact hole is formed. As a result, there is a great concern that an undesired connection between the conductors may occur during a subsequent process for forming the contact.

【0007】従って、上記したような従来技術の問題点
を解決するために案出された本発明は、微細コンタクト
ホール内に絶縁スペーサ形成時下部絶縁層が損傷される
ことを防止するための微細半導体素子のコンタクトホー
ル形成方法を提供することにその目的がある。
Therefore, the present invention devised to solve the above-mentioned problems of the prior art is intended to prevent the lower insulating layer from being damaged during the formation of the insulating spacer in the fine contact hole. It is an object of the present invention to provide a method for forming a contact hole in a semiconductor device.

【0008】[0008]

【課題を解決するための手段】上記目的を達成するため
に本発明は、半導体素子のコンタクトホールの形成方法
において、半導体基板を供給する工程と、前記半導体基
板上に第1絶縁膜を形成する工程と、前記第1絶縁膜の
所定部位を除去して前記半導体基板を露出させる開口部
を形成する工程と、全体構造の上部に第2絶縁膜を形成
するが、開口部の側壁に形成される前記第2絶縁膜の厚
さが前記第1絶縁膜上に形成される前記第2絶縁膜の厚
さより薄く形成する工程と、前記半導体基板の所定部位
が露出されるように前記第2絶縁膜を非等方性蝕刻して
前記開口部の側壁に絶縁膜スペーサを形成する工程とを
有することを特徴とする。
In order to achieve the above object, the present invention provides a method of forming a contact hole of a semiconductor element, the step of supplying a semiconductor substrate, and forming a first insulating film on the semiconductor substrate. A step of removing a predetermined portion of the first insulating film to form an opening exposing the semiconductor substrate, and forming a second insulating film on the upper portion of the entire structure, which is formed on a sidewall of the opening. Forming the second insulating film having a thickness smaller than that of the second insulating film formed on the first insulating film, and the second insulating film so that a predetermined portion of the semiconductor substrate is exposed. And anisotropically etching the film to form an insulating film spacer on the sidewall of the opening.

【0009】又は、上記目的を達成するために本発明
は、半導体素子のコンタクトホール形成方法において、
半導体基板を供給する工程と、前記半導体基板上に第1
絶縁膜を形成する工程と、前記第1絶縁膜上に均一な厚
さの第2絶縁膜を形成する工程と、前記第1及び第2絶
縁膜の所定部位を除去して前記半導体基板を露出させる
開口部を形成する工程と、全体構造の上部に均一な厚さ
の第3絶縁膜を形成する工程と、前記半導体基板の所定
部位が露出されるように前記第3絶縁膜を非等方性蝕刻
して前記開口部の側壁に絶縁膜スペーサを形成する工程
とを有することを特徴とする。
In order to achieve the above object, the present invention provides a method for forming a contact hole in a semiconductor device,
A step of supplying a semiconductor substrate, and a first step on the semiconductor substrate.
Forming an insulating film; forming a second insulating film having a uniform thickness on the first insulating film; and removing a predetermined portion of the first and second insulating films to expose the semiconductor substrate. A step of forming an opening that allows the third insulating film to have a uniform thickness on the entire structure, and the third insulating film is anisotropic so that a predetermined portion of the semiconductor substrate is exposed. And forming an insulating film spacer on the side wall of the opening by erosion etching.

【0010】[0010]

【発明の実施の形態】以下、添付された図1、図2を参
照して本発明の実施形態を詳述する。図1(a)(b)
は本発明の一実施形態によるコンタクトホール形成過程
を示す断面図で、先ず、図1(a)に示すように、シリ
コン基板21に図示しない他の素子及び配線を形成した
後、絶縁膜22を形成して後続工程により形成されるコ
ンタクトホールと上記コンタクトホールを介して接続さ
れる既に形成された素子及び配線を絶縁する。
BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the attached FIGS. FIG. 1 (a) (b)
1A is a cross-sectional view showing a process of forming a contact hole according to an embodiment of the present invention. First, as shown in FIG. 1A, after forming other elements and wiring not shown on a silicon substrate 21, an insulating film 22 is formed. A contact hole that is formed and is formed in a subsequent process is insulated from an element and a wiring that are already formed and connected through the contact hole.

【0011】続いて、フォトリソグラフィ(photo
lithography)工程を通じてコンタクトホ
ールマスクを形成した後、これを蝕刻マスクとして利用
して異方性乾式蝕刻法により素子及び配線と接続される
部分の絶縁膜22を除去して、既に形成された活性領域
20を露出させる。この時、絶縁膜22は通常の酸化
膜、BPSG(borophosphosilicat
e glass)膜、PSG(phosphosili
cate glass)膜又は上記列記した酸化膜の組
合により形成される。
Subsequently, photolithography (photo
After forming the contact hole mask through the lithography process, the insulating film 22 of the portion connected to the device and the wiring is removed by the anisotropic dry etching method using the contact hole mask as an etching mask, thereby forming the already formed active region. Expose 20. At this time, the insulating film 22 is a normal oxide film, or BPSG (borophosphosilicate).
e-glass) film, PSG (phosphosili)
Cate glass) film or a combination of the oxide films listed above.

【0012】次いで、通常のプラズマフォトレジスト蝕
刻法及び湿式フォトレジスト蝕刻法によりフォトレジス
トを除去して、スペーサ形成用酸化膜24を蒸着する。
この時、スペーサ形成用酸化膜24は絶縁膜22の上で
は相対的に厚くてコンタクトホール内の絶縁膜22の側
壁とシリコン基板21の活性領域20又は他の素子の導
体部分に接続される部分では相対的に薄く形成されるよ
うにする。
Next, the photoresist is removed by a usual plasma photoresist etching method and a wet photoresist etching method, and a spacer forming oxide film 24 is deposited.
At this time, the spacer forming oxide film 24 is relatively thick on the insulating film 22 and is connected to the sidewall of the insulating film 22 in the contact hole and the active region 20 of the silicon substrate 21 or the conductor portion of another element. Then, make it relatively thin.

【0013】スペーサ形成用絶縁膜24は次の表1に示
すように各々異なる工程条件を有する各々別個の蒸着工
程によりLTO(Low Temperature O
xide)、MTO(Middle Temperat
uer Oxide)、LPTEOS(Low Pre
ssur TEOS(tetraethoxysila
ne))の各酸化膜を形成することができる。
As shown in Table 1 below, the spacer forming insulating film 24 is formed by LTO (Low Temperature O) by a separate vapor deposition process having different process conditions.
xide), MTO (Middle Temperat)
er Oxide), LPTEOS (Low Pre)
ssure TEOS (tetraethoxysila)
ne)) each oxide film can be formed.

【0014】[0014]

【表1】 [Table 1]

【0015】ただし、TEOSはSi(OC254
表す。
However, TEOS represents Si (OC 2 H 5 ) 4 .

【0016】次いで、図1(b)に示すように、スペー
サ形成用酸化膜24をブランキットにコンタクトホール
内部の活性領域20が完全に露出されるまで異方性蝕刻
する。この時、絶縁膜22上部にはスペーサ用酸化膜の
一部24’が残留したり下部の絶縁膜22が蝕刻された
りしても消耗される絶縁膜の厚さが非常に小さくて絶縁
膜により保護を受けている素子及び導体が露出されなく
て充分な厚さの絶縁膜22により絶縁状態にあるように
なる。また、コンタクトホール内部も絶縁スペーサ2
4”によりコンタクト形成のための導体蒸着等、後続工
程によっても絶縁膜22により保護されている素子及び
導体がコンタクトホールの側壁に所望しない接続が生じ
ることを防止できることになる。
Next, as shown in FIG. 1B, the spacer forming oxide film 24 is anisotropically etched by blanket until the active region 20 inside the contact hole is completely exposed. At this time, even if a part of the spacer oxide film 24 ′ is left on the insulating film 22 or the lower insulating film 22 is etched, the thickness of the insulating film consumed is very small. The protected element and conductor are not exposed, and the insulating film 22 having a sufficient thickness provides an insulating state. Also, the inside of the contact hole is the insulating spacer 2.
By 4 ", it is possible to prevent undesired connection of the element and the conductor protected by the insulating film 22 to the side wall of the contact hole even in the subsequent step such as vapor deposition of a conductor for forming a contact.

【0017】一方、図2(a)(b)は本発明の異なる
実施形態によるコンタクトホール形成過程を示す断面図
で、先ず、図2(a)に示すように、シリコン基板31
に図示しない他の素子及び配線を形成する。その後、絶
縁膜32を形成するとともに、この絶縁膜32の上に酸
化膜35を形成した後、フォトリソグラフィ(phot
o lithography)工程を通じてコンタクト
ホールマスクを形成し、これを蝕刻マスクとして利用し
て異方性乾式蝕刻法により素子及び配線と接続される部
分の絶縁膜32、酸化膜35を除去して、既に形成され
た活性領域30を露出されるコンタクトホールを形成す
る。この時、絶縁膜32は通常の酸化膜、BPSG膜、
PSG膜又は上記列記した酸化膜の組合により生成され
る。
On the other hand, FIGS. 2A and 2B are sectional views showing a process of forming a contact hole according to another embodiment of the present invention. First, as shown in FIG.
Other elements and wiring not shown are formed. After that, an insulating film 32 is formed, an oxide film 35 is formed on the insulating film 32, and then photolithography (photo) is performed.
A contact hole mask is formed through an o-lithography process and is used as an etching mask to remove the insulating film 32 and the oxide film 35 in a portion connected to the device and the wiring by an anisotropic dry etching method. A contact hole is formed to expose the exposed active region 30. At this time, the insulating film 32 is an ordinary oxide film, a BPSG film,
It is produced by a combination of the PSG film or the oxide films listed above.

【0018】次いで、通常のプラズマフォトレジスト蝕
刻法及び湿式フォトレジスト蝕刻法によりフォトレジス
トを除去して、均一な厚さを有るスペーサ形成用酸化膜
36を次の工程条件下で蒸着する。
Next, the photoresist is removed by the usual plasma photoresist etching method and wet photoresist etching method, and the spacer forming oxide film 36 having a uniform thickness is deposited under the following process conditions.

【0019】 温度:800〜950℃ 圧力:0.1〜4.0Torr ソースガス:SiH2Cl2(dichloros,la
ne)+N2O ガス量:60sccm:60sccm ガスの比率:1:10 この時、絶縁膜32の上に酸化膜を形成することによ
り、全体的に絶縁層が絶縁膜32の上では相対的に厚く
てコンタクトホール内の絶縁膜32の側壁とシリコン基
板31の活性領域30又は他の素子の導体部分に接続さ
れる部分では相対的に薄く形成される。
Temperature: 800 to 950 ° C. Pressure: 0.1 to 4.0 Torr Source gas: SiH 2 Cl 2 (dichloros, la)
ne) + N 2 O gas amount: 60 sccm: 60 sccm gas ratio: 1:10 At this time, by forming an oxide film on the insulating film 32, the insulating layer is relatively relatively formed on the insulating film 32 as a whole. The side wall of the insulating film 32 in the contact hole is thick and is relatively thin in the portion connected to the active region 30 of the silicon substrate 31 or the conductor portion of another element.

【0020】次いで、図2(b)に示すように、スペー
サ形成用酸化膜36、酸化膜35を異方性蝕刻法により
蝕刻して絶縁スペーサ36’を形成する。この時、絶縁
膜32の上部には酸化膜35の一部35’が残留して下
部の絶縁膜32は損失なき残留酸化膜35’により保護
されることになる。また、コンタクトホール内部も絶縁
スペーサ36’によりコンタクト形成のための導体蒸着
等の後続工程によっても、絶縁膜32により保護されて
いる素子及び導体がコンタクトホールの側壁に所望しな
い接続が生じることを防止できることになる。
Next, as shown in FIG. 2B, the spacer forming oxide film 36 and the oxide film 35 are etched by an anisotropic etching method to form an insulating spacer 36 '. At this time, a part 35 'of the oxide film 35 remains on the upper portion of the insulating film 32, and the lower insulating film 32 is protected by the lossless residual oxide film 35'. Also, the inside of the contact hole is prevented by the insulating spacer 36 'from causing an undesired connection between the element and the conductor protected by the insulating film 32 on the side wall of the contact hole even in a subsequent step such as vapor deposition of a conductor for forming a contact. You can do it.

【0021】上記のように構成した本発明においては、
スペーサ形成用絶縁膜24,36を段差部被覆特性(s
tep coverage)が脆弱するように形成した
後、異方性蝕刻により絶縁スペーサ24”,36’を形
成することにより、微細コンタクトホール内に絶縁スペ
ーサ形成時下部絶縁層が損傷されることを防止する。ま
た、コンタクトホール側壁への所望しない導体間の接続
を防止できる。
In the present invention configured as described above,
The spacer forming insulating films 24 and 36 are covered with the step portion covering characteristic (s
The insulating spacers 24 ″ and 36 ′ are formed by anisotropic etching after forming the insulating layer to be fragile, so that the lower insulating layer is prevented from being damaged in forming the insulating spacer in the fine contact hole. Further, it is possible to prevent undesired connection between conductors on the side wall of the contact hole.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の一実施形態によるコンタクトホール
形成過程を示めす断面図である。
FIG. 1 is a cross-sectional view showing a process of forming a contact hole according to an embodiment of the present invention.

【図2】 本発明の異なる実施形態によるコンタクトホ
ール形成過程を示めす断面図である。
FIG. 2 is a sectional view showing a process of forming a contact hole according to another embodiment of the present invention.

【図3】 従来の方法によるコンタクトホール形成過程
を示めす断面図である。
FIG. 3 is a cross-sectional view showing a process of forming a contact hole by a conventional method.

【符号の説明】[Explanation of symbols]

10…活性領域、21,31…シリコン基板、22,3
2…絶縁膜、24,36…スペーサ形成用酸化膜、2
4”…絶縁スペーサ、35…酸化膜、36’…絶縁スペ
ーサ。
10 ... Active region, 21, 31 ... Silicon substrate, 22, 3
2 ... Insulating film, 24, 36 ... Spacer forming oxide film, 2
4 "... Insulating spacer, 35 ... Oxide film, 36 '... Insulating spacer.

フロントページの続き (72)発明者 バク ソンウク 大韓民国 467−860 キョウンキド イチ ヨンクン ブバリュブ アミ−リ サン 136−1 ヒュンダイ エレクトロニクス インダストリイズ カンパニー リミテ ッド内Front Page Continuation (72) Inventor Bak Sung Wook South Korea 467-860 Kyung Kidd Yi Yong Kun Buba Ryu Ami Risan 136-1 Hyundai Electronics Industry Co., Ltd. Limited

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子のコンタクトホールの形成方
法において、 半導体基板を供給する工程と、 前記半導体基板上に第1絶縁膜を形成する工程と、 前記第1絶縁膜の所定部位を除去して前記半導体基板を
露出させる開口部を形成する工程と、 全体構造の上部に第2絶縁膜を形成するが、開口部の側
壁に形成される前記第2絶縁膜の厚さが前記第1絶縁膜
上に形成される前記第2絶縁膜の厚さより薄く形成する
工程と、 前記半導体基板の所定部位が露出されるように前記第2
絶縁膜を非等方性蝕刻して前記開口部の側壁に絶縁膜ス
ペーサを形成する工程とを有することを特徴とする微細
半導体素子のコンタクトホール形成方法。
1. A method of forming a contact hole in a semiconductor device, comprising: supplying a semiconductor substrate; forming a first insulating film on the semiconductor substrate; and removing a predetermined portion of the first insulating film. Forming an opening exposing the semiconductor substrate; and forming a second insulating film on the upper portion of the entire structure, wherein the thickness of the second insulating film formed on the sidewall of the opening is the first insulating film. Forming the second insulating film to a thickness smaller than that of the second insulating film formed thereon, and forming the second insulating film so that a predetermined portion of the semiconductor substrate is exposed.
And a step of forming an insulating film spacer on the sidewall of the opening by anisotropically etching the insulating film.
【請求項2】 前記請求項1に記載の微細半導体素子の
コンタクトホール形成方法において、前記第2絶縁膜を
0.1〜4.0Torrで形成することを特徴とする微
細半導体素子のコンタクトホール形成方法。
2. The method of forming a contact hole in a fine semiconductor device according to claim 1, wherein the second insulating film is formed at 0.1 to 4.0 Torr. Method.
【請求項3】 前記請求項2に記載の微細半導体素子の
コンタクトホール形成方法において、前記第2絶縁膜を
SiH4及びO2ガスを使用して300〜500℃で形成
する工程を有することを特徴とする微細半導体素子のコ
ンタクトホール形成方法。
3. The method of forming a contact hole of a fine semiconductor device according to claim 2, further comprising the step of forming the second insulating film at 300 to 500 ° C. using SiH 4 and O 2 gas. A method for forming a contact hole in a featured fine semiconductor device.
【請求項4】 前記請求項2に記載の微細半導体素子の
コンタクトホール形成方法において、前記第2絶縁膜を
SiH4及びN2Oガスを使用して700〜900℃で形
成する工程を有することを特徴とする微細半導体素子の
コンタクトホール形成方法。
4. The method for forming a contact hole of a fine semiconductor device according to claim 2, further comprising the step of forming the second insulating film at 700 to 900 ° C. using SiH 4 and N 2 O gas. A method for forming a contact hole in a fine semiconductor device, comprising:
【請求項5】 前記請求項2に記載の微細半導体素子の
コンタクトホール形成方法において、第2絶縁膜をSi
(OC254及びN2Oガスを使用して600〜800
℃で形成する工程を有することを特徴とする微細半導体
素子のコンタクトホール形成方法。
5. The method for forming a contact hole in a fine semiconductor device according to claim 2, wherein the second insulating film is formed of Si.
600-800 using (OC 2 H 5 ) 4 and N 2 O gas
A method of forming a contact hole in a fine semiconductor device, comprising the step of forming the contact hole at a temperature of ° C.
【請求項6】 半導体素子のコンタクトホール形成方法
において、 半導体基板を供給する工程と、 前記半導体基板上に第1絶縁膜を形成する工程と、 前記第1絶縁膜上に均一な厚さの第2絶縁膜を形成する
工程と、 前記第1及び第2絶縁膜の所定部位を除去して前記半導
体基板を露出させる開口部を形成する工程と、 全体構造の上部に均一な厚さの第3絶縁膜を形成する工
程と、 前記半導体基板の所定部位が露出されるまで前記第3絶
縁膜を非等方性蝕刻して前記開口部の側壁に絶縁膜スペ
ーサを形成する工程とを有することを特徴とする微細半
導体素子のコンタクトホール形成方法。
6. A method of forming a contact hole in a semiconductor device, comprising: supplying a semiconductor substrate; forming a first insulating film on the semiconductor substrate; and forming a first insulating film on the first insulating film with a uniform thickness. A step of forming a second insulating film, a step of removing predetermined portions of the first and second insulating films to form an opening exposing the semiconductor substrate, and a third step of forming a uniform thickness on the entire structure. Forming an insulating film; and anisotropically etching the third insulating film until a predetermined portion of the semiconductor substrate is exposed to form an insulating film spacer on a sidewall of the opening. A method for forming a contact hole in a featured fine semiconductor device.
【請求項7】 前記請求項6に記載の微細半導体素子の
コンタクトホール形成方法において、前記第3絶縁膜を
0.1〜4.0Torrで形成することを特徴とする微
細半導体素子のコンタクトホール形成方法。
7. The method of forming a contact hole in a fine semiconductor device according to claim 6, wherein the third insulating film is formed at 0.1 to 4.0 Torr. Method.
【請求項8】 前記請求項7に記載の微細半導体素子の
コンタクトホール形成方法において、前記第3絶縁膜を
SiH2Cl2及びN2Oガスを使用して800〜950
℃で形成する工程を有することを特徴とする微細半導体
素子のコンタクトホール形成方法。
8. The method of forming a contact hole of a fine semiconductor device according to claim 7, wherein the third insulating film is formed by using SiH 2 Cl 2 and N 2 O gas at 800 to 950.
A method of forming a contact hole in a fine semiconductor device, comprising the step of forming the contact hole at a temperature of ° C.
JP17137896A 1995-06-30 1996-07-01 Method for forming contact hole in fine semiconductor device Expired - Fee Related JP3170458B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019950019157A KR100190381B1 (en) 1995-06-30 1995-06-30 Method for forming a contact hole of a semiconductor device
KR1995P19157 1995-06-30

Publications (2)

Publication Number Publication Date
JPH0922882A true JPH0922882A (en) 1997-01-21
JP3170458B2 JP3170458B2 (en) 2001-05-28

Family

ID=19419500

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17137896A Expired - Fee Related JP3170458B2 (en) 1995-06-30 1996-07-01 Method for forming contact hole in fine semiconductor device

Country Status (3)

Country Link
JP (1) JP3170458B2 (en)
KR (1) KR100190381B1 (en)
CN (1) CN1146070A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040038283A (en) * 2002-10-31 2004-05-08 아남반도체 주식회사 Method for forming plug inside of contact or via hole in semiconductor device
US9923120B2 (en) 2015-09-26 2018-03-20 Nichia Corporation Semiconductor light emitting element and method of producing the same
US10438845B2 (en) 2018-03-02 2019-10-08 Toshiba Memory Corporation Semiconductor device and manufacturing method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040038283A (en) * 2002-10-31 2004-05-08 아남반도체 주식회사 Method for forming plug inside of contact or via hole in semiconductor device
US9923120B2 (en) 2015-09-26 2018-03-20 Nichia Corporation Semiconductor light emitting element and method of producing the same
US10424693B2 (en) 2015-09-26 2019-09-24 Nichia Corporation Semiconductor light emitting element having first semiconductor layer and holes through second semiconductor layer to expose the first semiconductor layer
US10438845B2 (en) 2018-03-02 2019-10-08 Toshiba Memory Corporation Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
CN1146070A (en) 1997-03-26
JP3170458B2 (en) 2001-05-28
KR100190381B1 (en) 1999-06-01
KR970003530A (en) 1997-01-28

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