JPH09219098A - Semiconductor storage and its drive circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To remarkably reduce a chip size by providing the circuit with first, second drivers, a word line and a redundancy word line and commonly inputting an address signal to the first, second drivers. SOLUTION: At the time of redundancy operation, an X decoder/driver 3 isn't driven by an XRDN signal, and on the other hand, a redundancy driver 5 is driven. Then, the driver 5 receiving prescribed address information from a redundancy decoder makes a redundancy main word line RML0 active. On the other hand, a row address decoder 14 selects address information from a redundancy control circuit by the XRDN signal to output the information to a row address driver 15. The driver 15 makes e.g. a RAI0 signal an H level, and a redundancy sub-word driver 6B drives an RSWL0 to the H level. Thus, a redundancy memory cell is selected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a driving circuit thereof, and more particularly to a semiconductor memory device having a redundancy circuit (redundancy circuit) and a driving circuit thereof.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor memory device such as a dynamic random access memory (DRAM), the rate of occurrence of defects increases as the degree of integration increases, especially in the memory element region (in the memory cell array). More often occurs. Redundant circuits are used to eliminate such defects in memory cells.

FIG. 10 is a drive circuit diagram of a semiconductor memory device showing a conventional example. As shown in FIG. 10, first, a conventional semiconductor memory device 10a includes a plurality of divided memory cell arrays 11 and the divided memory cell array 11
Multiple sub-word drivers (SW
D) 12a, a plurality of sense amplifiers (SA) 13 driven at the time of reading, and a plurality of sub-word drivers (SW)
D) 12a and a plurality of redundancy sub-word drivers (RSWD) 12b. Each of the memory cell arrays 11 divided into these plurality has a SW
It is divided in the row direction at D12a and in the column direction at SA13.

Although an X decoder or a Y decoder (not shown) is used as a drive circuit for selecting the memory cell array 11 of the DRAM 10a, a row address decoder 14a as a part of the X decoder and a row address decoder 14b for redundancy are used. A plurality of row address (R) drivers 15a driven by the row address decoder 14a, and the redundancy row address decoder 1
There is a redundancy row address (RR) driver 15b driven by 4b.

In this divided decoding type word driver, one of the plurality of SWDs 12a is selected by the above X decoder. R is assigned to the selected SWD 12a.
The row address (RA
I) A signal is input, and one of the selected four sub-word lines (SWL) is selected.

When a defective address in the memory cell array 11 is selected, the redundancy row address decoder 14b selects the redundancy RSWD 12b via the RR driver 15b. A redundancy row address (RRAI) signal, which is an output signal of the redundancy RR driver 15b, is input to the selected redundancy RSWD 12b, and one of the selected redundancy subword lines (RSW) is selected.
L) is selected.

As an example of driving the R driver 15a and the RR driver 15b, the 4-bit RAI signal and the RRAI signal are respectively supplied to the row address decoder 14.
a and the row address decoder 14b for redundancy are activated. Of these decoders 14a and 14b, the row address decoder 14a is the X address signal X1.
B and X2B are decoded to obtain four signals X1B2B and X1.
2B, X1B2, and X12 are generated, and a 4-bit row address driver activation (RAIS) signal is output at the input timing of the row address enable (RAE) signal. Also, the row address decoder 1 for redundancy
4b includes redundancy address signals RX1B2B, RX12B, RX1B2 and RX1 which have already been decoded.
Since 2 is input, row address enable (RA
E) Inputting a signal outputs a 4-bit redundancy row address driver activation (RRAIS) signal.

[0008]

However, in the conventional semiconductor memory device, the normal subword driver (SWD) 12a connected to the periphery of the memory cell is used.
And redundancy subword driver (RSWD) 12
Since b is required separately, an R driver 15a and an RR driver 15b for driving them and an X decoder are formed, and these R driver 15a and RR driver 15b are formed.
It is also necessary to separately provide a row address decoder 14a for driving the memory and a row address decoder 14b for redundancy. Therefore, the row address driver 14
a and redundancy row address driver 14b and S
Since the WD 12a and the RSWD 12b are connected by different wirings, and the decoder and the R driver 15a and the RR driver 15b are also separately wired, there is a drawback that the total number of wirings increases and the chip area increases.

Further, the conventional semiconductor memory device has the SWD1
The number of wirings passing over 2a and RSWD 12b also increases, which also causes a problem of increasing the chip area.

An object of the present invention is to provide a semiconductor memory device and a driving circuit thereof which can reduce the total number of wirings and circuits and the chip area.

[0011]

A semiconductor memory device of the present invention includes a plurality of memory cells, a plurality of redundancy memory cells, a first driver provided corresponding to the plurality of memory cells, and a plurality of memory cells. A first driver having a second driver provided corresponding to the redundancy memory cell, a word line connected to the first driver, and a redundancy word line connected to the second driver; And an address signal is commonly input to the second driver.

A semiconductor memory device driving circuit according to the present invention is a semiconductor memory device driving circuit for inputting first address information, second address information and a determination signal and outputting an output signal. It is characterized in that the first address information is output as an output signal by the determination signal of the level 1 and the second address information is output as an output signal by the determination signal of the second level.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to clarify the above and other objects, features, and effects of the present invention, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing a semiconductor memory device according to a first embodiment of the present invention. The semiconductor memory device of the present embodiment includes an X decoder for selecting a main word line (MWL) and a means for selecting one subword line from a plurality of subword lines from the selected main word line MWL. The division decoding system is adopted.

According to FIG. 1, the address buffer 1 receives as its input an address consisting of bits X1 to X12,
The address information of bits X3 to X12 is output to the redundancy decoder 2 and the X decoder / driver 3. The X decoder / driver 3 selects one main word line MWL of the memory cell array 11 based on the address information of the bits X3 to X12.

The redundancy decoder 2 drives the redundancy control circuit 4 based on the address information consisting of the bits X3 to X12 from the address buffer 1. The redundancy control circuit 4 supplies a 4-bit output signal to the redundancy driver 5. Furthermore, the redundancy control circuit 4 is
A redundancy determination (XRDN) signal is supplied to the X decoder / driver 3 and the redundancy driver 5.

The address buffer 1 supplies address information consisting of bits X1 and X2 of the address to the row address decoder 14. The row address decoder 14 is
The 4-bit information and the XRDN signal from the redundancy control circuit 4 are input.

The row address decoder 14 further includes an address enable (RAE) signal from the row address strobe generator shown in FIG. 5 and an address latch (XLAT).
Input the signal and precharge (XPRE) signal, and
The bit signal is output to the plurality of row drivers 15. The row driver 15 outputs the 4-bit signal to the memory cell array 11
To the selected memory cell.

FIG. 2 is a drawing showing a more detailed semiconductor memory device including the row address decoder 14, the row driver 15, and the memory array 11 according to the first embodiment of the present invention. According to FIG. 2, the DRAM 10 includes a plurality of divided memory cell arrays 11, a plurality of sub word drivers (SWDs) 12 for driving each of the divided memory cell arrays 11, and a plurality of senses driven during reading. And an amplifier (SA) 13. Each of the memory cell arrays 11 divided into these plurality has a SW
It is divided in the row direction at D12, and is divided in the column direction at SA13.

The drive circuit for selecting the memory cell array 11 of the DRAM 10 uses an X decoder or a Y decoder as in the above-mentioned conventional example. The row address decoder 14 as a part of the X decoder and the row address decoder 14 are used. It comprises a plurality of row address (R) drivers 15 driven by the row address decoder 14. This divided decoding type word driver selects one of the plurality of SWDs 12 by the above-mentioned X decoder, and selects the selected SWD.
A row address selection (RAI) signal which is an output signal of the R driver 15 is input to D12. Therefore, one of the four selected subword lines (that is, a quarter) is selected. The signals X1B and X2B input to the row address decoder 14 are output signals from the address buffer 1 shown in FIG.
1B2B, RX12B, RX1B2, RX12 are shown in FIG.
The output signal from the redundancy control circuit 4 shown in FIG.

FIG. 3 is a drawing showing in more detail the configuration including a part of the memory block and the driver circuit of the memory cell array according to the first embodiment of the present invention.

The X decoder / driver 3 has main word lines MWL0 to 255, and the redundancy driver 5 has redundancy main word lines RMWL0 to 15.
Are connected, but for simplification of description, in FIG.
The main word line MWL0 and the redundancy main word line RMWL0 will be extracted and described.

A main word line MWL0 is connected to the X decoder / driver 3, and the main word line MWL0 is connected to the main word line MWL0.
Are connected to the sub-word driver 6A. The sub-word driver 6A is divided into four blocks, and the sub-word lines SWL0 to SWL3 are connected to the respective blocks. The sub-word driver 6A inputs the RAI signals RAI0-3 to the respective blocks and selects one of the main word line MWL0 and one of the RAI signals RAI0-3 to selectively drive one of the corresponding sub-word lines SWL0-3. To be done.

The redundancy main word line RMWL0 is connected to the redundancy driver 5, and the redundancy main word line RMWL0 is connected to the redundancy subword driver 6B. The sub-word driver 6B is divided into four blocks, and the redundancy sub-word lines RSWL0 to RSW are provided in the respective blocks.
L3 is connected. The redundancy subword driver 6B inputs the RAI signals RAI0 to 3 to the respective blocks, and the redundancy main word lines RMWL0 and RA
When one of the I signals RAI0 to 3 is selected, one of the corresponding redundancy subword lines RSWL0 to 3 is selectively driven.

Row address driver 15 responds to the output from row address decoder 14 with RAI signals 0-3.
Is output. The row address driver 15 drives the RAI signals RAI0 to 3 to potentials within a predetermined voltage range. For example, the row address driver 15 uses the RAI signal RAI0.
.About.2 are driven to 2.4V, while RAI signal RAI3 is driven to 3.7V.

In normal operation, X is generated by the XRDN signal.
The decoder / driver 3 is driven and the redundancy driver 5 is not driven. Therefore, the X decoder / driver 3 which receives the predetermined address information from the address buffer 1
Activates the main word line MWL0. On the other hand, the row address decoder 14 selects the address information from the address buffer 1 according to the XRDN signal,
The information is decoded into 4-bit information and output to the row address driver 15. The row address buffer 15 is
For example, the RAI0 signal is set to high level, and the sub word driver 6A drives SWL0 to high level.

On the other hand, during the redundancy operation, the X decoder / driver 3 is not driven by the XRDN signal, while the redundancy driver 5 is driven. Therefore, the redundancy driver 5 receiving the predetermined address information from the redundancy decoder 2 activates the redundancy main word line RMWL0. On the other hand, the row address decoder 14 selects the address information from the redundancy control circuit 4 according to the XRDN signal and outputs the information to the row address driver 15. The row address buffer 15 sets, for example, the RAI0 signal to a high level, and the redundancy subword driver 6B uses RSW.
Drive L0 to high level. As a result, the redundancy memory cell is selected.

As described above, according to the present embodiment, the memory cell for normal operation and the memory cell for redundancy can be selected even if there is only one row address decoder. More specifically, the subword driver 6A and the redundancy subword driver 6B, which are connected to the memory cell array for normal operation, commonly receive the outputs RAI0 to RAI3 from the row address driver 15, and respectively receive the main word line MWL and the redundancy main word. By driving the line RMWL, the respective sub-word lines SWL and redundancy sub-word lines RS
It drives the WL.

FIG. 4 is a diagram showing one block of the sub-word driver circuit 6A according to the first embodiment of the present invention. As is apparent from FIG. 4, the sub word driver 6A
1 block activates the sub word line SWL0 by the main word line MWL0 and the RAI0 signal. The configuration of the redundancy subword driver 6B is the same as that of the driver 6A.

FIG. 5 is a diagram showing a row address strobe (RAS) timing generator according to the first embodiment of the present invention. This device responds to the RAS signal by RA
It outputs the E signal, the XLAT signal, and the XPRE signal.

FIG. 6 is a circuit diagram of the row address decoder 14. As shown in FIG. 6, the row address decoder 14 according to the present embodiment is provided with X address signals X1B, X1.
Inverters 17A-17D to decode 2B
And a first logic gate section 16 composed of NAND gates 18A to 18D, and an output A of the first logic gate section 16 is separated and latched by the XLAT signal and the XPRE signal, and the held value B Of the address latch circuits 19A to 19D, the output B of the address latch circuits 19A to 19D in the normal state and the row address signals RX1B2B, RX12B in the redundancy state,
RX1B2 and RX12 are XRDN signals and inverter 2
A normal / redundancy switching circuit 2 which switches by an inverted signal via 0 and outputs the switched value C.
1A to 21D and the outputs C of the normal / redundancy switching circuits 21A to 21D are activated by the RAE signal,
In order to generate the row address driver activation inversion signal D and the row address driver activation signals RAIS0 to RAIS3, the second logic gate section 22 composed of NAND gates 23A to 23D and inverters 24A to 24D is provided. With this one row address decoder 14,
By separating and holding the normal decode signal, the normal decode signal and the redundancy decode signal are output.

Thus, the X address signals X1B, X2
B is directly connected to the NAND gates 18A to 18D forming the first logic gate section 16 or the inverters 17A to 17D.
When input via D, these NAND gates 18A
One of the four outputs A of ~ 18D is activated.
One decode signal A activated by the first logic gate section 16 is output at a low level and is input to, for example, the address latch circuit 19A.

Further, the normal / redundancy switching circuit 2
1A to 21D are the decode signal B of the normal address and the decode signal RX1B of the redundancy address, respectively.
2B, RX12B, RX1B2, RX12, and enter X
Based on the RDN signal and its complementary signal XRDNB, it is determined whether or not there is redundancy, and the signal C is output.

Normally, the XRDN signal and the redundancy address signals RX1B2B, RX12B, RX1B2, R
Since X12 is delayed as compared with the normal address signal B, the timing of the XLAT signal is set to be the same as the timing of the redundancy address signal RX1B2B. The address is not output once and then switched to the redundancy address. Therefore, when the data of the output C of the normal / redundancy switching circuits 21A to 21D is determined, the RAE signal is input to the NAND gates 23A to 23D of the second logic gate unit 22 and RAIS0 to RAIS0 are input.
RAIS3 signal is output.

FIG. 7 is a timing chart of various signals in FIG. As shown in FIG. 7, XPRE in FIG.
At a timing T1 when the signal becomes high level, an intermediate point of the address latch circuits 19A to 19D (E in FIG.
The point) is set to high floating, and the input of the point A is held at the point E at the timing T2 when the XLAT signal becomes high level. In addition, the redundancy address signal (RX1
B2B) is selected, and at the timing T3 when the redundancy circuit operates, the B point input or the RX1B2B input is selected depending on the normal or the redundancy, and the RAIS is activated at the timing T4 when the RAE signal becomes high level.

FIG. 8 is a diagram of the address latch circuit shown in FIG. As shown in FIG. 8, the address latch circuit 19A, which is representative of four, receives the output A of the first logic gate section 16 and an NMOS transistor 25 as a switching element whose gate is controlled by an XLAT signal. , Connected between this NMOS transistor 25 and VCC,
A CMOS which is connected to a PMOS transistor 26 as a switching element whose gate is controlled by the XPRE signal and an NMOS transistor 25 and outputs a latch output B
And a data holding circuit 27 formed by an inverter. The high / low timing of each signal and data is as shown in FIG.

First, before the address decoder signal A is input, that is, at the timing T1, the XPRE signal, X
Since the LAT signal is at the low level, the NMOS
The transistor 25 turns off and the PMOS transistor 26
Is on. Therefore, the address decode hold signal B, which is the output of the data hold circuit 27, continues to output a low level.

Next, when the decode signal is taken in, X
Since the PRE signal becomes high level and the PMOS transistor 26 is turned off, the data holding circuit 27 continues to hold the decode signal B at low level.

Further, at the timing T2 when the address changes and the output A of the logic gate section 16 is determined from the high level to the low level, the XLAT signal consisting of one high level pulse is supplied. The data is turned on for one pulse period, and the data opposite to the data held in the data holding circuit 27 is written. Therefore, the output B of the data holding circuit 27 becomes high level,
Moreover, this high level data is kept held. At this time, even if the input decode signal A changes, the NMOS transistor 25 is off, so that the high-level data is kept held, so that no malfunction occurs due to the input of the next address. That is, the timing T
This is because at 3 and T4, the NMOS transistor 25 is at the low level, and the address latch circuit 19A continues to hold data.

FIG. 9 is a normal / redundancy switching circuit diagram shown in FIG. As shown in FIG. 9, the normal / redundancy switching circuit 21A, which is representative of four circuits, includes two CMOS transfer gates 28 and 2 in which PMOS transistors and NMOS transistors are connected in parallel.
9. A normal address decode hold signal B is input to the first transfer gate 28, and a redundancy address decode signal RX1B2B is input to the second transfer gate 29, both of which are controlled by the XRDN signal and its complementary signal XRDNB. Then, the switching output C as the RAI selection signal is output.

First, in the initial state, that is, at the timing T1, the input B in the normal state and the input R in the redundancy state are provided.
Both X1B2B are at low level. At this time,
Since the XRDN signal is at the low level and its complementary signal XRDNB is at the high level, the first CM
OS transfer gate 28 is on, second CMOS
The transfer gate 29 is off. Therefore,
The output signal C is the first CMOS transfer gate 2
Since 8 is on, the low level of the input B is output as it is.

Next, as shown at the timing T2, since the redundancy control circuit 4 does not operate,
When the normal address is selected, the XRDN signal is low, its complementary signal XRDNB remains high, and the input B is output as it is as the RAI selection signal C.

On the other hand, as shown at the timing T3, when the redundancy control circuit 4 operates and the redundancy address is selected, the XRDN signal becomes high and the complementary signal XRDNB becomes low, so that the input RX1B2B is output to C. , Switch from normal address to redundancy address. The reverse operation is also performed in the same manner.

Thereafter, as shown at timing T4,
When the RAE signal becomes high, the C output which becomes high is output as the row address driver activation signal RAIS0.

In the present embodiment, by separating and holding the decode signal in the normal state, even if a continuous address signal is input, the data is separated so that no malfunction occurs, and in the normal state and the redundancy state. By switching the address signal and the decode signal of, there is an advantage that the decode outputs can be made the same. That is, the normal address decode hold signal B
And address decode signal RX1B2B for redundancy
Is switched by the row address decoder 14,
Since the normal driver and the redundancy driver can be shared, it is not necessary to use the driver circuit dedicated to the redundancy which has been conventionally required, and the number of circuits can be reduced by half. Further, since the row address selection signal (RAI selection signal) can be shared, the number of wirings passing over the sub word driver (SWD) can be reduced by half, and the chip area can be greatly reduced.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and can be modified as long as the scope of the invention does not change.

[0047]

As described above, the semiconductor memory device of the present invention can select the memory cell array in the normal operation and the memory cell array in the redundancy operation by the output from one row address driver. Further, the semiconductor memory device drive circuit of the present invention includes a first logic gate unit for driving a row address signal, and an address for separating and holding the output of the first logic gate unit by the XLAT signal and the XPRE signal. The latch circuit, the normal / redundancy switching circuit that switches the output of the address latch circuit in the normal state and the row address signal in the redundancy by the XRDN signal, and the output of the normal / redundancy switching circuit are activated by the row address enable signal to activate a plurality of signals. By having one row address decoder having a second logic gate section for generating a row address decode signal for the memory cell array, the row address driver selection signal in the normal state and the redundancy state can be made the same. As described above, since the row address driver is shared and the row address wiring passing over the sub word driver can be halved, the chip size can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a drawing showing a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a drawing showing a more detailed semiconductor memory device including a row address decoder, a row driver, and a memory array according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a configuration including a memory cell array and a driver circuit according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a sub-word driver circuit according to the first embodiment of the present invention.

FIG. 5 is a diagram showing a RAS timing generator according to the first embodiment of the present invention.

FIG. 6 is a circuit diagram of the row address decoder in FIGS. 1 and 2.

FIG. 7 is a timing chart of various signals in FIG.

FIG. 8 is an address latch circuit diagram shown in FIG. 6.

9 is a normal / redundancy switching circuit diagram in FIG.

FIG. 10 is a schematic diagram of a semiconductor memory device for explaining a conventional example.

[Explanation of symbols]

 10 DRAM 11 Memory Cell Array 12 Sub Word Driver (SWD) 13 Sense Amplifier (SA) 14 Row Address Decoder 15 Row Address Driver 16 First Logic Gate 19A-19D Address Latch Circuit 21A-21D Normal Redundancy Switching Circuit 22 Second Ethics gate section 25, 26 Switch transistor 27 Holding circuit 28, 29 Transfer gate

Claims (8)

[Claims] 1. A plurality of memory cells, a plurality of redundancy memory cells, a first driver provided corresponding to the plurality of memory cells, and a first driver provided corresponding to the plurality of redundancy memory cells. A second driver, a word line connected to the first driver, and a redundancy word line connected to the second driver. The first driver and the second driver have A semiconductor memory device, wherein address signals are commonly input. 2. The address signal is a signal having first address information corresponding to one of the plurality of memory cells in the first mode, and is used for the plurality of redundancy in the second mode. The second corresponding to one of the memory cell arrays
2. The semiconductor device according to claim 1, wherein the semiconductor device is a signal having address information of. 3. The first driver includes a plurality of first blocks provided corresponding to each of the plurality of memory cells, and the second driver includes a plurality of redundancy memory cells. A plurality of second provided corresponding to each
Block, the word line is connected to each of the plurality of first blocks of the first driver, and the sub-word line is formed of the plurality of second blocks of the second driver.
2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is connected to each of the blocks. 4. A first address signal and a second address signal from the X decoder are received, and one of a plurality of word lines is received.
A first driver for selecting one of the two, a second driver for receiving the address activation signal and driving the first address signal by the address activation signal, and first address information,
When the second address information and the determination signal are input, the first address information is output as the address activation signal in response to the determination signal of the first level in the first mode, An address decoder that outputs the second address information as the address activation signal in response to the determination signal of level 2. 5. A drive circuit for a semiconductor memory device, which receives first address information, second address information, and a determination signal and outputs an output signal, wherein the first level is determined by the determination signal at the first level. The address information of the above is output as the output signal, and the second address information is output as the output signal according to the determination signal of a second level. 6. A first logic gate section for decoding an address signal, an address latch circuit for separating and holding an output of the first logic gate section by an address latch signal and a precharge signal, and a first mode. Output of the address latch circuit and a switching circuit that switches the address signal in the second mode by a determination signal, and an output of the switching circuit is activated by an address enable signal to generate row address decode signals for a plurality of memory cell arrays. An address decoder having a second logic gate section to be created, and by separating and holding the decode signal in the first mode, the address decoder in the first mode and the second mode A drive circuit for a semiconductor memory device, wherein a decode signal is output as the same. 7. A plurality of word lines, a plurality of redundancy word lines, a word line activation signal and a first driver circuit connected to the plurality of signal lines, and a redundancy word line activation signal. A semiconductor memory device having a second driver circuit connected to the plurality of signal lines, wherein the first driver circuit includes the plurality of signals when the word line activation signal takes an activation level. Driving one of the plurality of word lines in response to information on the plurality of lines, the second driver circuit is configured to operate the plurality of signal lines when the redundancy word line activation signal takes an activation level. A semiconductor memory device characterized by driving one of the plurality of redundancy word lines in response to the above information. 8. The word line is a sub word line, the word line activation signal is a main word line, and the redundancy word line activation signal is a redundancy main word line. Semiconductor device.