JPH09218386A - Driving circuit of display device and display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve displaying quality and to reduce power consumption by changing a scanning pattern corresponding to a divided sub-selection period by means of an input signal for discriminating the selection period and an input signal for discriminating sub-multilines into which the selection period is divided. SOLUTION: An input register 105 stores a data signal from a data input control circuit 102 for one line, a write register 106 stores the data stored in the input register 105 for four lines and the data are written in a frame memory 107 by means of a timing circuit 101. Displaying data for a number of simultaneously selecting lines are simultaneously read out of the frame memory 107, a number-of-discordance deciding circuit 108 decides the number of discordance between the read-out data and the scanning patterns, the data are converted to selection data for a voltage level and all displaying data for a number of simultaneously selecting lines are processed in parallel. Read-out data for a number of simultaneously selecting lines are not changed during the selection period and only the scanning pattern is changed in the sub-selection period and outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit for a display device and a display device, and more particularly to h among a plurality of scanning lines.
The present invention relates to a drive circuit of a display device and a display device necessary for performing so-called multi-line driving in which scanning lines of a book (h is an integer of 2 or more) are simultaneously selected and displayed.

[0002]

2. Description of the Related Art A simple matrix type liquid crystal display device is
Compared with the FT active matrix type liquid crystal display device, it does not require expensive switching elements on the substrate and is inexpensive, and is therefore widely used including portable PC monitors. As a driving method of this simple matrix type liquid crystal display device, a line sequential driving method is known in which scanning lines are sequentially selected one by one. However, when a display element such as a high-speed response liquid crystal is line-sequentially driven, so-called frame response in which the luminance changes in response to one display occurs, and high contrast display cannot be performed.

Therefore, a multi-line driving method has been proposed for the purpose of eliminating the frame response and obtaining a high contrast (for example, Japanese Patent Application No. 4-84007).
JP-A-5-46127).

First, The drive waveforms of the multi-line drive method will be described, and then the drive circuit will be described.

Driving waveforms in the case of driving the simple matrix type liquid crystal display device by simultaneously selecting four scanning lines among such driving methods using the display device of FIG. 14 and the voltage waveform diagram of FIG. Will be explained.

In the display device of FIG. 14, scanning lines (X1 to Xn) and signal lines (Y1 to Ym) are formed on two transparent substrates. This is a display element that holds a liquid crystal at a position where the scanning line and the signal line are orthogonal to each other and forms a pixel, and is further configured by a scanning line driving circuit and a signal line driving circuit.

The voltage waveform for driving this display device is as shown in FIG.

The voltage waveforms applied to the scanning lines are appropriately selected from three (+ V1, 0, -V1) voltage levels according to a scanning pattern defined by a preselected orthogonal function system, and four scanning lines are selected. Applied to each line (Fig. 15)
(A)).

Further, the scanning pattern at this time is compared with the display pattern determined by the data displayed on the pixels on the selected line, and the voltage level (-V3, -V2, 0, + V2) determined by the number of mismatches. , + V3) is applied to each signal line from the signal line drive circuit. The number of voltage levels is the number obtained by adding 1 to the number of simultaneously selected scanning lines. Since four scanning lines are simultaneously selected, five levels of voltage are required.

The liquid crystal is driven by the voltage applied to the scanning line and the signal line.

The procedure for determining the voltage level applied to the signal line will be described below.

The scanning pattern is + V1 (+), the selection voltage is -V1 (-), and the display pattern is ON display data (+) and OFF display data (-). ). The number of disagreements is not taken into consideration during the non-selection period.

In FIG. 15, the period required to display one screen is one frame period, the period required to select all the scanning lines once is one field period, and the scanning line is selected once. One selection period is the period required to do this.
Here, H1st in FIG. 15 is the first selection period, and H2nd
Is the second selection period. Also, f1st is the first field period and f2nd is the second field period. Further, F1st is the first frame period.

In the case of FIG. 15, since the scanning pattern of 4 lines (X1 to X4) selected for H1st of f1st is set in advance as shown in (a), it is always (++) regardless of the state of the display screen. -+). Considering the case of performing full-screen on-display, (pixel (X1, Y1), pixel (X2, Y1), pixel (X3, Y1) and pixel (X4, Y1)
The display pattern in the first column corresponding to (1)) is (++++
+). When comparing both patterns in order, the first,
The second and fourth have the same polarity, and the third has the different polarity. That is, the number of mismatches is 1. When the number of mismatches is 1, -V2 is selected from among five voltage levels (+ V3, + V2, 0, -V2, -V3). By doing this, + V1
In the case of scanning lines X1, X2 and X4 in which is selected,
The voltage applied to the liquid crystal element is increased by the selection of V2, while it is -V in the case of the scanning line X3 in which -V1 is selected.
By selecting 2, the voltage applied to the liquid crystal element becomes low.
The voltage applied to this signal line corresponds to the vector weight at the time of orthogonal transformation, and the voltage level is set so that the true display pattern can be reproduced by adding all the weights to the four scanning patterns. . Similarly, when the number of mismatches is 0, -V3 is selected, when the number of mismatches is 2, 0 is selected, when the number of mismatches is 3, + V2 is selected, and when the number of mismatches is 4, + V3 is selected.
V2 and V3 are set so that the voltage ratio is (V2: V3 = 1: 2).

In the same procedure, the number of mismatches of the signal line columns Y2 to Ym is determined for the four scanning lines X1 to X4, and the obtained selection voltage data is transferred to the signal line drive circuit. , The voltage determined by the above procedure is applied during the first selection period.

Similarly, when the above procedure is repeated for all the scanning lines (X1 to Xn), f1st ends.

Similarly, for f2nd, f3rd and f4th, when the above procedure is repeated for all scanning lines, F1st ends and the entire screen can be displayed.

According to the above procedure, the voltage waveform applied to the signal line (Y1) when the entire surface is turned on is as shown in (b), and the voltage waveform applied to the pixel (X1, Y1) is
(C). The scan pattern is shown in Table 1.

[0019] The 1st line, 2nd line, 3rd line, and 4th line in the table indicate four scanning lines that are simultaneously selected. Also,
By the inversion signal, the scan pattern abcd is
And-are inverted, but here for simplicity,
The case where one frame is displayed without being inverted is shown.

In each of the scanning lines X1 to X4, the pattern a is displayed by H1st of f1st and the pattern b is displayed by f2n.
The pattern c is displayed as H1st of d3, the pattern c is displayed as H1st of f3rd, and the pattern d is displayed as H1st of f4th.

Next, a circuit example of the multi-line driving method is as follows.
It is configured as shown in FIG. 16 in JP-A-5-46127.

In this circuit example, the display data read from the RAM 1611 and arranged in parallel for the number of simultaneously selected lines are subjected to exclusive OR and addition by the exclusive OR and addition 1614. Is calculated and the data is transferred to the shift register 1615. The clock signal 1604 used for this transfer is a clock divided into parallel inputs. When all the data corresponding to the total number of signal lines is prepared, the data is transferred in parallel from the shift register 1615 to the latch 1616, and the number of simultaneous selections + 1 level driver 1617 is based on this data.
Applies a voltage to the signal line to the liquid crystal panel 1621.

In the case of such a circuit configuration, the number of simultaneous selections +
Before the timing of applying a voltage to the signal line, the 1-level driver 1617 performs all data processing of the total number of signal lines × the number of scanning lines to be simultaneously selected. Must be entered within.

The applicant of the present invention further suppresses the display unevenness in the signal line direction, and even when the display content changes momentarily, the display unevenness in the signal line direction does not become severe and flicker does not occur. . No display unevenness in the scanning line direction occurs. Therefore, the following driving method is proposed.

FIG. 17 shows voltage waveforms when four lines of the proposed driving method are simultaneously selected. The difference from FIG. 15 is that each selection period (H1st, H2nd, H3rd, H4th) is further divided into two, and divided sub-selection periods (S1, S2,
S3, S4, S5, S6, S7, S8).
By this division, the influence of the spike-like voltage from the scan signal applied to the adjacent scan line can be replaced within the divided sub-selection period so as to cancel out within a certain period (one frame in FIG. 15).

In FIG. 17, the voltage waveforms applied to the scanning lines X2 and X3 are falling and rising in the periods S1 and S2, respectively. Also, for example, looking at the voltage waveform of the scanning line X2, the spike-like waveform shows that the rising spike waveform 1703 and the falling spike waveform 17
When 04 are added one by one, and summed as an effective value voltage for one frame, the influence of this spike-like waveform disappears.

In FIG. 17, scanning lines X1 to X4 have S1
When the patterns shown in Table 1 are sequentially displayed from S to S8, ab, c
The order is d, ba, dc.

In the divided sub-selection period, the same display data is displayed by changing the scanning pattern, so that the effective value voltage applied to the display element is made uniform in a short period.

This homogenization will be described by taking simultaneous selection of four lines as an example.

Adjacent divided sub-selection periods (for example, S1
And S2) are orthogonal to each other, so that the voltage applied to the display element is made uniform. For example, even if the 0 potential is selected in the period S1, the V3 potential is always selected in the period S2. Further, when the V2 potential is selected in the period S1, in the period S2,
Only V2 potential or -V2 potential is selected. This is because the same data is displayed orthogonally by different scanning patterns.

Therefore, even if it is not divided even within a short period of combining the periods S1 and S2, only the V3 potential may be selected. However, when the V3 potential is selected, it is combined with the 0 potential and other V2 potentials are selected. The difference between the effective voltage applied to the display element and that when the potential or -V2 potential is selected becomes small.

As described above, the multi-line driving in which the scanning pattern is changed in the sub-selection period obtained by dividing the selection period improves the display image quality. Hereinafter, the multi-line drive that changes the scanning pattern in this sub-selection period is referred to as divided sub-multi-line drive.

[0033]

However, in the same driving circuit as the conventional one, when the divided sub-multiline driving is performed, all the data are input to the shift register 1615 by the clock signal 1604 in each divided sub-selection period. Must. For this reason, when the number of divisions is set to 2, the power consumption is doubled because double transfer is performed. As described above, there is a problem that the larger the number of divisions, the larger the power consumption becomes.

[0034]

A drive circuit for a display device according to the present invention comprises: a) a first substrate having a plurality of scanning lines, a second substrate having a plurality of signal lines, the scanning lines and the signals. A driving circuit of a display device having a plurality of display elements selected by a line, and b) selecting simultaneously h scanning lines (h is an integer of 2 or more) from the plurality of scanning lines. In the drive circuit for driving the display element according to the above, c) a selection voltage (V1, -V1) is applied during a selection period, and a scanning voltage waveform that applies a non-selection signal (0V) is applied during a non-selection period, d) reading the display data corresponding to the selected scanning line in the selection period, e) providing a sub-selection period that is a further division of the selection period, and f) a sub-selection period that is divided in the selection period, Different scan patterns for the same display data Determining the number of mismatches, to determine the voltage applied to the signal line, g) and performs the driving of changing the scan pattern in the sub-selection period is divided in the selection period.

Further, it is characterized in that a signal (SLP) for distinguishing the divided sub-selection periods is inputted.

Further, it is characterized in that a scan pattern circuit for generating a scan pattern corresponding to the divided sub-selection periods is provided inside the signal line drive circuit.

In order to distinguish the divided sub-selection periods, it is necessary to input the signal (LP) for distinguishing the selection periods as a signal obtained by increasing the number of pulses for timing according to the divided sub-selection periods. Characterize.

Further, it is characterized in that the reset timings of the signal line driving circuit and the scanning line driving circuit are different.

The drive circuit of the display device of the present invention is selected from a) a first substrate having a plurality of scanning lines, a second substrate having a plurality of signal lines, the scanning lines and the signal lines. A method of driving a display device having a plurality of display elements, comprising: b) driving the display elements by simultaneously selecting h scanning lines (h is an integer of 2 or more) from the plurality of scanning lines. In the drive circuit for performing: c) a selection signal (V1, -V1) is applied in the selection period, and a scanning voltage waveform is applied in the non-selection period, which gives a non-selection signal (0V), and d) the selection period. It is characterized in that a further divided sub-selection period is provided, and driving of changing the scanning pattern in the sub-selection period obtained by dividing the selection period, e) driving without dividing the selection period, and f) can be switched.

[0040]

The drive circuit of the display device according to the first aspect suppresses display unevenness in the signal line direction, and even if the display content changes moment by moment, the display unevenness in the signal line direction does not become severe. , Does not cause flicker. No display unevenness in the scanning line direction occurs. It is possible to provide a driving circuit capable of performing divided sub-multi-line driving with low power consumption.

A drive circuit of a display device according to a second aspect provides a drive circuit of a display device capable of easily performing divided sub multi-line driving by inputting a signal (SLP) for distinguishing divided sub selection periods. be able to.

The drive circuit of the display device according to claim 3 has a scan pattern circuit for generating a scan pattern corresponding to the divided sub-selection periods inside the signal line drive circuit.
It is possible to provide a drive circuit of a display device capable of generating a scanning pattern required for divided sub-multiline driving.

In order to distinguish the divided sub-selection periods, the drive circuit of the display device according to claim 4 provides the signal (LP) for distinguishing the selected periods with a pulse for timing according to the divided sub-selection periods. By inputting the increased signal, it is possible to provide a drive circuit of a display device that can perform divided sub-multi-line driving without newly providing an input terminal.

In the drive circuit of the display device according to the fifth aspect, the reset timing of the signal line drive circuit is different from that of the scanning line drive circuit, so that even if the mismatch number determination circuit in the signal line drive circuit has a latch, the divided sub circuit is divided. Multi-line drive can be performed.

According to the drive circuit of the display device of claim 6, it is possible to provide a drive circuit having a good cost performance in which a drive method can be arbitrarily selected according to display conditions.

According to the display device of the seventh aspect, it is possible to provide a display device having excellent image quality and good cost performance.

[0047]

BEST MODE FOR CARRYING OUT THE INVENTION A drive circuit for a display device according to the present invention will be specifically described below based on embodiments.

[Embodiment 1] This embodiment is an embodiment corresponding to the drive circuit of the display device according to claims 1, 2 and 3. FIG. 1 is a block diagram of a 160-output signal line driver circuit, FIG. 2 is a block diagram of a 120-output scanning line driver circuit, and FIG. 3 is a connection example of the signal line driver circuit and the scanning line driver circuit. FIG.
Is a timing diagram.

The drive circuit of the display device of the present embodiment does not change the data read in parallel from the frame memory in the selection period, and the scan pattern is sent to the mismatch number determination circuit in the divided sub-selection period within the selection period. By changing and inputting only the data, the divided sub-multi-line driving is performed with low power consumption. Since the display data is not newly read for each divided sub-selection period, the power consumption of the clock signal necessary for input / output and the processing for determining the number of mismatches is reduced and the power consumption is reduced. is there.

First, the signal line drive circuit will be described.

The signal line drive circuit shown in FIG. 1 includes a timing circuit 101, a data input circuit 102, and a row address register 1.
03, chip enable control circuit 104, input register 105, write register 106, frame memory 107, mismatch number determination circuit 108, level shifter 1
09 and a voltage selector 110. In this signal line drive circuit, the configuration in which the frame memory is incorporated has been described as an example, but the configuration is not limited to this, and the configuration in which the frame memory is provided outside may be used.

The timing circuit 101 controls all operation timings. The data input control circuit 102 rearranges the data in order to sequentially input the input data to the frame memory 107 to the input register. The row address register 1003 is
It outputs a write address and a read address of the frame memory. The chip enable control circuit controls the cascade signals (CEI, CEO) necessary for connecting the signal line drive circuits in cascade. The input register 105 is a register for storing the data signal (DATA) output from the data input control circuit 102 for one line (160 pieces). The write register 106 is a register for storing four lines (the number of simultaneously selected lines) of the data stored in the input register 105. The data for four lines (the number of simultaneously selected lines) stored in this register is the timing circuit 1
01, the data is simultaneously written in the frame memory 107. That is, the read / write operation to the frame memory is performed in units of the number of simultaneously selected lines.

Display data for the number of simultaneously selected lines is simultaneously read out from the frame memory 107, and the mismatch number determination circuit 108 determines the number of mismatches between the read data and the scanning pattern, and which of the five levels is selected. Select voltage level or convert to select data. The scanning pattern is the signal PD [1. . [0] specifies the patterns a, b, c, and d shown in Table 1 inside the mismatch number determination circuit. Discrepancy number determination circuit 108
The level shifter 109 level-shifts the selected data converted by the voltage shifter 109, and the voltage selector 110 outputs five levels (-V).
One-level voltage of 3, -V2, 0, V2, V3) is selected and output to the signal lines (Y1 to Y160).

[0054] As shown in FIG. 3, the scanning pattern signals PD [1. . 0]
Are output from the signal line drive circuit and input to the scanning line drive circuit.

The scanning line drive circuit will be described with reference to FIG.
From FIG. 2, a control circuit 20 for controlling all of this circuit
1. Shift register 2 for shifting the selected position of the scanning line
02, scan pattern signals from the control circuit 201 and shift data (SH1 to SH3) from the shift register 202.
0) is decoded and three levels of voltage (-V1, 0, V
(1) a decoder 203 which determines which data is selected, a level shifter 204 which level-shifts a signal from the decoder 203, and a voltage selector 205 which selects one level from three levels and outputs it to a scanning line Has been done.

In the case of simultaneous selection of 4 lines, 4 lines are selected in the selection period.
The signals SH1 to SH30 for each line sequentially become High, and one cycle is made in 30 selection periods. Through this cycle, the signal FS is output as a signal that outputs High for a certain period. This signal FS becomes a signal in the f (field) period.

The point of the present invention is that the reading of the frame memory is performed by using the display data for the number of simultaneously selected lines as a unit, so that the clock signal is not used for the calculation of the number of mismatches as in the conventional example.

The read data of the number of simultaneously selected lines is
It is the same during the selection period, and in the sub-selection period that is a further division of the selection period, only the scanning pattern is changed,
To output.

Is as follows.

The point is that the reading timing of the frame memory of the signal line drive circuit is such that the display data for the number of simultaneously selected lines are all processed in parallel by the non-coincidence number determination circuit 108 to reduce the power consumption. Is.

Points will be described in more detail with reference to FIG.

FIG. 4 shows a signal Y for distinguishing frame periods.
D, a signal LP for distinguishing a selection period, a signal SLP for distinguishing a sub-selection period obtained by further dividing the selection period, a signal FS for distinguishing a field period, and a data signal D
ATA, clock signal XSCL for inputting data
It is shown. To distinguish the sub-selection period,
In this embodiment, the signal SLP is input.

This timing will be described.

Signal YD, signal FS, signal LP, signal DA
The TA and the signal XSCL are the same even in the case of normal multi-line driving in which the selection period is not divided. Input DATA
The frame memory output DATA has a timing earlier than the signal YD by one selection period. However, in order to match the timing of a drive circuit having no conventional memory, a control for storing one selection period before the signal YD is stored. Is performed by the timing circuit 101.

The difference in the input timing is the signal S.
In order for LP to distinguish the sub-divided selection periods, there is a pulse for taking output timing between the signals LP. FIG. 4 shows a case where the selection period is divided into two. At this time, it can be seen that the read data from the frame memory does not change during the sub-selection period obtained by dividing the selection period. In the sub-selection period, only the scan pattern signals PD [1..0] are changing. FIG. 5 shows a scan pattern circuit that produces the scan pattern signals PD [1..0]. This scanning pattern circuit is in the timing circuit 101 of the signal line drive circuit of FIG.

This scanning pattern circuit is composed of D Philip
A field counter configured by flops 502 and 503 for counting fields, and a signal L configured by D Philip flops 505 and 506.
It is composed of a counter that counts P and the signal SLP. The timing of each part is shown in FIG. From FIG. 6, f1st is changed by scanning pattern signals PD1 and PD0.
In the field, abba., In the f2nd field,
In the cdcd ·, f3rd field, baab ·, f4th
It can be seen that in the field, the order is dccd.

Further, although the example of the simple matrix type liquid crystal panel has been described, the present invention is not limited to this, and can be applied to a display device using an MIM panel or an EL panel.

[Embodiment 2] In this embodiment, claims 4 and 5 are adopted.
It is an embodiment corresponding to the drive circuit of the display device. In the first embodiment, the signal SLP is input to distinguish the sub-selection periods. In the second embodiment, instead of newly inputting the signal SLP, the signal LP for distinguishing the selection period is input to the drive circuit corresponding to the divided sub-selection period, thereby performing the divided sub multi-line driving. is there.

FIG. 7 shows the timing when the divided sub multi-line driving is performed. The number of divisions in the selection period (H) is two. Comparing with the normal timing, it can be seen that there are two pulses of the signal LP within the selection period H. Therefore, it is possible to divide the selection period H into two and perform divided sub-multiline driving.

However, in this case, the normal timing is 2
It must be made up of doubled signal LP. FIG. 8 shows an MCLK circuit that creates a normal LP from the doubled signal LP.
In this case, the RESET signal is assumed to be generated from YD and LP NAND gates. This RESET signal and 2
Double the LP signal to the D Philip flop 801
By inputting to the R terminal and CLK terminal of, and applying the divided GATE, the same signal MCLK as LP at the normal timing is obtained.
Has been created.

Explaining with reference to FIG. 7, unlike the first embodiment, the timing of DATA read from the frame memory of the signal line drive circuit is earlier by S period than the selection period H1st. This is the mismatch number determination circuit 1 of the signal line drive circuit.
This is because if there is a latch for temporarily holding data inside 08, it is necessary to determine the data at a time that is approximately S periods earlier than the output timing.

In this case, the reset timing of the frame memory of the signal line driving circuit and the scanning line X of the scanning line driving circuit
The timing to start driving 1 is only for the S period (LP
Pulse interval) It will be a slur. In order to solve this, it is necessary to make the signal line driving circuit and the scanning line driving circuit have different signals YD for distinguishing frames.

However, it is more economical to input the same signal (YD and LP) and have different reset timings than to input different signals to the signal line driving circuit and the scanning line driving circuit. .

Therefore, it is necessary to distinguish between the reset circuit inside the timing circuit of the signal line driving circuit and the reset circuit inside the control circuit of the scanning line driving circuit.

FIG. 9 shows a reset circuit in the timing circuit of the signal line driving circuit, and FIG. 10 shows a reset circuit in the control circuit of the scanning line driving circuit. Each (a)
The circuit diagram and the timing diagram are shown in (b) and (b), respectively. Signal Y
D has a High period in which it includes two signals LP whose pulse number is doubled.

In the reset circuit of the signal line drive circuit of FIG. 2, the pulse of the first signal LP is output as reset,
The reset circuit of the scanning line drive circuit in FIG. 3 outputs the pulse of the next signal LP as a reset.

As described above, the reset timing of the reset circuit of the signal line driving circuit and the reset timing of the reset circuit of the scanning line driving circuit are different from each other, whereby divided sub-multi-line driving can be performed.

By adding the simple circuit as described above and increasing the number of pulses of the LP signal, it is possible to easily realize the drive circuit for the divided sub multi-line drive.

[Embodiment 3] This embodiment is an embodiment corresponding to the drive circuit of the display device according to claim 6.

In the first and second embodiments, a signal line driving circuit and a scanning line driving circuit for performing divided sub-multi-line driving are added,
The modified circuit has been described. This added / modified circuit was a very simple circuit.

The third embodiment shows a drive circuit capable of switching between normal multi-line drive and divided sub-multi-line drive. This is because, in the case of a display element using a low-speed response liquid crystal or the like, the normal multi-line driving has an advantage that power consumption can be reduced due to a small amount of potential switching. In the case of high-speed response, the divided sub-multi-line driving method is adopted due to the image quality. As described above, by making the driving method switchable, it is more versatile than making a new driving circuit for each driving method, so that there is an advantage that it can be mass-produced and manufactured at a low price.

The switching of the driving method is performed by changing the number of LP pulses, adding one terminal for setting the driving method to be displayed, and controlling by the signal LSEL.

FIG. 11 shows a signal line driving circuit which can switch the driving method, and FIG. 12 shows a scanning line driving circuit. FIG.
3 shows a connection example of the display device.

In the signal line drive circuit of FIG. 11, the signal LSEL is added to the timing circuit so that the signal LSEL becomes Lo.
When w, the normal timing circuit 1101 for performing the normal multi-line driving shown in FIG. 11 is selected, and the signal L
Timing circuit 1 for divided sub when SEL is High
102 is selected and the divided sub-multi-line drive shown in FIG. 17 is performed.

Similarly, in the scanning line driving circuit of FIG. 12, the signal LSEL is added to the control circuit, and the signal LSEL is added.
Is Low, the normal control circuit 1201 shown in FIG. 12 for performing the normal multi-line driving is selected, and the signal L
When SEL is High, the control circuit 1202 for the divided sub
Is selected and the divided sub-multi-line driving shown in FIG. 17 is performed.

In the entire connection example of FIG. 13, the signal LSEL
It is possible to provide a display device in which two types of driving methods can be selected with the only difference that is added.

[0087]

[Brief description of drawings]

FIG. 1 is a block diagram of a signal line drive circuit of the present invention.

FIG. 2 is a block diagram of a scanning line driving circuit of the present invention.

FIG. 3 is a diagram showing a connection example of a drive circuit of the present invention.

FIG. 4 is a diagram showing input timing of a drive circuit of the present invention.

FIG. 5 is a scanning pattern circuit diagram of the present invention.

FIG. 6 is a timing diagram of the scan pattern circuit of the present invention.

FIG. 7 is a diagram showing input timing of a drive circuit of the present invention.

FIG. 8 is a diagram showing an MCLK circuit of the present invention.

FIG. 9 is a reset circuit and timing chart of the signal line driver circuit of the present invention.

FIG. 10 is a timing diagram and a reset circuit of a scan line driver circuit of the present invention.

FIG. 11 is a block diagram of a signal line driver circuit of the present invention.

FIG. 12 is a block diagram of a scanning line driving circuit of the present invention.

FIG. 13 is a diagram showing a connection example of a driving circuit of the present invention.

FIG. 14 is a diagram of a display device.

FIG. 15 is a voltage waveform diagram of multi-line driving.

FIG. 16 is a conventional drive circuit diagram.

FIG. 17 is a voltage waveform diagram of divided sub multi-line driving.

[Explanation of symbols]

101 Timing Circuit 102 Data Control Circuit 103 Row Address Register 104 Chip Enable Control Circuit 105 Input Register 106 Write Register 107 Frame Memory 108 Mismatch Number Judgment Circuit (Decoder) 109 Level Shifter 110 Voltage Selector 201 Control Circuit 202 Shift Register 203 Decoder 204 Level Shifter 205 Voltage Selector 301 Display panel 302 Scan line driving circuit 303, 304 Signal line driving circuit 501 NAND gate 502, 503, 505, 506 DFR (D Philip flop) 504 OR gate 507, 508 EX_OR gate 801 DFR (D Philip flop) 802 AND gate 803 OR gate 804 Inverter 901 DFR (D Philip flop 902 Inverter 903 NAND gate 1001 DFR (D Philip flop) 1002 Inverter 1003 AND gate 1004 NAND gate 1101 Normal timing circuit 1102 Divided sub timing circuit 1103 Timing circuit 1104 Data control circuit 1105 Row address register 1106 Chip enable control circuit 1107 Input register 1108 Write register 1109 Frame memory 1110 Mismatch number determination circuit 1111 Level shifter 1112 Voltage selector 1201 Normal control circuit 1202 Divided sub control circuit 1203 Control circuit 1204 Shift register 1205 Decoder 1206 Level shifter 1207 Voltage selector 1301 Display panel 1302 Scan line drive circuit 1303, 130 A signal line driver circuit

Claims (7)

[Claims] 1. A) a first substrate having a plurality of scanning lines, a second substrate having a plurality of signal lines, and a plurality of display elements selected by the scanning lines and the signal lines. A driving circuit of a display device, b) a driving circuit for driving the display element by simultaneously selecting h scanning lines (h is an integer of 2 or more) from the plurality of scanning lines, and c) A selection voltage (V1, -V1) is applied during the selection period, and a scanning voltage waveform that applies the non-selection signal (0V) is applied during the non-selection period, and d) Corresponding to the scanning line selected during the selection period. Display data to be read, e) a sub-selection period provided by further dividing the selection period is provided, and f) in the sub-selection period obtained by dividing the selection period, different display patterns do not match the same display data. Judge the number and determine the voltage applied to the signal line , G) a driver circuit of a display device which is characterized in that the drive for changing the scan pattern in the sub-selection period is divided in the selection period. 2. The drive circuit for a display device according to claim 1, wherein a signal (SL) for distinguishing a sub-selection period obtained by dividing the selection period is used.
P) is input, the drive circuit of the display device characterized by the above-mentioned. 3. The display device drive circuit according to claim 1, further comprising a scan pattern circuit for generating a scan pattern corresponding to a sub-selection period inside the signal line drive circuit. . 4. The drive circuit for a display device according to claim 1, in order to distinguish the divided sub-selection periods, a signal (LP) for distinguishing the selected periods is timed according to the divided sub-selection periods. A drive circuit for a display device, wherein a pulse is input as an increased signal. 5. The drive circuit for a display device according to claim 1, wherein reset timings of the signal line drive circuit and the scanning line drive circuit are different. 6. A) a first substrate having a plurality of scanning lines, a second substrate having a plurality of signal lines, and a plurality of display elements selected by the scanning lines and the signal lines. A driving method of a display device, b) a driving circuit for driving the display element by simultaneously selecting h scanning lines (h is an integer of 2 or more) from the plurality of scanning lines, and c). A selection signal (V1, -V1) is applied to the selection period, a scan voltage waveform that applies the non-selection signal (0V) is applied to the non-selection period, and d) a sub-selection period obtained by further dividing the selection period A driving circuit of a display device, which is capable of switching between driving for changing a scanning pattern in a sub-selection period obtained by dividing a selection period, e) driving for not dividing a selection period, and f). 7. A display device comprising the drive circuit of the display device according to claim 1.